USRE37126E1 - Multilevel cascade voltage source inverter with seperate DC sources - Google Patents

Multilevel cascade voltage source inverter with seperate DC sources Download PDF

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USRE37126E1
USRE37126E1 US09/167,287 US16728798A USRE37126E US RE37126 E1 USRE37126 E1 US RE37126E1 US 16728798 A US16728798 A US 16728798A US RE37126 E USRE37126 E US RE37126E
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inverter
phase
full bridge
node
voltage
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Fang Zheng Peng
Jih-Sheng Lai
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Lockheed Martin Energy Systems Inc
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Lockheed Martin Energy Systems Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/49—Combination of the output voltage waveforms of a plurality of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/18—Arrangements for adjusting, eliminating or compensating reactive power in networks
    • H02J3/1821—Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators
    • H02J3/1835—Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators with stepless control
    • H02J3/1842—Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators with stepless control wherein at least one reactive element is actively controlled by a bridge converter, e.g. active filters
    • H02J3/1857—Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators with stepless control wherein at least one reactive element is actively controlled by a bridge converter, e.g. active filters wherein such bridge converter is a multilevel converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/10—Flexible AC transmission systems [FACTS]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/20—Active power filtering [APF]

Definitions

  • the present invention relates to a multilevel voltage source inverter with separate DC sources, and more particularly to a multilevel voltage source inverter with separate DC sources including an apparatus and a method for use in flexible AC transmission system (FACTS) applications such as compensating reactive power and voltage balancing.
  • FACTS flexible AC transmission system
  • VAR reactive power
  • SVGs Static VAR generators
  • TSCs Thyristor Switched Capacitors
  • TCRs Thyristor Controlled Reactors
  • VAR volt-ampere-reactive
  • the state of the art VAR compensating approach uses transformer coupling voltage source inverters.
  • a transformer coupling voltage source inverter comprising eight six-pulse converters connected in either a zig-zag, wye or delta configuration has a 48-pulse or a 48-step staircase inverter output voltage waveform which dramatically reduces harmonics.
  • the major problem of using this transformer coupling approach resides in the transformer as a function of harmonic neutralizing magnetics.
  • inverter a multilevel voltage source inverter
  • the transformerless multilevel inverter can reach high voltage and minimize induced harmonics as a function of inverter structure.
  • a multilevel, referred to as M-level, diode clamped inverter can reach high performance without the benefit of transformers.
  • This inverter does, however, require the implementation of additional clamping diodes.
  • These clamping diodes not only increase the cost of the system but also cause packaging/layout problems and introduce parasitic inductances into the system. Thus, for practicality, the number of levels of a conventional multilevel diode clamped inverter is typically limited to seven or nine levels.
  • the multilevel flying capacitor inverter has the capability to solve the voltage balance problems and aforementioned problems associated with the multilevel diode clamped inverters.
  • the required number of flying capacitors for an M-level inverter, provided that the voltage rating of each capacitor used is the same as the main power switches is determined by the formula, (M ⁇ 1)*(M ⁇ 2)*3/2+(M ⁇ 1).
  • M ⁇ 1 the voltage rating of each capacitor used is the same as the main power switches
  • M ⁇ 1 the voltage rating of each capacitor used is the same as the main power switches.
  • M-level diode clamped inverter requires only (M ⁇ 1) capacitors. Therefore, the flying capacitor inverter requires capacitors of substantial size compared with the conventional inverter.
  • control is very complicated and higher switching frequency is required to balance the voltages between each capacitor in the inverter.
  • a multilevel cascade inverter with separate DC sources for reactive power compensation in AC power systems which is directed toward overcoming and is not susceptible to the above limitations and disadvantages is described herein.
  • the multilevel voltage source inverter having separate DC sources eliminates the excessively large number of transformers required by conventional multipulse inverters, clamping diodes required by multilevel diode-clamped inverters and flying capacitors required by multilevel flying-capacitor inverters.
  • the multilevel voltage source inverter having separate DC sources also has the following features:
  • the multilevel voltage source inverter having separate DC sources is more suitable to high voltage, high power applications than conventional inverters;
  • the multilevel voltage source inverter having separate DC sources generates a multistep staircase voltage waveform with the switching of each device only once per line cycle, thus reaching a nearly sinusoidal output voltage approximation by increasing the number of voltage levels;
  • a multiple voltage source inverter for connecting to an AC power system comprising a plurality of full bridge inverters having a primary node and a secondary node, each of the full bridge inverters having a positive node and a negative node, each of the full bridge inverters having a voltage supporting device electrically connected in a parallel relationship between the positive node and the negative node; at least one cascade inverter phase, each of the cascade inverter phases having a plurality of the full bridge inverters, each of the cascade inverter phases having a consistent number of the full bridge inverters with respect to each phase, each of the full bridge inverters in each cascade inverter phase interconnected in a series relationship with the secondary node of one of the full bridge inverters connected to the primary node of another full bridge inverter, the series interconnection defining a first full bridge inverter and a last full bridge inverter, each of the phases having an input node at the primary node of the
  • This inverter is applicable to high voltage, high power applications such as flexible AC transmission systems ( FACTS ) including static VAR generation ( SVG ), power line conditioning, series compensation, phase shifting, voltage balancing, and fuel cell and photovoltaic utility interface systems.
  • FACTS flexible AC transmission systems
  • SVG static VAR generation
  • SVG static VAR generation
  • series compensation phase shifting
  • phase shifting phase shifting
  • voltage balancing voltage balancing
  • fuel cell and photovoltaic utility interface systems fuel cell and photovoltaic utility interface systems.
  • the multiple voltage source inverter may be configured in either a wye-connected or a delta-connected embodiment to address the requirements of multiple phase systems.
  • Yet another aspect of the present invention provides a method for inverting a plurality of DC voltage signals to approximate a sinusoidal voltage waveform comprising the steps of detecting the DC voltage levels of a plurality of DC voltage sources; averaging the DC voltage levels; comparing the average with a reference DC voltage; generating a first error signal from the comparison of the average with a reference DC voltage; comparing the average with the detected DC voltage levels; generating a second error signal from the comparison of the average with the detected DC voltage levels; generating a phase shift offset signal from the second error signal; generating an average phase shift signal from the first error signal; summing the phase shift offset signal and the average phase shift signal; detecting an AC line voltage having a period; generating a phase reference signal directly related to the period of the AC line voltage; generating a plurality of firing reference signals for a plurality of full bridge inverters using the phase reference signal and the sum of the phase shift offset signal and the average phase shift signal; determining a modulation index; providing a reference table for the modulation index
  • FIG. 1 is a schematic representation of a full bridge inverter.
  • FIG. 2 is a schematic representation of the single-phase embodiment of the multilevel DC voltage source inverter.
  • FIG. 3 is a graphical representation of the output voltage waveforms with respect to the input signals, v C1 , v C2 , v C3 and v C4 .
  • FIG. 4 is a schematic representation of the multiphase wye connected embodiment of the multilevel voltage source inverter.
  • FIG. 5 is a schematic representation of the multiphase delta connected embodiment of the multilevel voltage source inverter.
  • FIG. 6 is a control block diagram of a static VAR generatorcompensation system employing a three-phase multilevel cascade inverter having separate DC sources.
  • FIG. 7 a is a waveform representation wherein v S is the source voltage, i C is the current flowing into the inverter and v C is the inverter output voltage of the multilevel voltage source inverter used with the control system of FIG. 6 .
  • FIG. 7 b is a waverform representation wherein v Ci is the input wavform, shifted ahead by ⁇ Ci , a full bridge inverter of the multilevel voltage source inverter used with the control system of FIG. 6 .
  • FIG. 8 contains the experimental voltage waveforms showing the phase voltage results of the inverter and the line current waveform in the system of FIG. 6 at +1 kVAR output.
  • FIG. 9 contains the experimental voltage waveforms showing the phase voltages of the AC source and of the inverter and the line current waveform in the system of FIG. 6 at +1 kVAR output.
  • FIG. 10 contains the experimental voltage waveforms showing the line-to-line voltages of the AC source and of the inverter and the line current waveform of in the system of FIG. 6 at +1 kVAR output.
  • FIG. 11 contains the experimental voltage waveforms showing the phase voltages of the inverter and the line current in the system of FIG. 6 at 0 kVAR output.
  • FIG. 12 contains the experimental voltage waveforms showing the phase voltages of the inverter and the line current in the system of FIG. 6 at ⁇ 1 kVAR output.
  • FIG. 13 contains the experimental voltage waveforms showing the line-to-line voltages of the AC source and the inverter and the line current in the system of FIG. 6 at ⁇ 1 kVAR output.
  • FIG. 14 is a block diagram of a typical application of a multiphase, multilevel cascade inverter with separate DC sources connected to an AC load.
  • FIG. 1 a schematic representation showing the primary building block of the preferred embodiment of the apparatus of the present invention, a single-phase, full-bridge inverter (FBI) unit 50 .
  • a FBI unit comprises a primary node 1 and a secondary node 2 and an inverting means therebetween.
  • the inverting means comprises four switching means further comprising gate turn-off devices 10 , 20 , 30 and 40 and anti-parallel diodes 15 , 25 , 35 and 45 connected in an operable, oppositely biased, parallel relationship by conductors 17 , 18 , 27 , 28 , 37 , 38 , 47 and 48 , respectively.
  • the gate turn-off devices may be any of the components capable of switching such as gate turn-off thyristors, insulated gate bipolar transistors, power MOSFETs, MOSFET controlled thyristors, bipolar junction transistors, static induction transistors, static induction thyristors or MOSFET turn-off thyristors.
  • the first switching means is connected to the second switching means by conductors 22 and 24 through positive node 26 .
  • the second and third switching means are connected by conductors 23 and 33 through secondary node 2 .
  • the third and fourth switching means are connected by conductors 32 and 34 through negative node 36 .
  • the first and fourth switching means are connected by conductors 11 and 12 through primary node 1 .
  • a voltage supporting device 5 is connected between positive node 26 and negative node 36 by conductors 6 and 7 , respectively.
  • the voltage supporting device 5 may be any device, such as a DC voltage source or a capacitor, capable of maintaining a DC voltage for a sufficient period of time.
  • the FBI unit 50 can generate three level outputs; +V DC , 0 and ⁇ V DC at the respective primary node 1 . This is permitted by connecting the DC source 5 to the AC side of the FBI unit 50 via the four switching devices 10 , 20 , 30 and 40 . Each switching device 10 , 20 , 30 and 40 is switched, wherein switching is defined by the activation and deactivation of the respective switching device, only once per power line cycle in an alternating fashion commonly known to one of ordinary skill in the art to produce the +V DC , 0 and ⁇ V DC output voltages across the primary node 1 and the secondary node 2 . The switching action is generally controlled by an external control means using either analog or digital control signals in a manner commonly known to one of ordinary skill in the art.
  • FIG. 2 shows the single-phase embodiment 100 of the multilevel cascade inverter having separate DC voltage sources.
  • M is the number of output voltage levels generated by the multilevel cascade inverter during a half fundamental cycle.
  • FBI units 60 and 70 are interconnected between primary node 75 and secondary node 66 by conductor 51 .
  • FBI units 70 and 80 are interconnected between primary node 85 and secondary node 76 by conductor 52 .
  • FBI units 80 and 90 are interconnected between primary node 95 and secondary node 86 by conductor 53 .
  • the primary node 65 of the first FBI unit 60 in the multilevel cascade inverter functions as the output of the cascade inverter single-phase embodiment 100 .
  • the secondary node 96 of the last FBI unit 90 in the multilevel cascade inverter functions as the reference of the cascade inverter single-phase embodiment 100 .
  • the FBI units are provided with separate DC voltage sources 63 , 73 , 83 and 93 .
  • FIG. 3 shows the waveform response of the circuit shown in FIG. 2 wherein a DC voltage input was injected by independent voltage sources 63 , 73 , 83 and 93 .
  • the waveform v Cp is measured between node 65 and node 96 using the output waveforms shown as v C1 , v C2 , v C3 and v C4 , injected by 60 , 70 , 80 and 90 , respectively.
  • v C1 , v C2 , v C3 and v C4 are the respective voltage output levels of the each FBI unit in the single phase cascade inverter 100 as shown in FIG. 2 .
  • FIG. 4 shows the three-phase, wye connected embodiment 250 of the multilevel cascade inverter having separate DC voltage sources.
  • the wye connected embodiment 250 comprises three distinct phases 110 , 160 and 210 , each phase having a multilevel cascade inverter comprising a plurality of FBI units.
  • Each multilevel cascade is constructed as previously described in the single-phase embodiment discussion.
  • the primary nodes 115 , 165 and 215 of the first FBI units 120 , 170 and 220 in each phase of the multilevel cascade is the phase output for each of the respective phases 110 , 160 and 210 .
  • the secondary nodes 125 , 175 and 225 of the last FBI units 130 , 180 and 230 in each phase of the multilevel cascade are electrically connected to create a common node 200 therebetween.
  • FIG. 5 shows the three-phase, delta connected embodiment 400 of the multilevel cascade inverter having separate DC voltage sources.
  • the delta connected embodiment 400 comprises three distinct phases 260 , 310 and 360 , each phase having a multilevel cascade inverter comprising a plurality of FBI units.
  • Each multilevel cascade is constructed as previously described in the single-phase embodiment.
  • the primary nodes 265 , 315 and 365 of the first FBI units 270 , 320 and 370 in each phase of the multilevel cascade is the phase output for the respective phases 260 , 310 and 360 .
  • the primary node 265 of FBI unit 270 is electrically connected to the secondary node 375 of the FBI unit 380 by conductor 285 .
  • the primary node 315 of FBI unit 320 is electrically connected to the secondary node 275 of the FBI unit 280 by conductor 290 .
  • the primary node 365 of FBI unit 370 is electrically connected to the secondary node 325 of the FBI unit 330 by conductor 295 .
  • FIG. 6 shows a control block diagram of a SVG 405 employing a three-phase multilevel cascade inverter 410 having separate DC sources as described herein.
  • v s represents the source voltage
  • L s the source impedance
  • L C the inverter interface impedance, respectively.
  • the multilevel cascade inverter discussed in this example will be the inverter previously discussed for the multilevel, wye connected embodiment 250 . Variations therefrom utilizing other embodiments previously discussed will be obvious to one of ordinary skill in the relevant art.
  • the switching pattern table 415 contains switching timing data for the multilevel cascade inverter 410 to generate the desired phase output voltage as shown in FIG. 3 .
  • V C * is the amplitude command of the inverter output phase voltage and V Cmax is the maximum obtainable amplitude, i.e., the amplitude of the phase voltage when all switching angles, ⁇ i , are equal to zero.
  • each DC voltage supporting device in this case a capacitor, sees no real power. Even without real power imparted on the respective capacitors, the capacitor voltage can not be maintained due to switching device losses and capacitor losses. Therefore to maintain each DC capacitor voltage, the inverter must be controlled to allow some real power to influence the DC capacitors to maintain the DC command voltage V DC *.
  • the control block diagram shown in FIG. 6 includes two distinct control loops.
  • the outer loop defined by the influence of the DC command voltage V DC *, is to control total power flow to the FBI units, whereas the inner loop, defined by the feed back from the individual FBI units, is to offset power flow to the individual FBI units.
  • v s is the source voltage
  • i C is the current flowing into the inverter
  • each DC capacitor voltage can not be exactly balanced using the outer loop only. Referring to FIGS. 7 a and 7 b, if FBI unit I output voltage, v Ci , is as shown by trace 520 , then the average charge into the DC capacitor over each half cycle, the second shaded area 530 , will nearly equal zero.
  • each FBI unit DC capacitor voltage can be actively controlled by slightly shifting the switching pattern.
  • total power loss for the multilevel cascade inverter 410 is typically less than one percent.
  • V 2 is the source voltage
  • i C is the current flowing into the inverter
  • each DC capacitor voltage can not be exactly balanced using the outer loop only. Referring to FIGS. 7a and 7b, if FBI unit I output voltage, V C1 is as shown by trace 520 , then the average charge into the DC capacitor over each half cycle, the second shaded area 530 , will nearly equal zero.
  • each FBI unit DC capacitor voltage can be actively controlled by slightly shifting the switching pattern.
  • total power loss for the multilevel cascade inverter 410 is typically less than one percent.
  • the method used to control the automatic switching of the FBIs may be best described with reference to FIG. 6 .
  • the voltage supporting device DC voltage levels, V Ci are detected, summed and then averaged.
  • the average DC voltage level is then compared with a system reference DC voltage, V dc *.
  • an average phase shift signal, ⁇ C is generated from a first error signal describing the comparison between the average DC voltage level and the system reference DC voltage, V dc *.
  • the average DC voltage level is also compared with the respective detected DC voltage levels, V Ci .
  • a phase shift offset signal, ⁇ Ci is generated from a second error signal describing the comparison between the average DC voltage level and the respective detected DC voltage levels, V Ci .
  • the phase shift offset signal, ⁇ Ci , and said average phase shift signal, ⁇ C are then summed.
  • An AC line voltage, V S having a period is detected from which a phase reference signal, ⁇ 0 , directly related to the period of the AC line voltage, V S , is developed by comparison with the sum of the phase shift offset signal signal ⁇ Ci , and said average phase shift signal, ⁇ C .
  • Multiple firing reference signals, ⁇ Ci for the FBIs are generated by comparing the phase reference signal, ⁇ 0 , and the sum of phase shift offset signal, ⁇ Ci , and the average phase shift signal, ⁇ C .
  • a modulation index, MI may be selected by the user for which a corresponding reference table is provided.
  • Firing angle signals are generated for the FBIs using the firing reference signal in view of the reference table for the given modulation index, MI, whereby, the alternate activation of a plurality of gate turn-off devices in the FBIs may be controlled to construct an output voltage waveform having a sinusoidal approximation for use by an AC load.
  • I is the current rating of the inverter
  • ⁇ is the given regulation factor of the DC voltage
  • ⁇ i is the switching timing angle of FBI unit I as shown in FIG. 3 . Note that:
  • ⁇ i is calculated for each MI value.
  • a SVG system as shown in FIG. 6 having an 11-level wye-connected cascade inverter with 5 FBI units per phase was constructed having the system parameters shown in Table 1.
  • the total capacitance is calculated:
  • An SVG system using the delta connected embodiment of a 21-level cascade inverter having 10 FBI units per phase is connected directly to a 13 kV distribution system.
  • the SVG capacity is ⁇ 50 MVAR.
  • [ ⁇ 1 , ⁇ 2 . . . ⁇ i ] [0.0334, 0.1840, 0.2491, 0.3469, 0.4275, 0.5381, 0.6692, 0.8539, 0.9840, 1.1613] rad.
  • FIG. 6 and Tables 1 and 2 show the experimental configuration and the corresponding parameters.
  • the control voltages for C 2 , C 3 and C 4 uses interpolating values of ⁇ C1 and ⁇ C5 .
  • FIGS. 8, 9 and 10 show the experimental results when the SVG generates +1 kVAR reactive power.
  • FIG. 11 shows experimental results at zero VAR output.
  • FIGS. 12 and 13 show the case of generating ⁇ 1 kVAR reactive power.
  • the inverter output phase voltage is an 11-level steplike waveform and the line-to-line voltage is a 21-level steplike waveform over a half cycle.
  • Each step has the same span, which means the voltage of each DC capacitor is well controlled and balanced.
  • FIG. 12 shows the experimental waveforms to generate zero reactive power or zero current with a different DC voltage and the same modulation index as that of FIGS. 8, 9 and 10 .
  • the inverter generates ⁇ 1 kVAR of reactive power, that is, the current, I Ca , is lagging the voltage, V Sa , by 90 degrees.
  • FIG. 14 shows a circuit diagram having a multiphase, multilevel cascade inverter with separate DC sources 701 connected to an AC load 790 through smoothing inductors 760 , 770 and 780 .
  • this circuit contains a set of separate DC voltage sources 710 , 720 , 730 and 740 which feed through a multilevel cascade inverter 701 to produce a step-like AC output voltage waveform.
  • the voltage is then filtered by small smoothing inductors 760 , 770 and 780 to produce a pure sinusoidal wave for an AC load 790 .
  • the smoothing inductors 760 , 770 and 780 may be removed from the circuit because the load motor has sufficient inductance to filter the input current. Examples of typical loads comprise motor drives, actuators and appliances.
  • the DC voltage sources 710 , 720 , 730 and 740 may be obtained from any type conventional voltage source such as batteries, capacitors, photocells, fuel cells and biomass.
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