US9781372B2 - Driver and image sensing device including the same - Google Patents

Driver and image sensing device including the same Download PDF

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US9781372B2
US9781372B2 US14/497,026 US201414497026A US9781372B2 US 9781372 B2 US9781372 B2 US 9781372B2 US 201414497026 A US201414497026 A US 201414497026A US 9781372 B2 US9781372 B2 US 9781372B2
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pull
signal
driving unit
voltage
output terminal
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US20150244954A1 (en
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Min-Seok SHIN
Young-chul Sohn
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SK Hynix Inc
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SK Hynix Inc
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    • H04N5/376—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/709—Circuitry for control of the power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/74—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
    • H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N5/3658—

Definitions

  • Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a driver for driving pixels and an image sensing device including the driver.
  • image sensing devices capture images by using a semiconductor which is sensitive to the light.
  • Image sensing devices may be divided into those that use Charge Coupled Device (CCD) technology and those that use Complementary Metal Oxide Semiconductor (CMOS) technology.
  • CCD Charge Coupled Device
  • CMOS Complementary Metal Oxide Semiconductor
  • Image sensing devices with CMOS technology are being widely used because it allows an analog circuit and a digital control circuit to be directly realized on a single integrated circuit (IC).
  • Exemplary embodiments of the present invention are directed to a driver using two or more driving voltages depending on a transition section of a signal to be driven, and an image sensing device including the driver.
  • a driver includes a first level shifting unit suitable for generating a second signal which swings in a second threshold range in response to a first signal which swings in a first threshold range, a second level shifting unit suitable for generating a third signal which swings in a third threshold range in response to the second signal, and a driving unit suitable for generating a fourth signal swinging in a fourth threshold range and outputted through an output terminal in response to the second and third signals, wherein the driving unit including a first pull-up driving unit suitable for driving the output terminal with a first high-voltage in response to the second signal, a first pull-down driving unit suitable for driving the output terminal with a first low voltage in response to the third signal, a second pull-down driving unit suitable for driving the output terminal with a second low voltage which is higher than the first low voltage in response to the fourth signal and a first path coupling unit suitable for coupling the second pull-down driving unit with the output terminal in response to the second signal.
  • a driver includes a first level shifting unit suitable for generating a second signal which swings in a second threshold range in response to a first signal which swings in a first threshold range, a second level shifting unit suitable for generating a third signal which swings in a third threshold range in response to the second signal, and a driving unit suitable for generating a fourth signal swinging in a fourth threshold range and outputted through an output terminal in response to the second and third signals, wherein the driving unit including a first pull-up driving unit suitable for driving an output terminal with a first high-voltage in response to the second signal, a pull-down driving unit suitable for driving the output terminal with a first low voltage in response to the third signal, a second pull-up driving unit suitable for driving the output terminal with a second high voltage which is lower than the first high voltage in response to the fourth signal, and a path coupling unit suitable for coupling the second pull-up driving unit with the output terminal in response to the third signal.
  • an image sensing device includes a driver suitable for generating a second signal by changing a level of a first signal, wherein the driver generates the second signal based on a first voltage during a first section of a first transition section where the first signal shifts from a first logic level to a second logic level and based on a second voltage which is different from the first voltage during a second section of the first transition section; and a pixel array suitable for generating a pixel signal in response to the second signal.
  • a driver includes a first pull-up driving unit suitable for generating a second signal by driving an output terminal with a first high voltage during a first transition section where a first signal shifts from a first logic level to a second logic level, a first pull-down driving unit suitable for generating the second signal by driving the output terminal with a first low voltage during a second transition section where the first signal shifts from the second logic level to the first logic level, a second pull-up driving unit suitable for driving the output terminal with a second high voltage which is lower than the first high voltage during a first section of the first transition section, a second pull-down driving unit suitable for driving the output terminal with a second low voltage which is higher than the first low voltage during a first section of the second transition section, a first path coupling unit suitable for coupling the second pull-up driving unit with the output terminal in response to the first signal, and a second path coupling unit suitable for coupling the second pull-down driving unit with the output terminal in response to the first signal.
  • FIG. 1 is a block diagram illustrating an image sensing device in accordance with an embodiment of the present invention.
  • FIG. 2 illustrates an internal structure of a first driving circuit shown in FIG. 1 .
  • FIG. 3 illustrates an example of an internal structure of a first transmission driver shown in FIG. 2 .
  • FIG. 4 illustrates an internal structure of a pixel shown in FIG. 1 .
  • FIG. 5 illustrates another example of an internal structure of a first transmission driver shown in FIG. 2 .
  • FIG. 6 illustrates another example of an internal structure of a first transmission driver shown in FIG. 2 .
  • FIG. 7 illustrates another example of an internal structure of a first transmission driver shown in FIG. 2 .
  • FIG. 8 is a timing diagram illustrating an operation of a first transmission driver shown in FIG. 2 .
  • FIG. 1 is a block diagram illustrating an image sensing device in accordance with an embodiment of the present invention.
  • an image sensing device 100 may include a first voltage generation circuit 110 , a second voltage generation circuit 120 , a row control block 130 , and a pixel array 140 .
  • the first voltage generation circuit 110 generates a boosted voltage VPP based on a power supply voltage VDD.
  • the second voltage generation circuit 120 generates a reduced (or negative) voltage VBB based on a ground voltage VSS.
  • the row control block 130 receives the power supply voltage VDD, the boosted voltage VPP, the ground voltage VSS and the reduced voltage VBB, and generates first to m th transmission signals TX 0 to TXm ⁇ 1, first to m th reset signals RX 0 to RXm ⁇ 1 and first to m th selection signals SX 0 to SXm ⁇ 1 in response to first to m th transmission source signals TX_S 0 to TX_Sm ⁇ 1, first to m th reset source signals RX_S 0 to RX_Sm ⁇ 1 and first to m th selection source signals SX_S 0 to SX_Sm ⁇ 1.
  • the pixel array 140 outputs first to n th pixel signals PX 0 to PXn ⁇ 1 in response to the first to m th transmission signals TX 0 to TXm ⁇ 1, the first to m th reset signals RX 0 to RXm ⁇ 1 and the first to m th selection signals SX 0 to SXm ⁇ 1.
  • the first voltage generation circuit 110 may generate a boosted voltage VPP, which is higher than a power supply voltage VDD.
  • the first voltage generation circuit 110 may include a positive DC-to-DC converter.
  • the second voltage generation circuit 120 may generate a reduced voltage VBB, which is lower than a ground voltage VSS.
  • the second voltage generation circuit 120 may include a negative DC-to-DC converter.
  • the row control block 130 may include first to m th driving circuits 130 _ 1 to 130 _ m corresponding to first to m th rows 140 _ 1 to 140 _ m of the pixel array 140 .
  • the first to m th driving circuits 130 _ 1 to 130 _ m output the first to m th transmission signals TX 0 to TXm ⁇ 1, the first to m th reset signals RX 0 to RXm ⁇ 1 and the first to m th selection signals SX 0 to SXm ⁇ 1, which swing in a second threshold range, by converting levels of the first to m th transmission source signals TX_S 0 to TX_Sm ⁇ 1, the first to m th reset source signals RX_S 0 to RX_Sm ⁇ 1 and the first to m th selection source signals SX_S 0 to SX_Sm ⁇ 1 which swing in a first threshold range.
  • the first threshold range may include a range between a ground voltage VSS and a power supply
  • the first driving circuit 130 _ 1 is described below representatively.
  • FIG. 2 illustrates an internal structure of the first driving circuit 130 _ 1 shown in FIG. 1 .
  • the first driving circuit 130 _ 1 may include a first transmission driver 130 _ 11 for generating a first transmission signal TX 0 in response to a first transmission source signal TX_S 0 , a first reset driver 130 _ 13 for generating a first reset signal RX 0 in response to a first reset source signal RX_S 0 and a first selection driver 130 _ 15 for generating a first selection signal SX 0 in response to a first selection source signal SX_S 0 .
  • the first transmission driver 130 _ 11 , the first reset driver 130 _ 13 and the first selection driver 130 _ 15 may have different structures or the same structure. In the embodiment of the present invention, as an example, the first transmission driver 130 _ 11 , the first reset driver 130 _ 13 and the first selection driver 130 _ 15 have the same structure, and the first transmission driver 130 _ 11 is described below representatively.
  • FIG. 3 illustrates an example of the internal structure of the first transmission driver 130 _ 11 shown in FIG. 2 .
  • the first transmission driver 130 _ 11 may include a first level shifting unit 130 _ 11 A, a second level shifting unit 130 _ 11 B, a first pull-up driving unit 130 _ 11 C, a second pull-up driving unit 130 _ 11 D, a first path coupling unit 130 _ 11 E, a first pull-down driving unit 130 _ 11 F, a second pull-down driving unit 130 _ 11 G, and a second path coupling unit 130 _ 11 H.
  • the first level shifting unit 130 _ 11 A generates a first transmission pull-up signal TX_P 0 which swings between a ground voltage VSS and a boosted voltage VPP in response to the first transmission source signal TX_S 0 which swings between the ground voltage VSS and a power supply voltage VDD.
  • the second level shifting unit 130 _ 11 B generates a first transmission pull-down signal TX_B 0 which swings between a reduced voltage VBB and the power supply voltage VDD in response to the first transmission pull-up signal TX_P 0 .
  • the first pull-up driving unit 130 _ 11 C drives an output terminal VOUT 0 of the first transmission signal TX 0 with the boosted voltage VPP in response to the first transmission pull-up signal TX_P 0 .
  • the second pull-up driving unit 130 _ 11 D drives the output terminal VOUT 0 with the power supply voltage VDD in response to the first transmission signal TX 0 .
  • the first path coupling unit 130 _ 11 E is coupled between the second pull-up driving unit 130 _ 11 D and the output terminal VOUT 0 and selectively couples the second pull-up driving unit 130 _ 11 D with the output terminal VOUT 0 in response to the first transmission pull-down signal TX_B 0 .
  • the first pull-down driving unit 130 _ 11 F drives the output terminal VOUT 0 with the reduced voltage VB in response to the first transmission pull-down signal TX_B 0 .
  • the second pull-down driving unit 130 _ 11 G drives the output terminal VOUT 0 with the ground voltage VSS in response to the first transmission signal TX 0 .
  • the second path coupling unit 130 _ 11 H is coupled between the second pull-down driving unit 130 _ 11 G and the output terminal VOUT 0 and selectively couples the second pull-down driving unit 130 _ 11 G with the output terminal VOUT 0 in response to the first transmission pull-up signal TX_P 0 .
  • first and second level shifting units 130 _ 11 A and 130 _ 11 B are widely known to those skilled in the art, detailed descriptions thereon will omitted.
  • the first pull-up driving unit 130 _ 11 C and the first pull-down driving unit 130 _ 11 F may supply the predetermined voltages VPP and VBB to the output terminal VOUT 0 during a transition section of the first transmission signal TX 0 as main driving units of the first transmission driver 130 _ 11 .
  • the first pull-up driving unit 130 _ 11 C may include a PMOS transistor where the first transmission pull-up signal TX_P 0 is inputted to its gate, and its source and drain are coupled between a boosted voltage VPP terminal and the output terminal VOUT 0 .
  • the first pull-down driving unit 130 _ 11 F may include an NMOS transistor where the first transmission pull-down signal TX_B 0 is inputted to its gate, and its source and drain are coupled between a reduced voltage VBB terminal and the output terminal VOUT 0 .
  • the second pull-up driving unit 130 _ 11 D and the second pull-down driving unit 130 _ 11 G supplies the predetermined voltages VDD and VSS to the output terminal VOUT 0 during a first section of the transition section of the first transmission signal TX 0 as pre-driving units of the first transmission driver 130 _ 11 .
  • the second pull-up driving unit 130 _ 11 D may include a PMOS transistor where the first transmission signal TX 0 is inputted to its gate, and its source and drain are coupled between a power supply voltage VDD terminal and the output terminal VOUT 0 .
  • the second pull-down driving unit 130 _ 11 G may include an NMOS transistor where the first transmission signal TX 0 is inputted to its gate, and its source and drain are coupled between a ground voltage VSS terminal and the output terminal VOUT 0 .
  • the second pull-up driving unit 130 _ 11 D and the second pull-down driving unit 130 _ 11 G may drive the output terminal VOUT 0 during the first section of the transition section of the first transmission signal TX 0 while the first pull-up driving unit 130 _ 11 C and the first pull-down driving unit 130 _ 11 F drive the output terminal VOUT 0 during the transition section of the first transmission signal TX 0 .
  • first pull-up driving unit 130 _ 11 C and the second pull-up driving unit 130 _ 11 D, or the first pull-down driving unit 130 _ 11 F and the second pull-down driving unit 130 _ 11 G are turned on during the first section of the transition section, and the first pull-up driving unit 130 _ 11 C or the first pull-down driving unit 130 _ 11 F is turned on during a second section of the transition section.
  • the ripple occurring in the levels of the boosted voltage VPP and the reduced voltage VBB, which are driving voltages, may decrease.
  • the driving capability of the second pull-up driving unit 130 _ 11 D becomes better than the driving capability of the first pull-up driving unit 130 _ 11 C.
  • the threshold voltage of the second pull-down driving unit 130 _ 11 G is designed to be lower than the threshold voltage of the first pull-down driving unit 130 _ 11 F, the driving capability of the second pull-down driving unit 130 _ 11 G becomes better than the driving capability of the first pull-down driving unit 130 _ 11 F. Therefore, as the driving capability is controlled as described above, the ripple occurring in the levels of the boosted voltage VPP and the reduced voltage VBB during the first section of the transition section may decrease greatly.
  • the first path coupling unit 130 _ 11 E selectively couples and decouples the second pull-up driving unit 130 _ 11 D with/from the output terminal VOUT 0 so that the second pull-up driving unit 130 _ 11 D may supply the power supply voltage VDD to the output terminal VOUT 0 during the first section of the transition section.
  • the second path coupling unit 130 _ 11 H selectively couples and decouples the second pull-down driving unit 130 _ 11 G with/from the output terminal VOUT 0 so that the second pull-down driving unit 130 _ 11 G may supply the ground voltage VSS to the output terminal VOUT 0 during the first section of the transition section.
  • the pixel array 140 includes a plurality of pixels 140 _ 1 _ 1 to 140 _ m _ n arranged in rows and columns.
  • the pixel array 140 is controlled on a basis of rows 140 _ 1 to 140 _ m by the row control block 130 .
  • pixels 140 _#_ 1 to 140 _#_ n included in one of the rows 140 _ 1 to 140 _ m share a corresponding transmission signal TX#, a corresponding reset signal RX#, and a corresponding selection signal SX#.
  • pixels 140 _ 1 _ 1 to 140 _ 1 _ n included in a first row 140 _ 1 share a first transmission signal TX 0 , a first reset signal RX 0 and a first selection signal SX 0 , and output first to n th pixel signals PX 0 to PXn ⁇ 1 simultaneously in response to the first transmission signal TX 0 , the first reset signal RX 0 and the first selection signal SX 0 .
  • the internal structure of the pixel is described below.
  • one pixel 140 _ 1 _ 1 is described below representatively because the pixels 140 _ 1 _ 1 to 140 _ m _ n have the same structure.
  • FIG. 4 illustrates the internal structure of the pixel 140 _ 1 _ 1 .
  • the pixel 140 _ 1 _ 1 has a general 4-transistor structure and may include a photodiode PD, a transmission transistor TXTR, a reset transistor RXTR, an amplification transistor DXTR, and a selection transistor SXTR.
  • the transmission transistor TXTR is controlled based on the first transmission signal TX 0
  • the reset transistor RXTR is controlled based on the first reset signal RX 0
  • the selection transistor SXTR is controlled based on the first selection signal SX 0 . Since the photodiode PD, the transmission transistor TXTR, the reset transistor RXTR, the amplification transistor DXTR and the selection transistor SXTR do not form the basis of the present invention, a detailed description on these units has been omitted.
  • FIGS. 5 to 7 illustrate other examples of the internal structure of the first transmission driver 130 _ 11 shown in FIG. 2 .
  • the same components shown in FIGS. 5 to 7 and in FIG. 3 are represented by the same reference numerals.
  • the first transmission driver 130 _ 11 may further include a first delay unit 130 _ 11 I, a second delay unit 130 _ 11 J, a first voltage limit unit 130 _ 11 K and a second voltage limit unit 130 _ 11 L in comparison with FIG. 3 .
  • the first delay unit 130 _ 11 I, the second delay unit 130 _ 11 J, the first voltage limit unit 130 _ 11 K and the second voltage limit unit 130 _ 11 L may be the components that may improve the performance of the first transmission driver 130 _ 11 in accordance with the embodiment of the present invention.
  • the first delay unit 130 _ 11 I generates a first transmission pull-up delay signal TX_PD 0 by delaying the first transmission pull-up signal TX_P 0 and outputs the first transmission pull-up delay signal TX_PD 0 to the first pull-up driving unit 130 _ 11 C. This is to control the first pull-up driving unit 130 _ 11 C to be turned on later than the second pull-up driving unit 130 _ 11 D when the first transmission source signal TX_S 0 transitions from a power supply voltage VDD level to a ground voltage VSS level.
  • the first delay unit 130 _ 11 I separates operation sections of the first and second pull-up driving units 130 _ 11 C and 130 _ 11 D so that the first and second pull-up driving units 130 _ 11 C and 130 _ 11 D are turned on step by step. Therefore, the second pull up driving unit 130 _ 11 D is turned on during a first section of a first transition section where the first transmission source signal TX_S 0 transitions from the power supply voltage VDD level to the ground voltage VSS level, and the first pull-up driving unit 130 _ 11 C is turned on during a second section of the first transition section.
  • the second delay unit 130 _ 11 J generates a first transmission pull-down delay signal TX_BD 0 by delaying the first transmission pull-down signal TX_B 0 and outputs the first transmission pull-down delay signal TX_BD 0 to the first pull-down driving unit 130 _ 11 F. This is to control the first pull-down driving unit 130 _ 11 F to be turned on later than the second pull-down driving unit 130 _ 11 G when the first transmission source signal TX_S 0 transitions from the ground voltage VSS level to the power source voltage VDD level.
  • the second delay unit 130 _ 11 J separates operation sections of the first and second pull-down driving units 130 _ 11 F and 130 _ 11 G so that the first and second pull-down driving units 130 _ 11 F and 130 _ 11 G are turned on step by step. Therefore, the second pull-down driving unit 130 _ 11 G is turned on during a first section of a second transition section where the first transmission source signal TX_S 0 transitions from the ground voltage VSS level to the power supply voltage VDD level, and the first pull-down driving unit 130 _ 11 F is turned on during the second section of the second transition section.
  • the first voltage limit unit 130 _ 11 K is coupled between the first pull-up driving unit 130 _ 11 C and the output terminal VOUT 0 and limits the voltage difference between both terminals of the first pull-up driving unit 130 _ 11 C in response to the ground voltage VSS. This is in order to secure the operation reliability of the first pull-up driving unit 130 _ 11 C by limiting the voltage swing range of the first pull-up driving unit 130 _ 11 C.
  • the first voltage limit unit 130 _ 11 K may include a PMOS transistor where the ground voltage VSS is inputted to its gate, and its source and drain are coupled between the first pull-up driving unit 130 _ 11 C and the output terminal VOUT 0 .
  • the second voltage limit unit 130 _ 11 L is coupled between the first pull-down driving unit 130 _ 11 F and the output terminal VOUT 0 and limits the voltage difference between both terminals of the first pull-down driving unit 130 _ 11 F in response to the power supply voltage VDD. This is to secure the operation reliability of the first pull-down driving unit 130 _ 11 F by limiting the voltage swing range of the first pull-down driving unit 130 _ 11 F.
  • the second voltage limit unit 130 _ 11 L may include an NMOS transistor where the power supply voltage VDD is inputted to its gate, and its source and drain are coupled between the first pull-down driving unit 130 _ 11 F and the output terminal VOUT 0 .
  • the first transmission driver 130 _ 11 does not include the second pull-down driving unit 130 _ 11 G and the second path coupling unit 130 _ 11 H shown in FIG. 3 .
  • the first transmission driver 130 _ 11 may be designed to decrease a ripple occurring in the level of the boosted voltage VPP as including the second pull-up driving unit 130 _ 11 D and the first path coupling unit 130 _ 11 E.
  • the first transmission driver 130 _ 11 does not include the second pull-up driving unit 130 _ 11 D and the first path coupling unit 130 _ 11 E shown in FIG. 3 .
  • the first transmission driver 130 _ 11 may be designed to decrease a ripple occurring in the level of the reduced voltage VBB as including the second pull-down driving unit 130 _ 11 G and the second path coupling unit 130 _ 11 H.
  • the first voltage generation circuit 110 generates a boosted voltage VPP based on a power supply voltage VDD, and the second voltage generation circuit 120 generates a reduced voltage VBB based on a ground voltage VSS.
  • the row control block 130 generates the first to m th transmission signals TX 0 to TXm ⁇ 1 corresponding to the first to m th transmission source signals TX_S 0 to TX_Sm ⁇ 1, the first to m th reset signals RX 0 to RXm ⁇ 1 corresponding to the first to m th reset source signals RX_S 0 to RX_Sm ⁇ 1, and the first to m th selection signals SX 0 to SXm ⁇ 1 corresponding to the first to m th selection source signals SX_S 0 to SX_Sm ⁇ 1 based on the power supply voltage VDD, the boosted voltage VPP, the ground voltage VSS and the reduced voltage VBB.
  • the first driving circuit 130 _ 1 generates the first transmission signal TX 0 , the first reset signal RX 0 and the first selection signal SX 0 which swing between the reduced voltage VBB and the boosted voltage VPP by converting levels of the first transmission source signal TX_S 0 , the first reset source signal RX_S 0 and the first selection source signal SX_S 0 , which swing between the ground voltage VSS and the power supply voltage VDD.
  • the capacitive load increases on signal lines for transmitting the signals TX 0 , RX 0 and SX 0 . Since the current load increases in the first and second voltage generation circuits 110 and 120 , a ripple occurs in the levels of the boosted voltage VPP and the reduced voltage VBB when the signals TX 0 , RX 0 and SX 0 transition. As a result, electric coupling occurs in a floating diffusion region FD of the pixels 140 _ 1 _ 1 to 140 _ 1 _ n , and consequently, a row-wise temporal noise occurs in the image sensing device 100 .
  • the first driving circuit 130 _ 1 in accordance with an embodiment of the present invention selectively uses the ground voltage VSS, the reduced voltage VBB, the power supply voltage VDD and the boosted voltage VPP when generating the first transmission signal TX 0 , the first reset signal RX 0 and the first selection signal SX 0 .
  • This is described in detail below with reference to FIG. 8 , and for a simple description, an operation of the first transmission driver 130 _ 11 shown in FIG. 3 is representatively described below.
  • FIG. 8 is a timing diagram illustrating an operation of the first transmission driver 130 _ 11 .
  • the first transmission driver 130 _ 11 drives the first transmission signal TX 0 based on the ground voltage VSS and the reduced voltage VBB during a first section A of a second transition section where the first transmission source signal TX_S 0 transitions from the ground voltage VSS to the power supply voltage VDD, and it drives the first transmission signal TX 0 based on the reduced voltage VBB during the second section B of the second transition section.
  • the first and second pull-down driving units 130 _ 11 F and 130 _ 11 G are turned on simultaneously during the first section A of the second transition section.
  • the first pull-down driving unit 130 _ 11 F drives the output terminal VOUT 0 with the reduced voltage VBB during the first section A
  • the second pull-down driving unit 130 _ 11 G drives the output terminal VOUT 0 with the ground voltage VSS during the first section A.
  • the first and second pull-down driving units 130 _ 11 F and 130 _ 11 G sink the current simultaneously during the first section A of the second transition section, the current load is spread on the reduced voltage VBB terminal and the ground voltage VSS terminal.
  • the threshold voltage of the second pull-down driving unit 130 _ 11 G is designed to be lower than the threshold voltage of the first pull-down driving unit 130 _ 11 F, the current load of the reduced voltage VBB terminal may greatly decrease. Meanwhile, during the second section B of the second transition section, the first pull-down driving unit 130 _ 11 F is turned on, and the second pull-down driving unit 130 _ 11 G is turned off. In other words, the first pull-down driving unit 130 _ 11 F only drives the output terminal VOUT 0 with the reduced voltage VBB during the second section B.
  • the first transmission driver 130 _ 11 drives the first transmission signal TX 0 based on the power supply voltage VDD and the boosted voltage VPP during a first section C of a first transition section where the first transmission source signal TX_S 0 transitions from the power supply voltage VDD to the ground voltage VSS, and it drives the first transmission signal TX 0 based on the power supply voltage VDD during the second section D of the first transition section.
  • the first and second pull-up driving units 130 _ 11 C and 130 _ 11 D are turned on simultaneously during the first section C of the first transition section.
  • the first pull-up driving unit 130 _ 11 C drives the output terminal VOUT 0 with the boosted voltage VPP during the first section C
  • the second pull-up driving unit 130 _ 11 D drives the output terminal VOUT 0 with the power supply voltage VDD during the first section C.
  • the first and second pull-up driving units 130 _ 11 C and 130 _ 11 C source the current simultaneously during the first section C of the first transition section, the current load is spread on the boosted voltage VPP terminal and the power source voltage VDD terminal.
  • the threshold voltage of the second pull-up driving unit 130 _ 11 D is designed to be lower than the threshold voltage of the first pull-up driving unit 130 _ 11 C, the current load of the boosted voltage VPP terminal may greatly decrease. Meanwhile, during the second section D of the first transition section, the first pull-up driving unit 130 _ 11 C is turned on, and the second pull-up driving unit 130 _ 11 D is turned off. In other words, the first pull-up driving unit 130 _ 11 C only drives the output terminal VOUT 0 with the boosted voltage VPP during the second section D.
  • the image sensing device may reduce row-wise temporal noise by decreasing the ripple occurring in levels of the boosted voltage VPP and the reduced voltage VBB when a transmission signal, a reset signal and a selection signal are generated.
  • a pixel of a 4-transistor structure is described in the embodiments of the present invention, the inventive concept is not limited to this and another transistor structure is possible in accordance with this invention, e.g., 1-transistor structure, 3-transistor structure, 5-transistor structure, and so on.
  • pixel driving signals e.g., a transmission signal, a reset signal, a selection signal, and so on, are generated to correspond to the structure of the pixel and may be altered accordingly.
  • the driver is applied to an image sensing device in the embodiments of the present invention, this is not a limitation and should be obvious that the driver may be applied to other fields such as a semiconductor memory device.

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KR102491136B1 (ko) * 2015-12-18 2023-01-25 에스케이하이닉스 주식회사 수신 장치, 이를 이용하는 반도체 장치 및 시스템
US11394910B2 (en) 2016-01-19 2022-07-19 SK Hynix Inc. Image sensing device generating pixel signal with boost voltage and operating method thereof
KR102476751B1 (ko) * 2018-03-29 2022-12-13 에스케이하이닉스 주식회사 전자 장치
US10785437B2 (en) * 2018-11-07 2020-09-22 Semiconductor Components Industries, Llc Area and power efficient multi-voltage row driver circuitry for image sensors
KR102594977B1 (ko) * 2019-04-09 2023-10-30 에스케이하이닉스 주식회사 신호전달회로 및 이를 포함하는 반도체 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5248906A (en) * 1992-06-12 1993-09-28 Advanced Micro Devices, Inc. High speed CMOS output buffer circuit minimizes output signal oscillation and steady state current
US5406147A (en) * 1993-06-18 1995-04-11 Digital Equipment Corporation Propagation speedup by use of complementary resolver outputs in a system bus receiver
KR20070013509A (ko) 2005-07-26 2007-01-31 삼성전기주식회사 Ｃｍｏｓ 이미지 센서의 단위 화소
KR20090055771A (ko) 2007-11-29 2009-06-03 주식회사 동부하이텍 이미지 센서
US20130342259A1 (en) * 2012-06-20 2013-12-26 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and switching device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100197557B1 (ko) * 1995-12-11 1999-06-15 윤종용 광역 전압동작 특성을 가지는 반도체 장치
KR100810611B1 (ko) * 2006-05-15 2008-03-07 삼성전자주식회사 반도체 장치의 레벨 쉬프팅 회로
KR101512336B1 (ko) * 2008-12-29 2015-04-15 삼성디스플레이 주식회사 게이트 구동회로 및 이를 구비한 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5248906A (en) * 1992-06-12 1993-09-28 Advanced Micro Devices, Inc. High speed CMOS output buffer circuit minimizes output signal oscillation and steady state current
US5406147A (en) * 1993-06-18 1995-04-11 Digital Equipment Corporation Propagation speedup by use of complementary resolver outputs in a system bus receiver
KR20070013509A (ko) 2005-07-26 2007-01-31 삼성전기주식회사 Ｃｍｏｓ 이미지 센서의 단위 화소
KR20090055771A (ko) 2007-11-29 2009-06-03 주식회사 동부하이텍 이미지 센서
US20130342259A1 (en) * 2012-06-20 2013-12-26 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and switching device

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