US9224461B2 - Low voltage embedded memory having cationic-based conductive oxide element - Google Patents

Low voltage embedded memory having cationic-based conductive oxide element Download PDF

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US9224461B2
US9224461B2 US13/686,507 US201213686507A US9224461B2 US 9224461 B2 US9224461 B2 US 9224461B2 US 201213686507 A US201213686507 A US 201213686507A US 9224461 B2 US9224461 B2 US 9224461B2
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cationic
conductive oxide
electrode
oxide layer
memory
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US20140146592A1 (en
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Elijah V. Karpov
Brian S. Doyle
Charles C. Kuo
Robert S. Chau
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Intel Corp
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Intel Corp
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Priority to CN201380055748.5A priority patent/CN104756246B/zh
Priority to EP13857711.9A priority patent/EP2926371B1/en
Priority to PCT/US2013/047418 priority patent/WO2014084909A1/en
Priority to KR1020157009641A priority patent/KR101805032B1/ko
Priority to TW102139956A priority patent/TWI552400B/zh
Publication of US20140146592A1 publication Critical patent/US20140146592A1/en
Priority to US14/930,393 priority patent/US9318701B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H01L45/085—
    • H01L45/1233—
    • H01L45/1266—
    • H01L45/142—
    • H01L45/145—
    • H01L45/147—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822—Sulfides, e.g. CuS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • H01L27/2436—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors

Definitions

  • Embodiments of the invention are in the field of memory devices and, in particular, low voltage embedded memory having cationic-based conductive oxide elements.
  • Nonvolatile memory based on resistance change known as RRAM/ReRAM
  • RRAM/ReRAM typically operates at voltages greater than 1V
  • high voltage (>1V) forming step typically requires a high voltage (>1V) forming step to form a filament, and typically have high resistance values limiting read performance.
  • operating voltages less than 1V and compatible with CMOS logic processes may be desirable.
  • FIG. 1 illustrates a cationic-based metal-conductive oxide-metal (MCOM) memory element, in accordance with an embodiment of the present invention.
  • MCOM metal-conductive oxide-metal
  • FIG. 2 illustrates an operational schematic representing a changing of states for the memory element of FIG. 1 , in accordance with an embodiment of the present invention.
  • FIG. 3 illustrates a schematic representation of resistance change in a cationic-based conductive oxide layer induced by changing the concentration of cation vacancies in the conductive oxide layer, using an example of material with composition of Li x CoO 2 , in accordance with an embodiment of the present invention.
  • FIG. 4 illustrates a fundamental phenomenon of a stoichiometry change for a cationic-based conductive oxide material, in accordance with an embodiment of the present invention.
  • FIG. 5 illustrates a schematic of a memory bit cell which includes a cationic-based metal-conductive oxide-metal (MCOM) memory element, in accordance with an embodiment of the present invention.
  • MCOM metal-conductive oxide-metal
  • FIG. 6 illustrates a block diagram of an electronic system, in accordance with an embodiment of the present invention.
  • FIG. 7 illustrates a computing device in accordance with one implementation of the invention.
  • Low voltage embedded memory having cationic-based conductive oxide elements is described.
  • numerous specific details are set forth, such as specific cationic-based conductive oxide material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
  • One or more embodiments of the present invention are directed to low voltage cationic conductive oxide random access memory (RAM) for embedded non-volatile memory (e-NVM) applications.
  • RAM low voltage cationic conductive oxide random access memory
  • e-NVM embedded non-volatile memory
  • one or more embodiments of described herein are directed to structures for and approaches to using low voltage embedded memory.
  • the memory is based on cationic-based conductive oxide and electrode stacks. Applications of such memory may include, but are not limited to, back end memory, embedded memory, resistive memory, random access memory, non-volatile memory, and RRAM.
  • the structural architecture of the memory is based on a junction-free arrangement, in that a non-conducting layer is not used in the functional element of the memory stack.
  • one or more embodiments include fabrication of a memory stack having a conductive oxide layer based on cationic conductivity versus an oxide-based resistive change memories where programming is driven by anionic conductivity through oxygen vacancy generation.
  • a memory element By basing a memory element on a cationic-based conductive oxide, instead of an anionic-based conductive oxide, faster programming operations may be achieved.
  • Such increase in performance may be based, at least partly, on the observation that ionic conductivities are much higher for cationic conductive oxides versus anionic conductive oxides, e.g., the ionic conductivity for lithium silicate (Li 4 SiO 4 , a cationic-based oxide) is greater that that of zirconia (ZrO 2 or ZrO x , an anionic-based oxide.
  • a cationic-based metal-conductive oxide-metal (MCOM) structure is implemented to fabricate a resistance change memory (often referred as RRAM) based architecture, e.g., instead of a metal-dielectric (insulating) oxide-metal (MIM) based structure.
  • RRAM resistance change memory
  • MIM metal-dielectric oxide-metal
  • a conventional RRAM device may be based on a metal-HfO x -metal structure.
  • FIG. 1 illustrates a cationic-based metal-conductive oxide-metal (MCOM) memory element, in accordance with an embodiment of the present invention.
  • a memory element 100 includes a first electrode 102 , a cationic-based conductive oxide layer 104 , and a second electrode 106 .
  • the memory element 100 may be included in a memory architecture via nodes 108 .
  • such a device may be placed between a bitline and a selector element such as a 1T (MOS transistor), or 2-terminal thin film selector which is connected to a wordline.
  • MOS transistor MOS transistor
  • the conductive oxide layer 104 is a cationic-based conductive oxide layer (e.g., having a thickness approximately in the range of 1-10 nanometers)
  • the first electrode 102 is composed of a noble metal
  • the second electrode 106 is reservoir cation reservoir (also referred to herein as an intercalation electrode), as will be described in greater detail below.
  • FIG. 2 illustrates an operational schematic representing a changing of states for the memory element of FIG. 1 , in accordance with an embodiment of the present invention.
  • memory element 100 may begin in a more conductive state ( 1 ), with cationic-based conductive oxide layer 104 being in a more conductive state 104 A.
  • An electrical pulse such as a duration of a positive bias ( 2 ) may be applied to provide memory element 100 in a less conductive state ( 3 ), with cationic-based conductive oxide layer 104 being in a less conductive state 104 B.
  • An electrical pulse, such as a duration of a negative bias ( 4 ) may be applied to again provide memory element 100 having the more conductive state ( 1 ).
  • Electrical pulsing may be used to change resistance of the memory element 100 .
  • Polarity applied is such as to attract active cations of in the memory layer to the intercalation electrode under negative bias.
  • a memory element includes a cationic-based conductive oxide layer sandwiched between two electrodes.
  • Resistivity of the cationic-based conductive oxide layer in low field (when device is read) is, in some embodiments, can be as low as found typical of conductive films of metal compounds, e.g. TiAlN.
  • the resistivity for such a layer is approximately in the range of 0.1 Ohm cm-10 kOhm cm when measured at low field. Resistivity of the film is tuned depending in the memory element size to achieve final resistance value in the range compatible with fast read.
  • FIG. 3 illustrates a schematic representation of resistance change in a cationic-based conductive oxide layer induced by changing the concentration of cation vacancies (such as lithium cation vacancies) in the conductive oxide layer, in accordance with an embodiment of the present invention.
  • a memory element 300 is shown as deposited (A).
  • the memory element includes a cationic-based conductive oxide layer 304 between a bottom electrode 302 and a top electrode 306 .
  • the layer 304 is a lithium cobalt oxide layer, described in greater details below, and lithium atoms and lithium vacancies are distributed as shown in (A).
  • the memory element 300 can be made more conductive. In that state, lithium atoms migrate to the top electrode 306 , while vacancies remain throughout the layer 304 .
  • the memory element upon application of a positive bias to one of the electrodes, the memory element can be made less conductive.
  • effective composition e.g., the location of lithium atoms (or cations) versus vacancies
  • effective composition e.g., the location of lithium atoms (or cations) versus vacancies
  • an applied electrical field which drives such compositional change during write operation, is tuned to values approximately in the range of 1e6-1e7 V/cm.
  • the cationic-based conductive oxide layer 304 is composed of a material suitable for cation-based mobility within the layer itself.
  • layer 304 of FIG. 3 part (A) is composed of lithium cobalt oxide (LiCoO 2 ).
  • the corresponding layer becomes lithium deficient (e.g., Li ⁇ 0.75 CoO 2 ) when a negative bias is applied and lithium atoms (e.g., as cations) migrate toward electrode 306 .
  • the corresponding layer becomes lithium rich (e.g., Li >0.95 CoO 2 ) when a positive bias is applied and lithium atoms (e.g., as cations) migrate away from electrode 306 .
  • other suitable compositions with cationic conductivity include, but are not limited to, LiMnO 2 , Li 4 TiO 12 , LiNiO 2 , LiNbO 3 , Li 3 N:H, LiTiS 2 (all of which are lithium atom or Li + mobility based), Na ⁇ -alumina (which is sodium atom or Na + mobility based), or AgI, RbAg 4 I 5 , AgGeAsS 3 (all of which are silver atom or Ag + mobility based).
  • these examples provide materials based on cation mobility or migration, which is typically much faster than anionic-based mobility or migration (e.g., for oxygen atoms or O 2 ⁇ anions).
  • one electrode (e.g., bottom electrode 302 ) in a memory element including a cationic conductive oxide layer is a noble metal based electrode.
  • suitable noble metals include, but are not limited to palladium (Pd) or platinum (Pt).
  • a memory stack includes a bottom electrode composed of an approximately 10 nanometer thick Pd layer. It is to be understood that use of the terms “bottom” and “top” for electrodes 302 and 306 need only be relative and are not necessarily absolute with respect to, e.g., an underlying substrate.
  • the other electrode (e.g., top electrode 306 ) in a memory element including a cationic conductive oxide layer is an “intercalation host” for migrating cations.
  • the material of the top electrode is a host in a sense that the material is conductive with or without the presence of the migrating cations and is not substantially altered in the absence or presence of the migrating cations.
  • the top electrode is composed of a material such as, but not limited to, graphite, or metal chalcogenides such as disulfides (e.g., TaS 2 ). Such materials are conductive as well as absorbing of cations such as Li + . This is in contrast to an electrode for an anionic based conductive oxide which may include a metal with a corresponding conductive oxide to accommodate migrating oxygen atoms or anions.
  • FIG. 4 illustrates a fundamental phenomenon of a stoichiometry change for a cationic-based conductive oxide material, in accordance with an embodiment of the present invention.
  • stoichiometric changes in a film or material layer may make all the difference between the behavior, in a relative sense, being either that of an “insulator” (higher resistivity) and that of a “metal” (lower resistivity.
  • Li >0.95 CoO 2 is more resistive (“insulator”), while Li ⁇ 0.75 CoO 2 less resistive (“metal”).
  • One of the differences of one or more embodiments described herein with respect to state of the art resistive devices is that all layers in the stack of the memory element are composed of conducting thin films.
  • the device structure for the resulting resistive memory element is different from the state of the art devices where at least one of the films is an insulator and/or dielectric film.
  • the resistivity is many orders of magnitude higher than that of metals or metal compounds and is essentially non measurable at low field until the device is formed.
  • the arrangement enables one or more of the following: (1) low voltage operation, e.g., less than 1 Volt operation; (2) elimination of the need for a one time high voltage, commonly called forming voltage, required for state of the art RRAM; and (3) low resistances (e.g., since all components are conductors) which can provide for fast read in operation of a memory device having the cationic-based MCOM structure.
  • a memory element including a cationic-based conductive oxide layer is fabricated by a process flow including a capacitor flow for which all active layers are deposited in situ to eliminate contamination related effects. Memory operation can be performed at voltages at or below DC 1V. In one embodiment, the fabricated device does not require application of initial high voltage DC sweep, e.g., as is known as first fire for conventional devices.
  • FIG. 5 illustrates a schematic of a memory bit cell 500 which includes a cationic-based metal-conductive oxide-metal (MCOM) memory element 510 , in accordance with an embodiment of the present invention.
  • MCOM metal-conductive oxide-metal
  • the cationic-based MCOM memory element 510 may include a first conductive electrode 512 with a cationic-based conductive metal oxide layer 514 adjacent the first conductive electrode 512 .
  • a second conductive electrode 516 is adjacent the cationic-based conductive metal oxide layer 514 .
  • the second conductive electrode 516 may be electrically connected to a bit line 532 .
  • the first conductive electrode 512 may be coupled with a transistor 534 .
  • the transistor 534 may be coupled with a word line 536 and a source line 538 in a manner that will be understood to those skilled in the art.
  • the memory bit cell 500 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the memory bit cell 500 . It is to be understood that a plurality of the memory bit cells 500 may be operably connected to one another to form a memory array (not shown), wherein the memory array can be incorporated into a non-volatile memory device. It is to be understood that the transistor 534 may be connected to the second conductive electrode 516 or the first conductive electrode 512 , although only the latter is shown.
  • the cationic-based conductive metal oxide layer 514 has a cationic mobility of approximately 6.25E-05 cm2/V ⁇ s, and the appropriate electrode has an intercalation time of approximately 4E-09 seconds. This corresponds to an estimated write time of approximately 4 nanoseconds for the memory bit cell 500 .
  • FIG. 6 illustrates a block diagram of an electronic system 600 , in accordance with an embodiment of the present invention.
  • the electronic system 600 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory.
  • the electronic system 600 may include a microprocessor 602 (having a processor 604 and control unit 606 ), a memory device 608 , and an input/output device 610 (it is to be understood that the electronic system 600 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments).
  • the electronic system 600 has a set of instructions that define operations which are to be performed on data by the processor 604 , as well as, other transactions between the processor 604 , the memory device 608 , and the input/output device 610 .
  • the control unit 606 coordinates the operations of the processor 604 , the memory device 608 and the input/output device 610 by cycling through a set of operations that cause instructions to be retrieved from the memory device 608 and executed.
  • the memory device 608 can include a memory element having a cationic-based conductive oxide and electrode stack as described in the present description.
  • the memory device 608 is embedded in the microprocessor 602 , as depicted in FIG. 6 .
  • FIG. 7 illustrates a computing device 700 in accordance with one implementation of the invention.
  • the computing device 700 houses a board 702 .
  • the board 702 may include a number of components, including but not limited to a processor 704 and at least one communication chip 706 .
  • the processor 704 is physically and electrically coupled to the board 702 .
  • the at least one communication chip 706 is also physically and electrically coupled to the board 702 .
  • the communication chip 706 is part of the processor 704 .
  • computing device 700 may include other components that may or may not be physically and electrically coupled to the board 702 .
  • these other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an
  • the communication chip 706 enables wireless communications for the transfer of data to and from the computing device 700 .
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 700 may include a plurality of communication chips 706 .
  • a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704 .
  • the integrated circuit die of the processor includes, or is electrically coupled with, one or more devices low voltage embedded memory having cationic-based conductive oxide and electrode stacks in accordance with implementations of the invention.
  • the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 706 also includes an integrated circuit die packaged within the communication chip 706 .
  • the integrated circuit die of the communication chip includes, or is electrically coupled with, one or more devices low voltage embedded memory having cationic-based conductive oxide and electrode stacks in accordance with implementations of the invention.
  • another component housed within the computing device 700 may contain an integrated circuit die that includes, or is electrically coupled with, one or more devices low voltage embedded memory having cationic-based conductive oxide and electrode stacks in accordance with implementations of the invention.
  • the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 900 may be any other electronic device that processes data.
  • one or more embodiments of the present invention relate generally to the fabrication of microelectronic memory.
  • the microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered.
  • One or more embodiments of the present invention relate to the fabrication of a memory element having a cationic-based conductive oxide and electrode stack for non-volatile microelectronic memory devices.
  • Such an element may be used in an embedded non-volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memory (eDRAM).
  • eDRAM embedded dynamic random access memory
  • embodiments of the present invention include low voltage embedded memory having cationic-based conductive oxide elements.
  • a material layer stack for a memory element includes a first conductive electrode.
  • a cationic-based conductive oxide layer is disposed on the first conductive electrode.
  • the cationic-based conductive oxide layer has a plurality of cation vacancies therein.
  • a second electrode is disposed on the cationic-based conductive oxide layer.
  • the cationic-based conductive oxide layer is composed of a material having cation-based mobility.
  • the material having cation-based mobility has lithium (Li + ), sodium (Na + ) or silver (Ag + ) mobility.
  • the material having cation-based mobility has lithium (Li + ) mobility and is a material such as, but not limited to, LiCoO 2 , LiMnO 2 , Li 4 TiO 12 , LiNiO 2 , LiNbO 3 , Li 3 N:H or LiTiS 2 .
  • the material having cation-based mobility has sodium (Na + ) mobility and is Na ⁇ -alumina.
  • the material having cation-based mobility has silver (Ag + ) mobility and is a material such as, but not limited to, AgI, RbAg 4 I 5 and AgGeAsS 3 .
  • the resistivity of the cationic-based conductive oxide layer is approximately in the range of 10 mOhm cm-10 kOhm when measured at a low field of approximately 0.1V.
  • the second electrode is composed of a material that is an intercalation host for cations.
  • the material that is an intercalation host for cations is one such as, but not limited to, graphite or a metal chalcogenide.
  • the first electrode is a noble metal electrode.
  • the noble metal electrode is composed of a material such as, but not limited to, palladium (Pd) or platinum (Pt).
  • a non-volatile memory device includes a first conductive electrode.
  • a cationic-based conductive oxide layer is disposed on the first conductive electrode.
  • a second electrode is disposed on the cationic-based conductive oxide layer.
  • a transistor is electrically connected to the first or the second electrode, a source line, and a word line.
  • a bit line is electrically coupled with the other of the first or the second electrode.
  • the cationic-based conductive oxide layer has a plurality of cation vacancies therein.
  • the cationic-based conductive oxide layer is composed of a material having cation-based mobility.
  • the material having cation-based mobility has lithium (Li + ), sodium (Na + ) or silver (Ag + ) mobility.
  • the material having cation-based mobility has lithium (Li + ) mobility and is one such as, but not limited to, LiCoO 2 , LiMnO 2 , Li 4 TiO 12 , LiNiO 2 , LiNbO 3 , Li 3 N:H or LiTiS 2 .
  • the material having cation-based mobility has sodium (Na + ) mobility and is Na ⁇ -alumina.
  • the material having cation-based mobility has silver (Ag + ) mobility and is one such as, but not limited to, AgI, RbAg 4 I 5 and AgGeAsS 3 .
  • the resistivity of the cationic-based conductive oxide layer is approximately in the range of 10 mOhm cm-10 kOhm when measured at a low field of approximately 0.1V.
  • the second electrode comprises a material that is an intercalation host for cations.
  • the material that is an intercalation host for cations is one such as, but not limited to, graphite or a metal chalcogenide.
  • the first electrode is a noble metal electrode.
  • the noble metal electrode is composed of a material such as, but not limited to, palladium (Pd) or platinum (Pt).
  • a method of operating a non-volatile memory device includes applying a positive bias to a memory element.
  • the memory element includes a first conductive electrode, a cationic-based conductive oxide layer disposed on the first conductive electrode, and a second electrode disposed on the cationic-based conductive oxide layer.
  • the method also includes changing the cationic-based conductive oxide layer from a more conductive state to a less conductive state by the applying.
  • the cationic-based conductive oxide layer includes lithium atoms and lithium vacancies, and changing the cationic-based conductive oxide layer from the more conductive state to the less conductive state includes migrating the lithium atoms from one of the electrodes toward the bulk of the cationic-based conductive oxide layer.
  • changing the cationic-based conductive oxide layer from the more conductive state to the less conductive state includes causing a change in composition of the cationic-based conductive oxide layer.
  • applying the positive bias includes applying a bias of less than absolute 1V.
  • a method of operating a non-volatile memory device includes applying a negative bias to a memory element.
  • the memory element includes a first conductive electrode, a cationic-based conductive oxide layer disposed on the first conductive electrode, and a second electrode disposed on the cationic-based conductive oxide layer.
  • the method also includes changing the cationic-based conductive oxide layer from a less conductive state to a more conductive state by the applying.
  • the cationic-based conductive oxide layer includes lithium atoms and lithium vacancies, and changing the cationic-based conductive oxide layer from the less conductive state to the more conductive state includes migrating the lithium atoms from the bulk of the cationic-based conductive oxide layer toward one of the electrodes.
  • changing the cationic-based conductive oxide layer from the less conductive state to the more conductive state includes causing a change in composition of the cationic-based conductive oxide layer.
  • applying the negative bias includes applying a bias of less than absolute 1V.

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KR1020157009641A KR101805032B1 (ko) 2012-11-27 2013-06-24 양이온 기반 도전성 산화물 요소를 갖는 저전압 내장 메모리
EP13857711.9A EP2926371B1 (en) 2012-11-27 2013-06-24 Low voltage embedded memory having cationic-based conductive oxide element
PCT/US2013/047418 WO2014084909A1 (en) 2012-11-27 2013-06-24 Low voltage embedded memory having cationic-based conductive oxide element
CN201380055748.5A CN104756246B (zh) 2012-11-27 2013-06-24 具有基于阳离子的导电氧化物元件的低电压嵌入式存储器
TW102139956A TWI552400B (zh) 2012-11-27 2013-11-04 具有陽離子爲基的導電氧化物元件之低電壓嵌入式記憶體
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EP2926371B1 (en) 2018-11-07
KR20150055054A (ko) 2015-05-20
TW201436319A (zh) 2014-09-16
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US20160056374A1 (en) 2016-02-25
KR101805032B1 (ko) 2018-01-10
CN104756246B (zh) 2018-12-18
US20140146592A1 (en) 2014-05-29
US9318701B2 (en) 2016-04-19
WO2014084909A1 (en) 2014-06-05

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