US8553115B2 - Photoelectric conversion apparatus and imaging system using the same - Google Patents

Photoelectric conversion apparatus and imaging system using the same Download PDF

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US8553115B2
US8553115B2 US12/957,537 US95753710A US8553115B2 US 8553115 B2 US8553115 B2 US 8553115B2 US 95753710 A US95753710 A US 95753710A US 8553115 B2 US8553115 B2 US 8553115B2
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photoelectric conversion
semiconductor region
conversion elements
conversion apparatus
semiconductor
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US20110134270A1 (en
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Yu Arishima
Takashi Matsuda
Toru Koizumi
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Canon Inc
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Canon Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/15—Charge-coupled device [CCD] image sensors
    • H10F39/158—Charge-coupled device [CCD] image sensors having arrangements for blooming suppression
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures

Definitions

  • the present application relates to a structure of isolation of a photoelectric conversion apparatus.
  • CCD type and CMOS type photoelectric conversion apparatuses are used for a lot of digital still cameras and digital camcorders.
  • pixels have been reduced.
  • measures against charge leakage (cross talk) into adjacent pixels that occurs according thereto are discussed.
  • Japanese Patent Application Laid-Open No. 2003-258232 discloses a configuration where a P type well region, which functions as a barrier for element isolation to prevent charge leakage (cross talk) between adjacent pixels, is formed in a deep region consistent with an N type well region of a photoelectric conversion element.
  • a transistor for reading charge from a photoelectric conversion element is provided around the photoelectric conversion element.
  • the widths of semiconductor regions functioning as element isolation regions for separating the photoelectric conversion elements from each other vary.
  • the inventors of the present invention have found that there is a case where amounts of leakage of charge from P type well regions, which can be element isolation of the photoelectric conversion elements described in Japanese Patent Application Laid-Open No. 2003-258232, may vary according to the widths of the element isolation regions in such situations. If amounts of leakage of signal charge into the adjacent photoelectric conversion elements vary, the image quality is degraded and correction of the image signal becomes difficult.
  • a photoelectric conversion apparatus comprises: a plurality of photoelectric conversion elements including a first photoelectric conversion element, a second photoelectric conversion element adjacent to the first photoelectric conversion element, and a third photoelectric conversion element adjacent to the first photoelectric conversion element; and a plurality of transistors each for transferring a signal charge generated in each of the plurality of photoelectric conversion elements, wherein the plurality of photoelectric conversion elements and the plurality of transistors are arranged in a semiconductor substrate, and wherein a first semiconductor region of a first width having a first conductivity type so as to contain the signal charge as a minority carrier is arranged between the first and second photoelectric conversion elements, a second semiconductor region of a second width smaller than the first width having the first conductivity type is arranged between the first and third photoelectric conversion elements, and a third semiconductor region of a third width and having the first conductivity type is arranged under the first and second semiconductor regions.
  • FIGS. 1A and 1B are schematic sectional views of a photoelectric conversion apparatus illustrating a first embodiment.
  • FIG. 2A is a circuit diagram and a planar layout diagram of the photoelectric conversion apparatus illustrating the first embodiment.
  • FIG. 2B is a planar layout diagram of the photoelectric conversion apparatus illustrating the first embodiment.
  • FIG. 2C is a planar layout diagram of the photoelectric conversion apparatus illustrating the first embodiment.
  • FIGS. 3A and 3B are schematic sectional views of a photoelectric conversion apparatus for comparison for illustrating the first embodiment.
  • FIGS. 4A and 4B are schematic sectional views of a photoelectric conversion apparatus illustrating a second embodiment.
  • FIGS. 5A and 5B are schematic sectional views of the photoelectric conversion apparatus illustrating the second embodiment.
  • FIGS. 6A and 6B are schematic sectional views of a photoelectric conversion apparatus illustrating a third embodiment.
  • FIGS. 7A , 7 B and 7 C are schematic sectional views of a photoelectric conversion apparatus illustrating a fourth embodiment.
  • FIG. 8 is a block diagram illustrating an imaging system.
  • a photoelectric conversion apparatus of the present invention includes a first semiconductor region that can be potential barriers against signal charge arranged in a element isolation region between first and second photoelectric conversion elements.
  • the photoelectric conversion apparatus also includes a second semiconductor region that can be potential barriers against signal charge arranged in an element isolation region between the first and a third photoelectric conversion element.
  • the second semiconductor region has the same depth as the depth of the first semiconductor region and a width narrower than a width of the first semiconductor region.
  • the photoelectric conversion apparatus includes a third semiconductor region that can be potential barriers against signal charge under the first and second semiconductor regions.
  • FIG. 2A illustrates an example of a pixel circuit to which the present invention can be applied.
  • FIGS. 2B and 2C illustrate planar layouts of the pixel circuit.
  • FIG. 2A illustrates a pixel cell including two photoelectric conversion elements. In the photoelectric conversion apparatus, such pixel cells are arranged in one-dimensionally or two-dimensionally and configure an imaging region. If a configuration where the pixel employs one photoelectric conversion element is employed, the pixel cell illustrated in FIG. 2A includes two pixels.
  • the photoelectric conversion apparatus includes photodiodes as photoelectric conversion elements 100 , transfer MOS transistors 101 , a reset MOS transistor 102 and an amplification MOS transistor 103 .
  • a node 104 is at the intersection of the transfer MOS transistor, the reset MOS transistor and the gate electrode of the amplification MOS transistor.
  • the photoelectric conversion apparatus includes a selection MOS transistor 105 and an output line 106 .
  • This embodiment includes two photoelectric conversion elements 100 a and 100 e and two transfer MOS transistors 101 a and 101 e .
  • the transfer MOS transistor 101 a transfers charge generated in the photoelectric conversion element 100 a to the node 104 .
  • the transfer MOS transistor 101 e transfers charge generated in the photoelectric conversion element 100 e to the node 104 .
  • the amplification MOS transistor 103 outputs an output according to the potential of the node 104 to the output line 106 via the selection MOS transistor 105 .
  • the amplification MOS transistor 103 is a part of a source follower circuit, and the gate electrode thereof is connected to the node 104 .
  • the reset MOS transistor 102 resets the node 104 of the gate electrode of the amplification MOS transistor 103 to a predetermined potential (reset potential).
  • the transfer MOS transistor 101 a is supplied with a transfer control signal TX 1 .
  • the transfer MOS transistor 101 e is supplied with a transfer control signal TX 2 .
  • the reset MOS transistor is supplied with a reset control signal RES.
  • the selection MOS transistor 105 is supplied with selection control signal SEL. Each control signal control readout of the signal charge.
  • the two photoelectric conversion elements share one amplification MOS transistor 103 , one reset MOS transistor 102 and one selection MOS transistor 105 .
  • the photoelectric conversion apparatus includes photodiodes as photoelectric conversion elements 200 , the gate electrodes 201 of the transfer MOS transistors and the gate electrodes 202 of the reset MOS transistors.
  • the photoelectric conversion apparatus further includes the gate electrodes 203 of the amplification MOS transistors, floating diffusion regions 204 , and the gate electrode 205 of the selection MOS transistor.
  • the floating diffusion region 204 configures the node 104 .
  • the photoelectric conversion apparatus includes the source region 206 of the amplification MOS transistor and the drain region 207 of the amplification MOS transistor.
  • the source region 208 of the selection MOS transistor is connected to the output line 106 .
  • the photoelectric conversion element 200 a and the photoelectric conversion element 200 e share the amplification MOS transistor 206 , the selection MOS transistor and the reset MOS transistor 202 .
  • a semiconductor region 209 is for supplying power voltage to the semiconductor region or/and the semiconductor substrate, and also referred to as well contact on occasions.
  • An element isolation region 210 separates the elements from each other.
  • An element isolation structure including insulators, such as LOCOS and STI, and a semiconductor region functioning as potential barriers against the signal charge are arranged in the element isolation region 210 .
  • the plurality of photoelectric conversion elements 200 in FIG. 2B is denoted by 200 a - 200 g .
  • the gate electrode 201 a of the transfer MOS transistor corresponds to the photoelectric conversion element 200 a .
  • the floating diffusion region 204 a is also arranged.
  • the gate electrode 201 b of the transfer MOS transistor corresponds to the photoelectric conversion element 200 b .
  • the floating diffusion region 204 b is also arranged.
  • the other photoelectric conversion elements 200 c - 200 g will be described as with the elements 200 a and 200 b.
  • FIG. 2C is a simplified planar layout for illustrating the configuration of FIG. 2B .
  • first element isolation regions 220 are arranged between the photoelectric conversion element 200 a and the photoelectric conversion elements 200 d and 200 e .
  • the second element isolation regions 221 are arranged between the photoelectric conversion element 200 a and the photoelectric conversion elements 200 b and 200 c .
  • the first element isolation region 220 has a first width W 1
  • the second element isolation region 221 has a second width W 2 , where W 1 >W 2 .
  • the first width W 1 is a width at a line segment connecting the center of mass of the photoelectric conversion element 200 a and the center of mass of the photoelectric conversion element 200 d or 200 e .
  • the second width W 2 is a width at a line segment connecting the center of mass of the photoelectric conversion element 200 a and the center of mass of the photoelectric conversion element 200 b or 200 c .
  • the first element isolation regions 220 and the second element isolation regions 221 are arranged in grid-like fashion surrounding the photoelectric conversion elements.
  • the first element isolation regions 220 and the second element isolation regions 221 illustrated in FIG. 2C are arranged in FIG. 2B .
  • a floating diffusion region 204 is also arranged in an activation region including the photoelectric conversion element 200 defined by the element isolation regions.
  • the photoelectric conversion elements are two-dimensionally arranged in the photoelectric conversion apparatus of the first embodiment.
  • the photoelectric conversion apparatus is not limited to the circuit as illustrated in FIG. 2A . Instead, a configuration where further plural photoelectric conversion elements share the amplification MOS transistor or a configuration without the selection MOS transistor may be employed. Moreover, a case where the pixel cell includes only one photoelectric conversion element may be adopted.
  • the planar layout as illustrated in FIG. 2B is not necessarily employed. Embodiments of the present invention will hereinafter be described using the drawings.
  • FIG. 1A is a schematic sectional view taken along line AB of FIG. 2B .
  • FIG. 1B is a schematic sectional view taken along line CD of FIG. 2B .
  • configurational elements corresponding to the elements of FIG. 2B are assigned with identical symbols, description of which is omitted.
  • the photoelectric conversion elements, or the pixels are arranged in a matrix form along a first direction Y and a second direction X.
  • the second direction X and the first direction Y are orthogonal to each other.
  • a semiconductor region 216 and a base substrate 218 are illustrated in FIGS. 1A and 1B .
  • a configuration including the semiconductor region 216 and the base substrate 218 is referred to as a semiconductor substrate 219 .
  • the semiconductor region 216 is formed in or on the base substrate 218 . More specifically, the semiconductor region 216 is formed, for example, by ion implantation into the base substrate 218 or by providing an epitaxial layer on the base substrate 218 .
  • the semiconductor region 216 is a P type (first conductive type) semiconductor region.
  • the base substrate 218 is of an N type (second conductive type).
  • the conductive types of the semiconductor region 216 and the base substrate 218 may be of the N type or the P type.
  • the main surface 217 of the semiconductor substrate 219 is also illustrated.
  • the main surface 217 is a plane including the light receiving surface of the photoelectric conversion element.
  • the photoelectric conversion element 200 includes a P type semiconductor region 211 that can also function as a surface protective layer, and an N type semiconductor region 212 that can also function as a charge accumulator.
  • the floating diffusion region 204 is made of an N type semiconductor region.
  • a P type semiconductor region 211 a and an N type semiconductor region 212 a correspond to the photoelectric conversion element 200 a .
  • a P type semiconductor region 211 b and an N type semiconductor region 212 b correspond to the photoelectric conversion element 200 b .
  • other photoelectric conversion elements 200 c - 200 e are configured.
  • the photoelectric conversion element 200 a is a first photoelectric conversion element.
  • the photoelectric conversion elements 200 d and 200 e are second photoelectric conversion elements.
  • the photoelectric conversion elements 200 b and 200 c are third photoelectric conversion elements.
  • the photoelectric conversion elements 200 f and 200 g are fourth photoelectric conversion elements.
  • a gate insulation film is omitted.
  • an element isolation structure (herein, LOCOS) 215 is arranged on the main surface of the semiconductor substrate of the first element isolation region 220 and the second element isolation region 221 .
  • P type first semiconductor region 113 and second semiconductor region 114 are arranged under the element isolation structure 215 .
  • the first and second semiconductor regions 113 and 114 have impurity concentrations higher than a concentration of a P type semiconductor region 216 and can be potential barriers against the signal charge.
  • the semiconductor region that can be potential barriers against the signal charge is, for example, a semiconductor region of a conductive type where the signal charge becomes minority carriers.
  • the first semiconductor region 113 has the same width as the width W 1 of the first element isolation region 220 ; the second semiconductor region 114 has the same width as the width W 2 of the second element isolation region 221 .
  • the widths are not limited thereto.
  • the first semiconductor region 113 and the second semiconductor region 114 extend from a lower part of the element isolation structure 215 to a first depth D 1 equal with respect to each other.
  • the first semiconductor region 113 and the second semiconductor region 114 have the same impurity concentration as each other.
  • the floating diffusion regions corresponding to the first photoelectric conversion element 200 a are arranged between the first photoelectric conversion element 200 a and the third photoelectric conversion elements 200 b and 200 c .
  • the floating diffusion region is arranged between the first photoelectric conversion element 200 a and the second semiconductor region 144 .
  • Other devices such as transistors ( 208 and 209 ) may be arranged on the first and second semiconductor regions.
  • the first semiconductor region 113 and the second semiconductor region 114 surround each photoelectric conversion element in grid-like fashion.
  • respective third semiconductor regions 115 are arranged under the first semiconductor region 113 and the second semiconductor region 114 .
  • the third semiconductor regions 115 have a third width W 3 , and arranged from the bottoms of the first and second semiconductor regions to a second depth D 2 . Since such third semiconductor region 115 is provided, it can be suppressed that charge generated in a depth of the semiconductor substrate 119 of the photoelectric conversion element 200 a unevenly leaks between the photoelectric conversion elements adjacent to each other.
  • the first to third semiconductor regions 113 to 115 are formed according to a method described below.
  • the element isolation structure 215 is formed in the first and second element isolation region of the semiconductor substrate.
  • a first mask such as a photoresist having openings with widths W 1 and W 2 is provided in a region where the first and second semiconductor regions 113 and 114 are to be formed, on the semiconductor substrate 219 .
  • Impurity ions for forming the P type semiconductor region using the first mask are implanted into the semiconductor substrate 219 by a first dosage at the first energy. This ion implantation forms the first semiconductor region 113 and the second semiconductor region 114 .
  • a second mask such as a photoresist having an opening with width W 3 is provided in a region where the third semiconductor region 115 is to be formed, on the semiconductor substrate 219 .
  • Impurity ions for forming the P type semiconductor region using the second mask is implanted into the semiconductor substrate 219 by a second dosage at a second energy.
  • This ion implantation forms the third semiconductor region 115 .
  • the first dosage and the second dosage are equal to each other.
  • the first energy is smaller than the second energy.
  • the first and second semiconductor regions 113 and 114 may separately be formed. The order may arbitrarily be selected.
  • the third semiconductor region 115 may be formed before the first and second semiconductor regions.
  • FIGS. 3A and 3B are schematic sectional views of a photoelectric conversion apparatus corresponding to FIGS. 1A and 1B .
  • configurational elements corresponding to the elements of FIGS. 1A , 1 B, 2 A and 2 B are assigned with identical symbols, description of which is omitted.
  • widths of element isolation regions arranged between the photoelectric conversion elements vary in some cases.
  • semiconductor regions ( 313 and 314 ) that can be potential barriers against signal charge are formed on the entire surface of the photoelectric conversion apparatus at the same time.
  • the depth (D 3 ) and the impurity concentration of semiconductor regions ( 313 and 314 ) that can be potential barriers against the signal charge become equal to each other.
  • the widths (W 1 and W 2 ) are different from each other. In such a configuration, as shown in FIGS. 3A and 3B , in a case that signal charges are generated at a depth of the semiconductor substrate 219 in the photoelectric conversion element 200 a , amounts of signal charge leakage (cross talk) vary with respect to adjacent photoelectric conversion elements 200 b , 200 c , 200 d and 200 e .
  • the element isolation structure 215 is provided in the element isolation region.
  • a configuration where only the P type first and second semiconductor regions 113 and 114 are provided may be employed.
  • a boundary of the semiconductor region is a point where the impurity concentration becomes the impurity concentration of the P type semiconductor region 216 in the impurity concentration profile. If the semiconductor region 216 is of the N type, the boundary is the point where the net concentration becomes zero in the impurity concentration profile.
  • the width of the semiconductor region or the region is a length of the semiconductor region or the region projected on the main surface 217 of the semiconductor substrate.
  • the width is the length on the line segment connecting the centers of mass of the photoelectric conversion elements on the main surface 217 in a case where the elements are projected on the main surface 217 of the semiconductor substrate.
  • the depth of the semiconductor region is the length of the semiconductor region from the main surface 217 of the semiconductor substrate into the semiconductor substrate.
  • FIGS. 4A and 4B are schematic sectional views of a photoelectric conversion apparatus corresponding to FIGS. 1A and 1B . Configurational elements having similar functions are assigned with identical symbols, description of which is omitted.
  • the configurations of the first to third semiconductor regions are different from the configurations of the first embodiment.
  • the first semiconductor region 413 is arranged to a depth D 4 , and includes two semiconductor regions.
  • the second semiconductor region 414 is arranged to the depth D 4 , and includes two semiconductor regions.
  • Third semiconductor regions 415 are arranged from the bottoms of the first and second semiconductor regions to a depth D 5 , and includes two semiconductor regions. That is, in this embodiment, the semiconductor regions that can function as potential barriers against the signal charge include a plurality of semiconductor regions.
  • the depth D 4 is the same as the depth of the lower surface of the N type semiconductor region 212 of the photoelectric conversion element.
  • Such a configuration allows charge generated at a depth of the semiconductor substrate deeper than the semiconductor region 212 of the photoelectric conversion element to be separated by the third semiconductor region 415 with width W 4 in both FIGS. 4A and 4B . If third semiconductor region 415 is provided at a part shallower than the bottom of the N type semiconductor region 212 , it is difficult to sufficiently separate the adjacent photoelectric conversion elements.
  • the regions 415 can be arranged at a position equal to or deeper than the position of the lower surface of the N type semiconductor region 212 , whose upper portion functions as a charge accumulator of the photoelectric conversion element.
  • a configuration where the first semiconductor region 413 and the second semiconductor region 414 include another semiconductor region in the depth direction of the semiconductor substrate and a configuration where the upper surface of the third semiconductor region 415 is disposed deeper than depth D 4 may be employed.
  • the width of the first semiconductor region 413 is W 1 .
  • the width of the second semiconductor region 414 is W 2 .
  • the width of the third semiconductor region 415 is W 4 .
  • FIGS. 5A and 5B illustrate a modification of this embodiment.
  • FIGS. 5A and 5B are a schematic sectional view of the photoelectric conversion apparatus corresponding to FIGS. 4A and 4B . Configurational elements having similar functions are assigned with identical symbols, description of which is omitted.
  • the configuration of FIGS. 5A and 5B different from the configuration of FIGS. 4A and 4B is the width W 5 of the third semiconductor region 515 .
  • the widths of the first to third semiconductor regions have the relationship W 1 >W 2 >W 4 .
  • the relationship is W 1 >W 5 >W 2 .
  • FIGS. 5A and 5B the relationship is W 1 >W 5 >W 2 .
  • a semiconductor region that functions as potential barriers having the same width against charge generated at a depth of the semiconductor substrate is provided. Accordingly, leakage between the adjacent photoelectric conversion elements can be suppressed.
  • the relationship between the widths of the first and second semiconductor regions and the width of the third semiconductor region may arbitrarily be set.
  • FIGS. 6A and 6B are schematic sectional views of a photoelectric conversion apparatus corresponding to FIGS. 1A and 1B . Configurational elements having similar functions are assigned with identical symbols, description of which is omitted.
  • This embodiment is different from the first embodiment in the structures of the first to third semiconductor regions.
  • the second semiconductor region 614 has the width W 2 and arranged to a depth D 7 .
  • the first semiconductor region 613 has the width W 1 and arranged to a depth D 6 .
  • third semiconductor region having the width W 2 and arranged to a depth D 7 is only arranged under the first semiconductor region 613 .
  • the second semiconductor region 614 integrally includes third semiconductor region 615 .
  • Such a configuration can also suppress that charge generated in a depth of the semiconductor substrate 119 of the photoelectric conversion element 200 a unevenly leaks between the adjacent photoelectric conversion elements.
  • the configuration where the second semiconductor region 614 integrally includes the third semiconductor region 615 has been described.
  • a configuration may be employed where the width of the third semiconductor region 615 equals to W 1 , the first semiconductor region 613 integrally includes the third semiconductor region 615 , and the third semiconductor region is arranged under the second semiconductor region 614 .
  • FIGS. 7A to 7C are schematic sectional views of a photoelectric conversion apparatus corresponding to FIGS. 1A and 1B , respectively.
  • FIG. 7C is a schematic sectional view of the photoelectric conversion apparatus corresponding to the view taken along line EF in FIG. 2B .
  • configurational elements having functions similar to the elements of FIGS. 1A and 1B are assigned with identical symbols, description of which is omitted.
  • the photoelectric conversion apparatus of this embodiment has color filters.
  • the color filters of this embodiment are of a Bayer color array.
  • a color filter of red (R) is arranged above the first photoelectric conversion element 200 a .
  • Color filters of green (G) are arranged above the second photoelectric conversion elements 200 d and 200 e and the third photoelectric conversion elements 200 b and 200 c .
  • Color filters of blue (B) are arranged above the forth photoelectric conversion elements 200 f and 200 g .
  • These elements are hereinafter denoted by 200 a (R), 200 b (G) and 200 f (B).
  • light incident on the photoelectric conversion element 200 a (R) has a long wavelength.
  • the light reaches a depth of the semiconductor substrate, and generates charge at the depth of the semiconductor substrate.
  • Light incident on the photoelectric conversion elements 200 b (G) and 200 f (B) has wavelengths shorter than the wavelength of the light incident on the photoelectric conversion element 200 a (R), and generates charge at a shallow part of the semiconductor substrate. Therefore, in this embodiment, the semiconductor regions at a depth of the substrate that are arranged adjacent to the photoelectric conversion element 200 a (R) are made to be equal in width. This configuration reduces variation of charge leaking into the photoelectric conversion elements.
  • second element isolation region 221 is provided with a P type semiconductor region 714 that has the width W 2 and is arranged to a depth D 8 , and a P type semiconductor region 715 that has the width W 3 and is arranged from the bottom of the semiconductor region 714 to a depth D 9 .
  • the first element isolation region 220 is provided with a P type semiconductor region 713 that has the width W 1 and is arranged to the depth D 8 , and the P type semiconductor region 715 that has the width W 3 and is arranged from the bottom of the semiconductor region 713 to a depth D 9 .
  • the first element isolation region 220 is provided with a P type semiconductor region 716 that has the width W 1 and is arranged to the depth D 9 .
  • the P type semiconductor regions 716 that have the same width W 3 and the same depth are arranged at least in the first element isolation region 220 and the second element isolation region 221 adjacent to the photoelectric conversion element 200 a (R).
  • Such a configuration can also uniformize amounts of signal charge leaking into the adjacent photoelectric conversion elements.
  • a following configuration may be employed in the first element isolation region 220 that is not adjacent to the photoelectric conversion element 200 a (R) in FIG. 7C of this embodiment.
  • the first semiconductor region 713 with the width W 1 is arranged, and a P type semiconductor region with a width smaller than W 1 may be arranged thereunder.
  • the first semiconductor region 713 with the width W 1 is arranged, and the P type semiconductor region is not necessarily arranged thereunder.
  • the P type semiconductor region with the width W 3 can be arranged as with the other embodiments.
  • the width W 3 may be larger than the width W 2 or W 1 .
  • the P type semiconductor region that can function as potential barriers against the signal charge may include a plurality of semiconductor regions.
  • the configuration employing the color filters of the Bayer color array has been described.
  • the color filters are not limited to the Bayer color array.
  • Color filters of complementary colors may be employed. At least the widths at a depth of the substrate of the semiconductor regions arranged adjacent to the photoelectric conversion element on which a color filter corresponding to light with the longest wavelength is arranged may be made to be equal.
  • the imaging system is a digital still camera, a digital video camera or a digital camera for a mobile phone.
  • FIG. 8 is a diagram illustrating a configuration of a digital still camera.
  • An optical image of a subject is formed on an imaging surface of a photoelectric conversion apparatus 804 by an optical system including a lens 802 .
  • a barrier 801 that has a protecting function and also serves as a main switch can be arranged around the outside of the lens 802 .
  • a diaphragm 803 for adjusting an amount of light emitted therefrom can be arranged at the lens 802 .
  • Imaged signals output from the photoelectric conversion apparatus 804 in a plurality of channels are subjected to processing, such as various types of correction and clump by an imaging signal processing circuit 805 .
  • the imaged signals output in the plurality of channels from the imaging signal processing circuit 805 are subjected to analog to digital conversion in an A/D converter 806 .
  • the image data output from the A/D converter 806 is subjected to various types of correction and data compression by a signal processing unit (image processor) 807 .
  • the photoelectric conversion apparatus 804 , the imaging signal processing circuit 805 , the A/D converter 806 and the signal processing unit 807 operate according to a timing signal generated by a timing generator 808 .
  • Each block is controlled by a whole controlling and arithmetic operation unit 809 .
  • the camera further includes a memory unit 810 for temporarily storing the image data and a recording medium control interface 811 for recording and reading the image on or from a recording medium.
  • the recording medium 812 includes a semiconductor memory and is detachable. Further, the recording medium 812 may include an external interface (I/F) unit 813 for communicating with an external computer.
  • I/F external interface
  • the blocks 805 to 808 may be formed on the same chip as the chip of the photoelectric conversion apparatus 804 .
  • the photoelectric conversion apparatus of the present invention is applied to the imaging system.
  • the photoelectric conversion apparatus of the present invention is used and thereby the amount of signal charge leakage between the pixels (cross talk) is uniformized. Accordingly, the image processing in the signal processing circuit becomes easy in comparison with the case with unevenness. Therefore, the configuration of the signal processing unit of the imaging system can be simplified.
  • the present invention is not limited to each embodiment, but may appropriately be modified.
  • the arrangement of the semiconductor region is not limited to the manner having been described. Instead, the semiconductor region may be separated into a plurality of regions or integrally formed in one region. The polarity of charge, the polarity of the semiconductor region and the polarity of the transistor may appropriately be modified.
  • the pixel arrangement is not limited to the matrix form. Further, the configuration of each embodiment can appropriately be combined.

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