US8274827B2 - Memory device and operating method thereof - Google Patents

Memory device and operating method thereof Download PDF

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Publication number
US8274827B2
US8274827B2 US12/780,938 US78093810A US8274827B2 US 8274827 B2 US8274827 B2 US 8274827B2 US 78093810 A US78093810 A US 78093810A US 8274827 B2 US8274827 B2 US 8274827B2
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common
semiconductor layers
memory device
nand strings
memory cells
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US20110280075A1 (en
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Riichiro Shirota
Te-Chang TSENG
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ROBUSTFLASH Tech Ltd
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ROBUSTFLASH Tech Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • each of the memory cells is composed of an active area extending along a first direction, a first gate line extending along a second direction perpendicular to the first direction, a second gate line extending along third direction parallel to the second direction and a charge trapping structure, and the first gate line and the second gate line are configured at two opposite sides of the active area and the charge trapping structure is configured between the active area and the first gate line and between the active area and the second gate line.
  • FIG. 3 is a schematic top view of the memory device shown in FIG. 2A .
  • FIG. 10A is a cross-sectional view showing a memory device according to one embodiment of the present invention.
  • each of the NAND strings includes a plurality of memory cells. More clearly, the NAND string S 1 comprises the memory cells MR 11 through MR 1 n , and the NAND string S 2 comprises the memory cells MR 21 through MR 2 n .
  • each of the NAND strings includes at least one string selection transistor and at least one source side selection transistor. Specifically, the NAND string S 1 comprises the string selection transistors TSGD 11 and TSGD 12 , and the NAND string S 2 comprises the string selection transistors TSGD 21 and TSGD 22 . Also, the NAND string S 1 comprises the source side selection transistor TSGS 1 , and the NAND string S 2 comprises the source side selection transistors TSGS 2 .
  • each of the active layers 402 a and 402 b there is at least one heavily doped region (such as the heavily doped regions 454 a and 454 b ) configured around one region 456 , which is used to form the string selection transistors of the NAND strings in later manufacturing process. Further, the at least one heavily doped region in each of the active layers 402 a and 402 b is used to form the depletion-mode string selection transistor. Noticeably, when the active layers 402 a and 402 b are made of lightly doped polysilicon, the conductive type of the active layers 402 a and 402 b is as same as the conductive type of the heavily doped regions 454 a and 454 b . In other words, the conductive type throughout each of the active layers 402 a and 402 b is single.
  • the gate line portion 464 b comprises a plurality of gate lines (such as the gate lines 468 a , 468 b , 468 c and 468 d shown in FIG. 7B ). Each of the gate line extends form the top layer of the active layers to the bottom layer of the active layers.
  • the gate lines 468 a , 468 b , 468 c and 468 d are used as gates of the memory cells of the NAND strings S 1 and S 2 of the active layers 402 a ′ and 402 b ′.
  • FIG. 10B is a cross-sectional view showing a memory device according to another embodiment of the present invention.
  • the structures of the memory devices in the memory regions and the transistors in the periphery regions respectively shown in FIG. 10A and FIG. 10B are similar to each other, and the difference between thereto is that, as shown in FIG. 10B , the transistors of the present embodiment are formed on the top layer of the active layers of the NAND strings in the periphery region 1100 b . That is, the transistors 1104 a ′ and 1104 b ′ shown in FIG. 10B are formed on the top layer of the active layers of NAND strings S 1 and S 2 in the periphery region 1102 b .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
US12/780,938 2010-05-17 2010-05-17 Memory device and operating method thereof Active 2031-04-27 US8274827B2 (en)

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US12/780,938 US8274827B2 (en) 2010-05-17 2010-05-17 Memory device and operating method thereof
TW099121675A TW201142842A (en) 2010-05-17 2010-07-01 Memory device and operating method thereof

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US12/780,938 US8274827B2 (en) 2010-05-17 2010-05-17 Memory device and operating method thereof

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US8274827B2 true US8274827B2 (en) 2012-09-25

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130033939A1 (en) * 2011-08-03 2013-02-07 Micron Technology, Inc. Functional data programming and reading in a memory
US20130194869A1 (en) * 2012-01-31 2013-08-01 Eun Seok Choi Three-dimensional non-volatile memory device
US20150092494A1 (en) * 2013-10-02 2015-04-02 Mosaid Technologies Incorporated Vertical Gate Stacked NAND and Row Decoder for Erase Operation
US9853049B2 (en) 2016-04-21 2017-12-26 Samsung Electronics Co., Ltd. Memory devices having common source lines including layers of different materials

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI427636B (zh) * 2009-11-27 2014-02-21 Macronix Int Co Ltd 於一記憶積體電路上進行抹除操作之方法與裝置
KR101370509B1 (ko) * 2012-02-24 2014-03-06 서울대학교산학협력단 Ｌｓｍ이 가능한 3차원 적층형 낸드 플래시 메모리 어레이 및 그 동작방법
US9384839B2 (en) * 2013-03-07 2016-07-05 Sandisk Technologies Llc Write sequence providing write abort protection
US9484530B2 (en) * 2014-11-11 2016-11-01 Globalfoundries Singapore Pte. Ltd. Integrated circuit structures with spin torque transfer magnetic random access memory having increased memory cell density and methods for fabricating the same
KR20160062498A (ko) * 2014-11-25 2016-06-02 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법
US10403637B2 (en) * 2017-01-20 2019-09-03 Macronix International Co., Ltd. Discrete charge trapping elements for 3D NAND architecture
US20240032278A1 (en) * 2022-07-22 2024-01-25 Nanya Technology Corporation Memory structure

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US20090122613A1 (en) 2007-11-12 2009-05-14 Samsung Electronics Co., Ltd. Non-volatile memory device and method of operating the same
US7615447B2 (en) * 2007-12-19 2009-11-10 Sandisk Corporation Composite charge storage structure formation in non-volatile memory using etch stop technologies
US20100109627A1 (en) * 2008-10-31 2010-05-06 Akira Umezawa Power circuit including step-up circuit and stabilizing method thereof
US20100117141A1 (en) * 2008-11-13 2010-05-13 Samsung Electronics Co., Ltd. Memory cell transistors having limited charge spreading, non-volatile memory devices including such transistors, and methods of formation thereof
US20100172182A1 (en) * 2009-01-06 2010-07-08 Samsung Electronics Co., Ltd. Nonvolatile memory device and method for operating the same
US7812390B2 (en) * 2006-07-25 2010-10-12 Samsung Electronics Co., Ltd. Semiconductor memory device with memory cells on multiple layers
US20110018051A1 (en) * 2009-07-23 2011-01-27 Ji-Young Kim Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same

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US7615447B2 (en) * 2007-12-19 2009-11-10 Sandisk Corporation Composite charge storage structure formation in non-volatile memory using etch stop technologies
US20100109627A1 (en) * 2008-10-31 2010-05-06 Akira Umezawa Power circuit including step-up circuit and stabilizing method thereof
US20100117141A1 (en) * 2008-11-13 2010-05-13 Samsung Electronics Co., Ltd. Memory cell transistors having limited charge spreading, non-volatile memory devices including such transistors, and methods of formation thereof
US20100172182A1 (en) * 2009-01-06 2010-07-08 Samsung Electronics Co., Ltd. Nonvolatile memory device and method for operating the same
US20110018051A1 (en) * 2009-07-23 2011-01-27 Ji-Young Kim Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130033939A1 (en) * 2011-08-03 2013-02-07 Micron Technology, Inc. Functional data programming and reading in a memory
US9449692B2 (en) * 2011-08-03 2016-09-20 Micron Technology, Inc. Functional data programming and reading in a memory
US9620234B2 (en) 2011-08-03 2017-04-11 Micron Technology, Inc. Functional data reading in a non-volatile memory
US10115465B2 (en) 2011-08-03 2018-10-30 Micron Technology, Inc. Functional data programming in a non-volatile memory
US20130194869A1 (en) * 2012-01-31 2013-08-01 Eun Seok Choi Three-dimensional non-volatile memory device
US8743612B2 (en) * 2012-01-31 2014-06-03 SK Hynix Inc. Three-dimensional non-volatile memory device
US20150092494A1 (en) * 2013-10-02 2015-04-02 Mosaid Technologies Incorporated Vertical Gate Stacked NAND and Row Decoder for Erase Operation
US9202578B2 (en) * 2013-10-02 2015-12-01 Conversant Intellectual Property Management Inc. Vertical gate stacked NAND and row decoder for erase operation
US9853049B2 (en) 2016-04-21 2017-12-26 Samsung Electronics Co., Ltd. Memory devices having common source lines including layers of different materials

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US20110280075A1 (en) 2011-11-17

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