US20070010055A1 - Non-volatile memory and fabricating method thereof - Google Patents
Non-volatile memory and fabricating method thereof Download PDFInfo
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- US20070010055A1 US20070010055A1 US11/180,117 US18011705A US2007010055A1 US 20070010055 A1 US20070010055 A1 US 20070010055A1 US 18011705 A US18011705 A US 18011705A US 2007010055 A1 US2007010055 A1 US 2007010055A1
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- 238000000034 method Methods 0.000 title claims description 33
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 125000006850 spacer group Chemical group 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 239000003989 dielectric material Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- Non-volatile memory is a type of memory that allows writing, reading and erasing data for multiple times, and the stored data will be retained even after power supplied to the device is off. Furthermore, non-volatile memory also has the advantages of small size, fast access speed and low power consumption. In addition, data can be erased in a block-by-block fashion so that the operating speed is further enhanced. With these advantages, non-volatile memory has become one of the most widely adopted memory devices for personal computers and electronic equipments.
- a typical non-volatile memory comprises an array of memory cells.
- the horizontally laid memory cells are serially connected through a word line and the vertically laid memory cells are serially connected through a bit line.
- the control gate of the memory cell serves as the word line, while the source region or drain region of the memory is electrically connected with bit line through the source contact or the drain contact.
- misalignment between the contacts and the source regions or the drain regions occurs easily, which would reduce device reliability.
- the misalignment can be corrected through an increased width of the source regions or the drain regions, the size of each device would be enlarged as well.
- a better solution is desired.
- At least one objective of the present invention is to provide a method of fabricating a non-volatile memory capable of resolving the misalignment problem in the conventional contact fabricating process.
- At least a second objective of the present invention is to provide a non-volatile memory having a smaller device dimension so that overall level of integration of the memory can be increased.
- the invention provides a method of fabricating a non-volatile memory.
- a substrate is provided.
- a plurality of columns of isolation structures are formed on the substrate.
- a plurality of rows of stacked gate structures are formed on the substrate.
- the stacked gate structures cross over the isolation structures, and each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate.
- a plurality of doping regions are formed in the substrate, between two neighboring stacked gate structures.
- a plurality of stripes of spacers are formed on the sidewalls of stacked gate structures.
- the present invention also provides a non-volatile memory.
- the non-volatile memory comprises a substrate, a plurality of columns of isolation structures, a plurality of rows of stacked gate structures, a plurality of stripes of spacers, a plurality of first dielectric layers, a plurality of first conductive layers and a plurality of doping regions.
- the isolation structures are located on the substrate.
- the stacked gate structures are located on the substrate, and cross over the isolation structures.
- each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate.
- the spacers are located on the sidewalls of the stacked gate structures.
- contacts are formed in the first dielectric layers on the isolation structures, misalignment between contacts and the source region or the drain region is minimized in the process of forming contacts, and the process window can be increased.
- FIGS. 1A through 1C are top views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention.
- FIGS. 2A through 2D are schematic cross-sectional views along line I-I′ of FIG. 1A showing the steps for fabricating a non-volatile memory.
- FIGS. 3A through 3D are schematic cross-sectional views along line II-II′ of FIG. 1A showing the steps for fabricating a non-volatile memory.
- FIGS. 4A through 4D are schematic cross-sectional views along line III-III′ of FIG. 1A showing the steps for fabricating a non-volatile memory.
- FIGS. 1A through 1C are top views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention
- FIGS. 2A through 2D are schematic cross-sectional views along line I-I′ of FIG. 1A
- FIGS. 3A through 3D are schematic cross-sectional views along line II-II′ of FIG. 1A
- FIGS. 4A through 4D are schematic cross-sectional views along line III-III′ of FIG. 1A .
- a substrate 100 is provided.
- the substrate 100 can be a silicon substrate.
- a plurality of columns of isolation structures 102 are formed on the substrate 100 .
- isolation structures 102 are shallow trench isolation structures, for example, which can be formed by performing a conventional shallow trench isolation structure fabricating process.
- each stacked gate structure 104 cross over the isolation structures 102 , and each stacked gate structure 104 comprises a bottom dielectric layer 106 , a charge storage layer 108 , a top dielectric layer 110 and a control gate layer 112 sequentially disposed over the substrate 100 .
- the stacked gate structures 104 are defined by a mask layer 114 , while the control gate layer 112 can serve as a bit line.
- the bottom dielectric layer 106 is a tunneling layer fabricated using silicon oxide material, for example.
- the charge storage layer 108 is a charge-trapping layer fabricated using silicon nitride material, for example.
- the top dielectric layer 110 is a charge barrier layer fabricated using silicon oxide material, for example.
- the control gate layer is a doped polysilicon layer, for example.
- a plurality of doping regions 116 are formed in the substrate 100 between two neighboring stacked gate structures 104 .
- the doping regions 116 can serve as source regions and drain regions, which can be formed by performing an ion implantation process.
- a plurality of stripes of spacers 118 are formed on the sidewalls of the stacked gate structures 104 .
- the material of the spacers 118 can be, for example, silicon nitride, which can be fabricated by forming a spacer material layer over the substrate, and then performing an anisotropic etching process.
- the method further comprises forming heavy doping regions in the substrate 100 by using the stacked gate structures 104 and the spacers 118 as a mask.
- dielectric material layers 120 and 122 are sequentially formed over the substrate 100 to cover the stacked gate structures 104 , isolation structures 102 and substrate 100 .
- the etching selectivities of the dielectric material layers 120 and 122 are different, so that the dielectric material layer 120 can serve as an etching stop layer.
- the material of the dielectric material layer 120 can be silicon nitride, while that of the dielectric material layer 122 can be silicon oxide, for example.
- only the dielectric material layer 122 is formed, and the material of the dielectric material layer 122 can be silicon oxide.
- the dielectric material layers 120 and 122 are patterned to form dielectric layers 120 a and 122 a on a portion of the isolation structures 102 adjacent to two rows of stacked gate structures 104 , and openings 124 are formed. Also, one isolation structure 102 is disposed between two neighboring dielectric layers 122 a in the same row, while two neighboring rows comprising the dielectric layer 112 a and isolation structure 102 are arranged in an interlacing manner (as shown in FIG. 1B ). In addition, in an embodiment, the formed dielectric layers 120 a and 122 a extend in two sides to cover a portion of the stacked gate structure 104 .
- self-aligned contact openings (openings 124 ) can be formed between two neighboring stacked gate structures 104 under the protection of the spacers 118 . Therefore, misalignment of contact openings is minimized, and the process window can be increased.
- conductive layers 126 are formed between two neighboring dielectric layers 120 a and 122 a (in openings 124 ) in the same row.
- the formed conductive layers 126 can be self-aligned contacts.
- the material of the conductive layers 126 can be tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material, for example, which can be made by forming a conductive material layer over the substrate 100 to cover the dielectric layers 120 a and 122 a , stacked gate structures 104 and substrate 100 , and then removing the conductive material layer outside the opening 124 to expose the top surfaces of the dielectric layers 122 a , wherein the removing method can be a chemical mechanical polishing process.
- the method further comprises forming a conductive barrier layer to increase the adhesion of the conductive layers 126 .
- a portion of the conductive layers 126 , the dielectric layers 120 a and 122 a is removed on the stacked gate structures 104 to expose the top surfaces of the stacked gate structures 104 .
- the removing method can be a chemical mechanical polishing process, for example.
- a plurality of conductive layers 134 are formed in the openings 130 (as shown in FIG. 1C ).
- the conductive layers 134 can serve as contacts, and electrically connect with the conductive layers 126 a .
- the material of the conductive layers 134 can be, for example, tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material and is formed by forming a conductive material layer over the substrate 100 to cover the entire structure, and then removing the conductive material layer outside the openings 130 , wherein the removing method can be a chemical mechanical polishing process.
- the method before forming the conductive layers 134 , the method further comprises forming a conductive barrier layer to increase the adhesion of the conductive layers 134 .
- bit line 136 connects with the conductive layers 134 in the same column.
- the non-volatile memory comprises a substrate 100 , a plurality of columns of isolation structures 102 , a plurality of rows of stacked gate structures 104 , a plurality of stripes of spacers 118 , a plurality of dielectric layers 112 a , a plurality of conductive layers 126 a and a plurality of doping regions 116 .
- the non-volatile memory further comprises dielectric layers 120 a and 128 and bit lines 136 .
- the isolation structures 102 are located on the substrate 100 , and the isolation structures 102 can be shallow trench isolation structures.
- the stacked gate structures 104 are located on the substrate 100 , and cross over the isolation structures 102 . Also, each stacked gate structure 104 comprises a bottom dielectric layer 106 , a charge storage layer 108 , a top dielectric layer 110 and a control gate layer 112 sequentially disposed over the substrate 100 .
- the spacers 118 are located on the sidewalls of the stacked gate structures 104 .
- the dielectric layers 122 a are located on a portion of the isolation structures 102 between two neighboring rows of stacked gate structures 104 .
- one isolation structure 102 is disposed between two neighboring dielectric layers 122 a in the same row, while two neighboring rows comprising the dielectric layer 112 a and the isolation structure 102 are arranged in an interlacing manner.
- the conductive layers 126 a are located between two neighboring dielectric layers 122 a in the same row.
- the material of the conductive layers 126 a can be, for example, tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material.
- the doping regions 116 are located in the substrate 100 beneath the conductive layers 126 a.
- Each dielectric layer 120 a is located between the dielectric layer 122 a and the isolation structure 102 , and between the dielectric layer 122 a and spacer 118 .
- the etching selectivities of the dielectric layers 120 a and 122 a are different.
- the material of the dielectric layers 120 a can be silicon nitride, while that of the dielectric layers 122 a can be silicon oxide, for example.
- the dielectric layer 128 with a plurality of openings 130 covers a portion of the conductive layers 126 a , the dielectric layers 122 a and the stacked gate structures 104 , and each opening 130 exposes a partial region of the conductive layer 126 a .
- the conductive layers 134 are located in the openings 130 , wherein the material of the conductive layers 134 can be tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material.
- the bit lines 136 are located on the dielectric layer 128 , and each bit line 136 connects with the conductive layers 134 in the same column.
- self-aligned contacts can be formed between two neighboring stacked gate structures by the spacers 118 and the dielectric layers on the isolation structures. Therefore, misalignment of contacts is minimized, and the process window can be increased.
Abstract
A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive: layers are formed between two neighboring first dielectric layers in the same row.
Description
- 1. Field of the Invention
- The present invention relates to a memory device and fabricating method thereof. More particularly, the present invention relates to a non-volatile memory and fabricating method thereof.
- 2. Description of The Related Art
- Non-volatile memory is a type of memory that allows writing, reading and erasing data for multiple times, and the stored data will be retained even after power supplied to the device is off. Furthermore, non-volatile memory also has the advantages of small size, fast access speed and low power consumption. In addition, data can be erased in a block-by-block fashion so that the operating speed is further enhanced. With these advantages, non-volatile memory has become one of the most widely adopted memory devices for personal computers and electronic equipments.
- A typical non-volatile memory comprises an array of memory cells. The horizontally laid memory cells are serially connected through a word line and the vertically laid memory cells are serially connected through a bit line. In general, the control gate of the memory cell serves as the word line, while the source region or drain region of the memory is electrically connected with bit line through the source contact or the drain contact. However, in the process of forming such contacts, misalignment between the contacts and the source regions or the drain regions occurs easily, which would reduce device reliability. Although the misalignment can be corrected through an increased width of the source regions or the drain regions, the size of each device would be enlarged as well. Hence, in view of device integration; a better solution is desired.
- Accordingly, at least one objective of the present invention is to provide a method of fabricating a non-volatile memory capable of resolving the misalignment problem in the conventional contact fabricating process.
- At least a second objective of the present invention is to provide a non-volatile memory having a smaller device dimension so that overall level of integration of the memory can be increased.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a non-volatile memory. First, a substrate is provided. A plurality of columns of isolation structures are formed on the substrate. Thereafter, a plurality of rows of stacked gate structures are formed on the substrate. The stacked gate structures cross over the isolation structures, and each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate. After that, a plurality of doping regions are formed in the substrate, between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures between two neighboring rows of stacked gate structures. Wherein, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. Then, a plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.
- The present invention also provides a non-volatile memory. The non-volatile memory comprises a substrate, a plurality of columns of isolation structures, a plurality of rows of stacked gate structures, a plurality of stripes of spacers, a plurality of first dielectric layers, a plurality of first conductive layers and a plurality of doping regions. The isolation structures are located on the substrate. The stacked gate structures are located on the substrate, and cross over the isolation structures. Also, each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate. The spacers are located on the sidewalls of the stacked gate structures. The first dielectric layers are located on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. The first conductive layers are located between two neighboring first dielectric layers in the same row, and between two spacers in opposite sides. The doping regions are located in the substrate beneath the first conductive layers.
- Because contacts (the first conductive layers) are formed in the first dielectric layers on the isolation structures, misalignment between contacts and the source region or the drain region is minimized in the process of forming contacts, and the process window can be increased.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
-
FIGS. 1A through 1C are top views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention. -
FIGS. 2A through 2D are schematic cross-sectional views along line I-I′ ofFIG. 1A showing the steps for fabricating a non-volatile memory. -
FIGS. 3A through 3D are schematic cross-sectional views along line II-II′ ofFIG. 1A showing the steps for fabricating a non-volatile memory. -
FIGS. 4A through 4D are schematic cross-sectional views along line III-III′ ofFIG. 1A showing the steps for fabricating a non-volatile memory. - Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
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FIGS. 1A through 1C are top views showing the steps for fabricating a non-volatile memory according to one embodiment of the present invention;FIGS. 2A through 2D are schematic cross-sectional views along line I-I′ ofFIG. 1A ;FIGS. 3A through 3D are schematic cross-sectional views along line II-II′ ofFIG. 1A ; andFIGS. 4A through 4D are schematic cross-sectional views along line III-III′ ofFIG. 1A . - First, as shown in
FIGS. 1A, 2A , 3A and 4A, asubstrate 100 is provided. Thesubstrate 100 can be a silicon substrate. Then, a plurality of columns ofisolation structures 102 are formed on thesubstrate 100. Wherein,isolation structures 102 are shallow trench isolation structures, for example, which can be formed by performing a conventional shallow trench isolation structure fabricating process. - Thereafter, a plurality of rows of stacked
gate structures 104 are formed on thesubstrate 100. Also, thestacked gate structures 104 cross over theisolation structures 102, and eachstacked gate structure 104 comprises abottom dielectric layer 106, acharge storage layer 108, atop dielectric layer 110 and acontrol gate layer 112 sequentially disposed over thesubstrate 100. Wherein, thestacked gate structures 104 are defined by amask layer 114, while thecontrol gate layer 112 can serve as a bit line. In an embodiment, thebottom dielectric layer 106 is a tunneling layer fabricated using silicon oxide material, for example. Thecharge storage layer 108 is a charge-trapping layer fabricated using silicon nitride material, for example. Thetop dielectric layer 110 is a charge barrier layer fabricated using silicon oxide material, for example. The control gate layer is a doped polysilicon layer, for example. - After that, a plurality of
doping regions 116 are formed in thesubstrate 100 between two neighboring stackedgate structures 104. Thedoping regions 116 can serve as source regions and drain regions, which can be formed by performing an ion implantation process. - Then, as shown in
FIGS. 2B, 3B and 4B, a plurality of stripes ofspacers 118 are formed on the sidewalls of the stackedgate structures 104. The material of thespacers 118 can be, for example, silicon nitride, which can be fabricated by forming a spacer material layer over the substrate, and then performing an anisotropic etching process. - In an embodiment, after forming
spacers 118, the method further comprises forming heavy doping regions in thesubstrate 100 by using the stackedgate structures 104 and thespacers 118 as a mask. - Thereafter, dielectric material layers 120 and 122 are sequentially formed over the
substrate 100 to cover thestacked gate structures 104,isolation structures 102 andsubstrate 100. In addition, the etching selectivities of the dielectric material layers 120 and 122 are different, so that thedielectric material layer 120 can serve as an etching stop layer. In an embodiment, the material of thedielectric material layer 120 can be silicon nitride, while that of thedielectric material layer 122 can be silicon oxide, for example. In another embodiment, only thedielectric material layer 122 is formed, and the material of thedielectric material layer 122 can be silicon oxide. - Then, as shown in
FIGS. 2C, 3C and 4C, the dielectric material layers 120 and 122 are patterned to formdielectric layers isolation structures 102 adjacent to two rows of stackedgate structures 104, andopenings 124 are formed. Also, oneisolation structure 102 is disposed between two neighboringdielectric layers 122 a in the same row, while two neighboring rows comprising the dielectric layer 112 a andisolation structure 102 are arranged in an interlacing manner (as shown inFIG. 1B ). In addition, in an embodiment, the formeddielectric layers stacked gate structure 104. - It is noted that self-aligned contact openings (openings 124) can be formed between two neighboring stacked
gate structures 104 under the protection of thespacers 118. Therefore, misalignment of contact openings is minimized, and the process window can be increased. - Then,
conductive layers 126 are formed between two neighboringdielectric layers conductive layers 126 can be self-aligned contacts. The material of theconductive layers 126 can be tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material, for example, which can be made by forming a conductive material layer over thesubstrate 100 to cover thedielectric layers gate structures 104 andsubstrate 100, and then removing the conductive material layer outside theopening 124 to expose the top surfaces of thedielectric layers 122 a, wherein the removing method can be a chemical mechanical polishing process. At this time, the conductive material layer cover all of thesubstrate 100, and only the top surfaces of thedielectric layers 122 a are exposed. In an embodiment, before forming theconductive layers 126, the method further comprises forming a conductive barrier layer to increase the adhesion of theconductive layers 126. - Thereafter, as shown in
FIGS. 2D, 3D and 4D, a portion of theconductive layers 126, thedielectric layers stacked gate structures 104 to expose the top surfaces of the stackedgate structures 104. The removing method can be a chemical mechanical polishing process, for example. - After that, a
dielectric layer 128 with a plurality ofopenings 130 is formed over thesubstrate 100 to cover the entire structure, and eachopening 130 exposes a partial region of theconductive layer 126 a. The material of thedielectric layer 128 can be, for example, silicon oxide. Thedielectric layer 128 is made by forming a dielectric material layer over thesubstrate 100 to cover the entire structure, and then performing a patterning process to form theopenings 130. It is noted that the size of theconductive layers 126 a under the dielectric material layer is bigger, so that the process window is big during the patterning process to formopenings 130, and thus misalignment can be avoided. In addition, in an embodiment, before forming the dielectric material layer, the method further comprises forming anotherdielectric layer 132 to serve as an etching stop layer. - Then, a plurality of
conductive layers 134 are formed in the openings 130 (as shown inFIG. 1C ). Theconductive layers 134 can serve as contacts, and electrically connect with theconductive layers 126 a. The material of theconductive layers 134 can be, for example, tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material and is formed by forming a conductive material layer over thesubstrate 100 to cover the entire structure, and then removing the conductive material layer outside theopenings 130, wherein the removing method can be a chemical mechanical polishing process. In an embodiment, before forming theconductive layers 134, the method further comprises forming a conductive barrier layer to increase the adhesion of theconductive layers 134. - Thereafter, a plurality of columns of
bit line 136 are formed on thedielectric layer 128, and eachbit line 136 connects with theconductive layers 134 in the same column. - In the following, the structure fabricated in the above method is described. As shown in
FIGS. 1C, 2D , 3D and 4D, the non-volatile memory comprises asubstrate 100, a plurality of columns ofisolation structures 102, a plurality of rows of stackedgate structures 104, a plurality of stripes ofspacers 118, a plurality of dielectric layers 112 a, a plurality ofconductive layers 126 a and a plurality ofdoping regions 116. In an embodiment, the non-volatile memory further comprisesdielectric layers - The
isolation structures 102 are located on thesubstrate 100, and theisolation structures 102 can be shallow trench isolation structures. Thestacked gate structures 104 are located on thesubstrate 100, and cross over theisolation structures 102. Also, eachstacked gate structure 104 comprises abottom dielectric layer 106, acharge storage layer 108, atop dielectric layer 110 and acontrol gate layer 112 sequentially disposed over thesubstrate 100. - The
spacers 118 are located on the sidewalls of the stackedgate structures 104. Thedielectric layers 122 a are located on a portion of theisolation structures 102 between two neighboring rows of stackedgate structures 104. Also, oneisolation structure 102 is disposed between two neighboringdielectric layers 122 a in the same row, while two neighboring rows comprising the dielectric layer 112 a and theisolation structure 102 are arranged in an interlacing manner. - The
conductive layers 126 a are located between two neighboringdielectric layers 122 a in the same row. The material of theconductive layers 126 a can be, for example, tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material. Thedoping regions 116 are located in thesubstrate 100 beneath theconductive layers 126 a. - Each
dielectric layer 120 a is located between thedielectric layer 122 a and theisolation structure 102, and between thedielectric layer 122 a andspacer 118. The etching selectivities of thedielectric layers dielectric layers 120 a can be silicon nitride, while that of thedielectric layers 122 a can be silicon oxide, for example. - The
dielectric layer 128 with a plurality ofopenings 130 covers a portion of theconductive layers 126 a, thedielectric layers 122 a and thestacked gate structures 104, and eachopening 130 exposes a partial region of theconductive layer 126 a. Theconductive layers 134 are located in theopenings 130, wherein the material of theconductive layers 134 can be tungsten, polysilicon, doped polysilicon, copper, aluminum, or other conductive material. The bit lines 136 are located on thedielectric layer 128, and eachbit line 136 connects with theconductive layers 134 in the same column. - Accordingly, in the present invention, self-aligned contacts can be formed between two neighboring stacked gate structures by the
spacers 118 and the dielectric layers on the isolation structures. Therefore, misalignment of contacts is minimized, and the process window can be increased. - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (11)
1. A method of fabricating a non-volatile memory, comprising:
providing a substrate;
forming a plurality of columns of isolation structures on the substrate;
forming a plurality of rows of stacked gate structures, wherein the stacked gate structures cross over the isolation structures, and each stacked gate structure comprises a bottom dielectric layer, a charge storage layer, a top dielectric layer and a control gate layer sequentially disposed over the substrate;
forming a plurality of doping regions in the substrate between two neighboring stacked gate structures;
forming a plurality of stripes of spacers on the sidewalls of the stacked gate structures;
forming a plurality of first dielectric layers on a portion of the isolation structures adjacent to two rows of stacked gate structures, wherein one isolation structure is between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and isolation structure are arranged in an interlacing manner; and
forming a plurality of first conductive layers between two neighboring first dielectric layers in the same row.
2. The method according to claim 1 , after the step of forming the first conductive layers, the method further comprising:
forming a second dielectric layer with a plurality of openings over the substrate, wherein each opening exposes a partial region of the first conductive layer;
forming a plurality of second conductive layers in the openings; and
forming a plurality of columns of bit lines on the second dielectric layer, each bit line connecting with the second dielectric layers in the same column.
3. The method according to claim 2 , wherein a material of the second conductive layers comprises tungsten, polysilicon, doped polysilicon, copper or aluminum.
4. The method according to claim 1 , wherein each formed first dielectric layer extends in two sides to cover a portion of the stacked gate structure.
5. The method according to claim 4 , wherein the step of forming the first conductive layers comprises:
forming a conductive material layer over the substrate to cover the first dielectric layers, the stacked gate structures and the substrate;
removing a portion of the conductive material layer to expose the top surfaces of the first dielectric layers; and
removing a portion of the conductive material layer and the first dielectric layers on the stacked gate structures to expose the top surfaces of the stacked gate structures.
6. The method according to claim 1 , wherein the step of forming the first dielectric layers comprises:
forming a first dielectric material layer over the substrate to cover the stacked gate structures, the isolation structures and the substrate; and
patterning the first dielectric material layer.
7. The method according to claim 6 , further comprising forming a second dielectric material layer over the substrate before forming the first dielectric material layer.
8. The method according to claim 7 , wherein the etching selectivities of the first dielectric material layer and the second dielectric material layer are different.
9. The method according to claim 1 , wherein a material of the first conductive layers comprises tungsten, polysilicon, doped polysilicon copper or aluminum.
10. The method according to claim 1 , wherein the control gate layer serves as a bit line.
11-17. (canceled)
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US9153483B2 (en) * | 2013-10-30 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of semiconductor integrated circuit fabrication |
US10515896B2 (en) * | 2017-08-31 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure for semiconductor device and methods of fabrication thereof |
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US5416349A (en) * | 1993-12-16 | 1995-05-16 | National Semiconductor Corporation | Increased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts |
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US6169025B1 (en) * | 1997-03-04 | 2001-01-02 | United Microelectronics Corp. | Method of fabricating self-align-contact |
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US6765259B2 (en) * | 2002-08-28 | 2004-07-20 | Tower Semiconductor Ltd. | Non-volatile memory transistor array implementing “H” shaped source/drain regions and method for fabricating same |
-
2005
- 2005-07-11 US US11/180,117 patent/US7157333B1/en active Active
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US5416349A (en) * | 1993-12-16 | 1995-05-16 | National Semiconductor Corporation | Increased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts |
US5589413A (en) * | 1995-11-27 | 1996-12-31 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing self-aligned bit-line during EPROM fabrication |
US6169025B1 (en) * | 1997-03-04 | 2001-01-02 | United Microelectronics Corp. | Method of fabricating self-align-contact |
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US6765259B2 (en) * | 2002-08-28 | 2004-07-20 | Tower Semiconductor Ltd. | Non-volatile memory transistor array implementing “H” shaped source/drain regions and method for fabricating same |
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US7157333B1 (en) | 2007-01-02 |
US20070026609A1 (en) | 2007-02-01 |
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