US8183162B2 - Method of forming a sacrificial layer - Google Patents

Method of forming a sacrificial layer Download PDF

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Publication number
US8183162B2
US8183162B2 US12/536,805 US53680509A US8183162B2 US 8183162 B2 US8183162 B2 US 8183162B2 US 53680509 A US53680509 A US 53680509A US 8183162 B2 US8183162 B2 US 8183162B2
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applying
layer
wet etching
etching process
patterned photoresist
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US20100093176A1 (en
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Ching-Yu Chang
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to CN2009101691434A priority patent/CN101789367B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means

Definitions

  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • a metal layer is deposited and etched.
  • the etch processing window is not enough and the photoresist (resist) may experience a peeling issue at the metal etch step.
  • the exposed metal film cannot be completely etched away and the patterned resist can be peeled from the underlying metal film.
  • the wet etch solution can penetrate to the interface between the patterned resist and the metal film and oxidize the metal film underlying the patterned resist. This further changes the metal film and degrades the device performance.
  • first and second features are formed in direct contact
  • additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
  • FIG. 1 is a flowchart of a method making a semiconductor device in one embodiment constructed according to aspects of the present disclosure.
  • FIGS. 2 through 8 are sectional views of one embodiment of a semiconductor structure having a metal gate stack at various fabrication stages constructed according to aspects of the present disclosure.
  • first and second features are formed in direct contact
  • additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
  • FIG. 1 is a flowchart of one embodiment of a method 100 making a semiconductor device having a metal gate stack constructed according to aspects of the present disclosure.
  • FIGS. 2 through 8 are sectional views of one embodiment of a semiconductor structure 200 at various fabrication stages. The method 100 of making a semiconductor device is described with reference to FIGS. 1 through 8 .
  • the method 100 begins at step 102 by providing a semiconductor substrate 210 .
  • the semiconductor substrate 210 includes silicon.
  • the substrate 210 includes germanium, silicon germanium or other suitable semiconductor material, such as diamond, silicon carbide or gallium arsenic.
  • the substrate 210 may further include additional features and/or material layers, such as various isolation features formed in the substrate.
  • the substrate 210 may include various p-type doped regions and/or n-type doped regions configured and coupled to form various devices and functional features. All doping features may be achieved using a process such as ion implantation or diffusion in various steps and techniques.
  • the substrate 210 may include other features such as a shallow trench isolation (STI).
  • STI shallow trench isolation
  • the substrate 210 may further include various dielectric-metal-gate-stack material layers.
  • a high k dielectric material layer is formed on the semiconductor substrate 210 .
  • the high k dielectric material layer is formed by a suitable process such as an atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • Other methods to form the high k dielectric material layer include metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), UV-Ozone Oxidation and molecular beam epitaxy (MBE).
  • MOCVD metal organic chemical vapor deposition
  • PVD physical vapor deposition
  • UV-Ozone Oxidation and molecular beam epitaxy
  • the high k dielectric material includes HfO2.
  • the high k dielectric material layer includes metal nitrides, metal silicates or other metal oxides.
  • a capping layer may be further formed on the high k dielectric material layer.
  • the capping layer includes lanthanum oxide (LaO).
  • the capping layer includes aluminum oxide (Al2O3).
  • the capping layer may alternatively includes other suitable material.
  • An interfacial layer may be interposed between the semiconductor substrate 210 and the high k dielectric material layer.
  • the interfacial layer may include a thin silicon oxide layer and is formed on the silicon substrate 210 before forming the high k dielectric material layer.
  • the thin silicon oxide layer may be formed by atomic layer deposition (ALD) or thermal oxidation.
  • the method 100 proceeds to step 104 by forming a first material layer 212 on the substrate 210 and a second material layer 214 on the first material layer 212 .
  • the first and second material layers each has a thickness less than about 100 angstrom.
  • the first material layer 212 includes a metal.
  • the metal layer includes titanium nitride (TiN).
  • the metal layer includes tantalum nitride (TaN), molybdenum nitride (MoN), tungsten nitride (WN), tungsten (W), tantalum carbide (TaC), tantalum carbide nitride (TaCN), titanium aluminum nitride (TiAlN), aluminum, (Al), tungsten (W) or polysilicon.
  • the metal layer is formed by a physical vapor deposition (PVD) technique or other suitable method.
  • the metal layer may have a thickness ranging between 5 angstrom and 100 angstrom. As an example, the metal layer has a thickness of about 50 angstrom.
  • the second material layer 214 is a sacrificial material layer that is implemented during the disclosed process to pattern the metal layer and is removed thereafter.
  • the sacrificial material layer include lanthanum oxide (LaO).
  • the sacrificial material layer includes aluminum oxide (Al2O3).
  • the sacrificial material layer may have a thickness ranging between 5 angstrom and 100 angstrom. As an example, the sacrificial material layer has a thickness of about 20 angstrom.
  • the sacrificial material layer may be formed by PVD or other suitable method.
  • the method 100 proceeds to step 106 by forming a patterned photoresist layer 216 on the substrate 210 .
  • the patterned photoresist layer 216 is used as a mask to pattern the sacrificial material layer and the metal layer. Particularly, the patterned photoresist layer 216 is formed on the sacrificial material layer as illustrated in FIG. 3 .
  • the patterned photoresist layer is formed by a photolithography process.
  • An exemplary photolithography process may include processing steps of photoresist coating, soft baking, mask aligning, exposing, post-exposure baking, developing photoresist and hard baking.
  • the lithography process may implement krypton fluoride (KrF) excimer lasers, argon fluoride (ArF) excimer lasers, ArF immersion lithography, extreme ultra-violet (EUV) or electron-beam writing (e-beam).
  • the photolithography exposing process may also be implemented or replaced by other proper methods such as maskless photolithography, ion-beam writing, and molecular imprint.
  • a hexamethyl disilazane (HMDS) solution is applied to the sacrificial material layer to enhance resist adhesion before the coating on the resist layer.
  • the patterned resist layer 216 defines various openings to expose the underlying sacrificial material layer.
  • the patterned photoresist layer define various gate regions or the openings of the patterned resist layer defines the regions wherein the gate stack material layers is to be removed.
  • the method 100 may include an additional cleaning step after the formation of the patterned resist layer.
  • a cleaning material 218 is applied to the patterned resist layer to clean organic residue or other residues.
  • the cleaning material is capable of removing the organic residue.
  • the cleaning material includes a top anti-reflective coating (TARC) layer.
  • TARC top anti-reflective coating
  • the cleaning material includes solvent, surfactant or polymer ingredient.
  • the method 100 proceeds to step 108 by applying a first wet etchant 220 in a first wet etching process to the substrate to etch the sacrificial material layer using the patterned resist layer as an etch mask.
  • the sacrificial material layer within the openings of the patterned mask is removed by the first wet etching process and the metal layer 212 is exposed thereafter.
  • LaO is used as the sacrificial material layer and the first etching process utilizes hydrochloric acid (HCl).
  • the first wet etching solution includes HCl and water (H2O). The HCl/H2O ration may range from about 1:1 to about 1:1000.
  • the etching duration may have a range between about 5 second and about 5 minute.
  • the first wet etching solution includes a weak acid.
  • the weak acid solution include carbon oxide (CO2) water.
  • the first wet etching solution includes, acetic acid solution, citric acid, boric acid or phosphoric acid.
  • the sacrificial material layer includes Al2O3 and the first wet etchant includes a resist developer.
  • TMAH tetramethylammonium hydroxide
  • a wet etching solution having a pH value below than 7 may be used to etch the LaO sacrificial material layer.
  • a wet etching solution having a pH value higher than 8 may be used to etch the Al2O3 sacrificial material layer.
  • the method 100 proceeds to step 110 by applying a wet etchant 220 to the second material layer 212 .
  • the metal layer 212 includes titanium nitride (TiN).
  • the wet etching process applied to the TiN layer at this step includes an ammonia hydroxide-hydrogen peroxide-water mixture (APM) solution.
  • API ammonia hydroxide-hydrogen peroxide-water mixture
  • the method 100 proceeds to step 112 by applying a stripping solution 222 to remove the patterned resist layer 216 .
  • a stripping solution is used.
  • the stripping solution includes N-methyl-2-pyrrolidine (NMP), cyclohexanol, cyclopentanol, dimethy sulfoxide (DMSO), propylene glycol monomethyl ether (PGME) or Propylene glycol monomethyl ether acetate (PGMEA).
  • the step 112 to remove the patterned resist layer by the stripping solution can be performed between the step 108 to wet etch the sacrificial material layer 214 and the step 110 to wet etch the metal layer 212 .
  • the patterned sacrificial material layer is used as the mask to etch the metal layer.
  • the method 100 proceeds to step 114 by applying a second wet etchant to the substrate to remove the patterned sacrificial material layer.
  • the second wet etchant is similar to the first etchant used at step 108 to pattern the sacrificial material layer.
  • the patterned sacrificial material layer includes LaO and the second etchant includes hydrochloric acid (HCl).
  • the first wet etching solution includes HCl and water (H2O).
  • the HCl/H2O ratio may range from about 1:1 to about 1:1000.
  • the etching duration may have a range between about 5 second and about 5 minute.
  • the first wet etching solution includes a weak acid.
  • the weak acid solution include carbon oxide (CO2) water.
  • the first wet etching solution includes, acetic acid solution, citric acid, boric acid or phosphoric acid.
  • the patterned sacrificial material layer includes Al2O3 and the second wet etchant includes a resist developer.
  • TMAH tetramethylammonium hydroxide
  • the wet etching process to the first material layer may use the patterned sacrificial material layer as an etching mask. Therefore, the etch time may be longer without the resist peeling issue.
  • the wet etchant used to pattern the first material layer has a higher wet etch selectivity relative to the sacrificial material layer.
  • the second material layer is not necessarily thick. The wet etch time to the second material layer can be reduced and the resist peeling issue is also eliminated.
  • the porous TiN will no longer absorb or adhere to PR during and after the associated wet etching process. Therefore, the resist residue on TiN surface is also eliminated.
  • the sacrificial material layer since the sacrificial material layer is completely removed afterward, the resist residue, if any, will be cleaned away as well after the sacrificial material layer is removed.
  • the sacrificial material layer includes metal oxide and can also be used as a stop layer to eliminate H2O2 oxidation to the first metal layer.
  • the first material layer when the sacrificial material layer is formed on the first material layer, the first material layer will have a good lateral etch control.
  • the first material layer may alternatively include other material layer to be patterned.
  • the first material layer includes high k dielectric material layer, such as hafnium oxide.
  • the second material layer can include other suitable metal oxide to be implemented in this wet etch process flow to pattern metal gate stack with reduced or eliminated resist peeling issue.
  • additional patterning steps may be applied to the substrate to further pattern the metal gate stack.
  • the light doped drain (LDD) regions are formed after the formation of the gate stack.
  • a gate spacer may be formed on the sidewalls of the metal gate stack. Then the source and drain regions are formed substantially aligned with the outer edges of the spacers.
  • the gate spacers may have a multilayer structure and may include silicon oxide, silicon nitride, silicon oxynitride, or other dielectric material.
  • the doped source and drain regions and LDD regions of either an n-type dopant or a p-type dopant are formed by a conventional doping process such as ion implantation.
  • N-type dopant impurities employed to form the associated doped regions may include phosphorus, arsenic, and/or other materials.
  • P-type dopant impurities may include boron, indium, and/or other materials.
  • the multilayer interconnection are further formed.
  • the multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines.
  • the various interconnection features may implement various conductive materials including copper, tungsten and silicide.
  • a damascene process is used to form copper related multilayer interconnection structure.
  • tungsten is used to form tungsten plug in the contact holes.
  • the semiconductor substrate may further include additional isolation features to isolate each from other devices.
  • the isolation features may include different structures and can be formed using different processing technologies.
  • an isolation feature may include shallow trench isolation (STI) features.
  • STI shallow trench isolation
  • the formation of STI may include etching a trench in a substrate and filling the trench by insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the filled trench may have a multi-layer structure such as a thermal oxide liner layer with silicon nitride filling the trench.
  • the STI structure may be created using a process sequence such as: growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning an STI opening using photoresist and masking, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, using chemical mechanical planarization (CMP) to etch back, and using nitride stripping to leave the STI structure.
  • LPCVD low pressure chemical vapor deposition
  • CMP chemical mechanical planarization
  • the semiconductor structure 200 serves only as one example of a device within which various aspects of the method 100 may be implemented.
  • the disclosed semiconductor structure and the method of making the same may be used in other semiconductor devices having metal gate features, such as strained semiconductor substrate, a hetero-semiconductor device or a stress-free isolation structure.
  • the semiconductor structure 200 may include a dynamic random access memory (DRAM) cell, a single electron transistor (SET), and/or other microelectronic devices (collectively referred to herein as microelectronic devices).
  • the semiconductor structure 150 includes FinFET transistors.
  • aspects of the present disclosure are also applicable and/or readily adaptable to other type of transistor, including single-gate transistors, double-gate transistors and other multiple-gate transistors, and may be employed in many different applications, including sensor cells, memory cells, logic cells, and others.
  • the second material layer may include tungsten oxide.
  • the disclosed method is used to form one or more metal-oxide-semiconductor field-effect-transistors (MOSFETs).
  • MOSFETs metal-oxide-semiconductor field-effect-transistors
  • the disclosed method is used to form a metal gate stack in a gate-first process in which the metal gate stack is formed by the disclosed method and remains in the final structure.
  • the disclosed method is used to form a metal gate stack in a hybrid process in which the first type metal gate stack (such as NMOS metal gate stack) is formed by the disclosed method and remains in the final structure.
  • the second type of the metal gate stack (such as PMOS metal gate stack) is formed as a dummy gate structure so that source/drain ion implantation processes and annealing processes can be implemented. Thereafter, a portion of the dummy gate stack is removed and the dummy gate trench is refilled with proper materials.
  • the disclosed method is used to form a metal gate stack in a gate-last process in which a dummy metal gate stack is formed by the disclosed method and is then, after the formation of the source and drain features, replaced with final metal layer materials collectively or individually for NMOS and PMOS.
  • the semiconductor substrate may include an epitaxial layer.
  • the substrate may have an epitaxial layer overlying a bulk semiconductor.
  • the substrate may be strained for performance enhancement.
  • the epitaxial layer may include a semiconductor material different from those of the bulk semiconductor such as a layer of silicon germanium overlying a bulk silicon, or a layer of silicon overlying a bulk silicon germanium formed by a process including SEG.
  • the substrate may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer.
  • SOI semiconductor-on-insulator
  • the present disclosure provides a method for making a semiconductor device.
  • the method includes forming a material layer on a substrate; forming a sacrificial layer on the material layer, wherein the material layer and sacrificial layer each as a thickness less than 100 angstrom; forming a patterned photoresist layer on the sacrificial layer; applying a first wet etching process to the substrate to etch the sacrificial layer to form a patterned sacrificial layer using the patterned photoresist layer as a mask; applying a second wet etching process to the substrate to etch the material layer; and applying a third wet etching process to remove the patterned sacrificial layer.
  • the disclosed method may further include applying a wet chemical to the substrate to remove the patterned photoresist layer after the applying the first wet etching process and before the applying the third wet etching process.
  • the applying the wet chemical to the substrate may be implemented before the applying the second wet etching process.
  • the material layer includes titanium nitride (TiN).
  • the sacrificial layer includes lanthanum oxide (LaO).
  • the first and third wet etching processes each includes an etchant having a hydrochloric acid (HCl).
  • the first and third wet etching processes each include applying carbon oxide (CO2) water.
  • the sacrificial layer includes aluminum oxide (Al2O3).
  • the first and third wet etching processes each includes applying a tetramethylammonium hydroxide (TMAH) solution.
  • the first wet etching process may include applying a weak acid solution to the substrate, the weak acid solution is selected from the group consisting of CO2 water, acetic acid solution, citric acid, boric acid and phosphoric acid.
  • the second wet etching process may include applying an ammonia hydroxide-hydrogen peroxide-water mixture (APM) to the substrate.
  • the method may further include applying hexamethyl disilazane (HMDS) to the sacrificial material layer before the forming the patterned photoresist layer.
  • the method may further include applying a cleaning material to the patterned photoresist layer before the applying the first wet etching process.
  • HMDS hexamethyl disilazane
  • the present disclosure also provides another embodiment of a method for making a semiconductor device.
  • the method includes forming a titanium nitride (TiN) layer on a substrate; forming a lanthanum oxide ((LaO) layer on the TiN layer; forming a patterned photoresist layer on the LaO layer; applying a first wet etching process to the substrate to etch the LaO layer to form a patterned LaO layer using the patterned photoresist layer as a mask; applying an ammonia hydroxide-hydrogen peroxide-water mixture (APM) to the substrate to etch the TiN layer; and applying a second wet etching process to remove the LaO layer.
  • TiN titanium nitride
  • APM ammonia hydroxide-hydrogen peroxide-water mixture
  • the disclosed method may further include applying a wet chemical to the substrate to remove the patterned photoresist layer after the applying the first wet etching process and before the applying the APM.
  • the method may further include applying a wet chemical to the substrate to remove the patterned photoresist layer after the applying the APM and before the applying the second wet etching process.
  • the wet chemical may be selected from the group consisting of N-methyl-2-pyrrolidine (NMP), cyclohexanol, cyclopentanol, dimethy sulfoxide (DMSO), propylene glycol monomethyl ether (PGME) and Propylene glycol monomethyl ether acetate (PGMEA).
  • the first and second wet etching processes each includes an etchant having hydrochloric acid (HCl) and water (H2O) in one embodiment.
  • the first and second wet etching processes each may include an etchant having a photoresist developer.
  • the first wet etching process may include applying to the substrate with a weak acid solution selected from the group consisting of carbon oxide (CO2) water, acetic acid solution, citric acid, boric acid and phosphoric acid.
  • the present disclosure also provides a method for making a semiconductor device.
  • the method includes forming a first material layer on a substrate; forming a second material layer on the first material layer; forming a patterned photoresist layer on the second layer; applying a first wet etching process to the substrate to etch the second material layer to form a patterned second material layer using the patterned photoresist layer as a mask; applying an ammonia hydroxide-hydrogen peroxide-water mixture (APM) to the substrate to etch the first material layer; and applying a second wet etching process to remove the patterned first material layer.
  • APM ammonia hydroxide-hydrogen peroxide-water mixture
  • the first material layer may include a material selected from the group consisting of MoN, TaC, TiN, TiAlN, TaN, Al and polysilicon.
  • the applying the APM may include patterning the first material layer to form a metal gate of a field-effect transistor (FET).
  • the second material layer includes lanthanum oxide (LaO) in one embodiment.
  • the first and second wet etching processes each may include applying a chemical solution with a pH value less than about 7. In this case, the first and second wet etching processes each may include applying hydrochloric acid (HCl) and water (H2O).
  • the second material layer may include aluminum oxide (Al2O3).
  • the first and second wet etching processes each may include applying a chemical solution with a pH value higher than about 8.
  • the first and second wet etching processes each may include applying a tetramethylammonium hydroxide (TMAH) solution.
  • TMAH tetramethylammonium hydroxide

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TWI409871B (zh) 2013-09-21

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