US7536610B2 - Method for detecting resistive-open defects in semiconductor memories - Google Patents

Method for detecting resistive-open defects in semiconductor memories Download PDF

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Publication number
US7536610B2
US7536610B2 US10/892,696 US89269604A US7536610B2 US 7536610 B2 US7536610 B2 US 7536610B2 US 89269604 A US89269604 A US 89269604A US 7536610 B2 US7536610 B2 US 7536610B2
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semiconductor memory
bits
data
address bits
memory
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Expired - Fee Related, expires
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US10/892,696
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US20050216799A1 (en
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Mohamed Azimane
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NXP BV
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Koninklijke Philips Electronics NV
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation

Definitions

  • the present invention relates to the field of testing of semiconductor memories and in particular, to a method for resistive-open defects in semiconductor memories.
  • embedded semiconductor memories are operating at high speed with clock cycles reaching 2 ns for SRAMS, or even less for the new generation of CMOS whose critical dimensions are on the order of 90 nanometers.
  • Testing of the embedded semiconductor memories is generally performed by Built-In-Self-Test (BIST) or a tester using scan test mode.
  • BIST Built-In-Self-Test
  • the tester consecutive test patterns are generated to perform read and write operations at the memory, according to a predetermined March test.
  • the march test is well known in the art and is often considered a sufficient test for semiconductor memories.
  • Resistive open defects not only cause static faulty behavior of the semiconductor memory, which is easily detected, but also dynamic faulty behavior known as “slow to rise” and “slow to fall” either in the data path or the address path.
  • the delays vary considerably. Big delays resulting in static faulty behavior are easily detected.
  • the detection of small delays corresponding to small sized defects requires high speed testing using the BIST or scan test. Ideally, the semiconductor memories need to be tested at their operating frequency. If a semiconductor memory is not tested at the operating frequency, small sized resistive open defects are not detected even with the correct test patterns applied.
  • a high speed BIST is not easily incorporated into the memory layout, because of the delay needed for the output analyzer of the BIST, the extra time needed for the synthesis, and the additional area needed for the high speed BIST.
  • Increasing the speed of the BIST implies a substantial increase in area for the BIST, which is unacceptable for most applications.
  • testing embedded semiconductor memories using scan test mode needs additional test time due to scan-in and scan-out of the data, which is done in series, and, therefore, substantially increases the test time for big memories with a high number of pins.
  • resistive-open defects are becoming the dominant defects. For example, in an aluminum process, resistive metal bridging is more prevalent than resistive opens. In contracts, in a copper process, resistive opens are more prevalent.
  • testing at frequencies below the operating frequency of a semiconductor memory may result in undetected delay faults such as those manifested by resistive open defects, resistive bridges, and capacitive coupling.
  • the present invention has been found useful in detecting resistive-open defects in semiconductor memories. These resistive-open defects manifest themselves as delay faults leading to slow-to-rise and slow-to-fall behavior at the memory address decoder, the pre-charge circuits, the write data lines, the global inputs/outputs, and also in the memory cell matrix.
  • the invention provides a reliable method for detecting these delay faults.
  • invention there is a method for detecting delay faults in a semiconductor memory.
  • the method comprises generating address bits and data bits according to a test pattern suitable for testing the semiconductor memory.
  • the address bits and data bits are validated.
  • the address bits and data bits are provided to input ports of the semiconductor memory.
  • memory operation is started, wherein a time interval between the provision of the address bits and the data bits and the start of the memory operation is approximately equal to an operating clock cycle of the semiconductor memory.
  • a method for detecting delay faults in a semiconductor memory comprises generating address bits and data bits according to a test pattern suitable for testing the semiconductor memory.
  • the address bits and data bits are validated.
  • the address bits and the data bits are provided to the input ports of the semiconductor memory.
  • the data bits are written into the semiconductor memory.
  • second address bits are generated. The second address bits are validated.
  • the second data bits out of semiconductor memory are read.
  • the second data bits are compared with predetermined data to obtain a comparison result and if the comparison result is indicative of a match indicating that the operation was fault free.
  • a test circuitry for detecting delay faults in a semiconductor memory comprising address and data generating circuitry for generating address bits and data bits according to a test pattern suitable for testing the semiconductor memory.
  • validation circuitry for validating the address bits and the data bits.
  • Connecting circuitry in communication with the semiconductor memory for provides the address bits and the data bits to the semiconductor memory.
  • Timing circuitry for provides a time signal for timing the provision of the address bits and the data bits and start of the memory operation such that a time interval between the provision of the address bits and the data bits and the start of the memory operation is approximately equal to an operating clock cycle of the semiconductor memory.
  • FIG. 1 is a flowchart of testing of the memory according to an embodiment of the present invention
  • FIG. 2 is a diagram schematically illustrating address and data set-up time in a BIST
  • FIG. 3 is a diagram schematically illustrating simulation results of a semiconductor memory test
  • FIG. 4 is a diagram schematically illustrating simulation results of a semiconductor test with an injected open defect at the least significant bit of the X address decoder
  • FIG. 5 is a diagram schematically illustrating an enlarged portion of the diagram shown in FIG. 4 ;
  • FIG. 6 is a diagram schematically illustrating simulation results of a semiconductor test using the method according to the invention.
  • the invention will be described in connection with the BIST for simplicity. As will become evident, the invention also may be implemented using a tester in scan test mode.
  • the frequency of the BIST has a significant impact on the delay fault detection.
  • High speed testing increases detection of delay faults by detecting small delay faults caused, for example, by resistive open defects.
  • implementation of the BIST at high testing frequency is not feasible in most applications.
  • the BIST generates data with corresponding addresses and runs consecutive write and read operations in increasing and decreasing address order.
  • an output analyzer of the BIST compares the read out data with predetermined logic values. If the read out data match the logic values, the memory is fault free, otherwise, the memory is faulty.
  • FIG. 2 illustrates the wave forms of the data and address generation 221 , 231 in relation to a signal provided by a test clock CL.
  • Address and data set-up time are defined as the time between address generation ( 222 , 223 ) and data generation ( 232 , 233 ) and a positive edge of the test clock CL.
  • the process steps 100 of the BIST are shown in FIG. 1 .
  • the BIST Depending upon the march test, the BIST generates the address and data backgrounds 110 .
  • the BIST holds the state of the memory in order for the data bits and the address bits to become valid 120 .
  • the address and data background are delivered to the memory inputs 130 .
  • memory operation is begun 140 .
  • the memory operation may either be a read or a write.
  • the data background is either written to the memory or is read out from the memory 160 .
  • the read out data is compared with predetermined logic values 170 .
  • the above steps are repeated depending on the complexity of the test patterns and the memory size.
  • the end of testing is reported by the BIST when a ready signal is delivered together with a second flag indicating the tested device being fault free or faulty.
  • FIG. 2 shows the waveforms of the address generation 230 and data generation 220 with the memory clock (CL) 210 .
  • the setup time 225 , 235 for the address and data is the time (which includes a hold time 222 , 232 and data valid interval 223 , 233 ) that exists between the address and data background generation ( 221 , 231 ) and the positive/negative edge of the clock.
  • the address and data generation is performed at a lower frequency than the operating frequency of present semiconductor memories.
  • delay faults are masked when the test patterns—address bits and data bits—are delivered to the memory inputs for a relatively long time before the start of the memory operation—positive/negative edge of the clock signal.
  • a BIST operating at 50 MHz needs 20 ns for generating address bits and data bits, and data comparison for the output analyzer in case of a read operation. Therefore, approximately 10 ns are needed to generate and deliver a set of address bits and data bits to the memory inputs.
  • a semiconductor memory is operating at 2 ns clock cycle, if the address bits and data bits are delivered to the memory approximately 10 ns before the positive/negative edge of the clock signal, the periphery circuitry of the memory is already in a substantially stable state before the positive/negative edge of the clock signal. Therefore, a delay fault caused by a defect in the memory periphery is not detected during application of the test pattern due to a delay of 10 ns before the positive/negative edge of the clock signal masking the delay fault.
  • the memories are self-timed, i.e. an internal clock for controlling the read/write operation is generated based on the positive/negative edge of an external clock signal.
  • the self-timing techniques avoid incomplete read/write operations to occur.
  • the state of the memory circuit before the positive/negative edge of the internal clock is critical. Small delay faults are detected when the state of the memory circuit is not yet stable due to the delay fault.
  • the positive/negative edge of the external clock signal is on time, the internal clock signal of the memory is generated and the memory circuit is still not yet stable.
  • the delay fault has an impact on the memory behavior and is detected. Therefore, the time interval separating the positive/negative clock edge and the delivery of the memory inputs is critical.
  • address decoder When the time interval between the provision of the address bits and data bits and the positive/negative clock edge is large compared to the memory clock cycle then address decoder, write circuitry, sense amplifiers, pre-charge and discharge circuitry are already stable before the positive/negative clock edge initiates the read/write operation.
  • a simulation result 300 of a march test of a memory with six output 320 pins q[0, . . . ,5] is shown.
  • the memory operates at 2 ns clock cycle, while the BIST performs the March test at 50 MHz-20 ns clock cycle.
  • the address and data set-up time is approximately 10 ns.
  • the output pins 320 and the clock 310 are plotted.
  • FIG. 4 illustrates the simulation results 400 performed under same conditions with an injected open defect at the least significant bit of the X address decoder.
  • This open defect results in a slow-to-rise fault indicated in the waveform 415 of the V(a — 2_open) diagram.
  • the slow-to-rise fault 425 is more clearly visible in the enlarged section shown in FIG. 5 .
  • this defect is not detected when the BIST is operated at a frequency lower than the operating frequency of the semiconductor memory. Referring to FIG.
  • the slow-to-rise fault 425 is zoomed in the plot 500 , pin a — 2_( 510 ) is a pin without resistive defects. Pin a — 2_open ( 520 ) reaches a logic-one 5 ns later.
  • the time between the delivery of the address bits and the data bits to the memory inputs and the start of the memory operation is reduced either by shifting the positive/negative clock edge or the address and data validation in order to detect delay faults.
  • data bits and address bits are generated depending on a test pattern such as a march test.
  • the address bits and data bits are then validated.
  • After the validation the address bits and data bits are then delivered to the memory inputs.
  • the positive/negative edge of the test clock starts memory operation—read or write—depending on a write enable signal.
  • the delivery of the address bits and data bits and the start of the memory operation are timed such that a time interval therebetween is approximately equal to an operating clock cycle of the semiconductor memory.
  • the appropriate time interval is obtained by appropriate timing of the address and data validation or, alternatively, by appropriate timing of the positive/negative edge of the test clock.
  • the data bits are read out of the memory and compared with predetermined logic values.
  • the above steps are repeated by generating data bits and address bits and running consecutive write and read operations in, for example, increasing or decreasing address order.
  • the read out data bits match the predetermined values; otherwise if, for example, one data bit does not match the predetermined value, the memory is determined to be faulty.
  • the above method for detecting delay faults in semiconductor memories is highly advantageous, enabling delay fault detection using a BIST operating at a frequency below the operating frequency of the semiconductor memory. For instance, a semiconductor memory operating at 200 MHz needs to be tested at the same frequency or smaller delay faults are not detected. Testing the semiconductor memory at 50 MHz or even 150 MHz using a conventional BIST does not enable detection of small delay faults.
  • By timing the delivery of the address bits and data bits and the start of the memory operation such that the time interval therebetween is approximately equal to the operating clock cycle of the semiconductor memory both the address decoder and the read/write circuitry are stressed in time appropriately, enabling detection of small delay faults.
  • the method according to the invention is also applicable for testing self-timed semiconductor memories using the positive/negative edge of the internal memory clock signal.
  • the BIST is implemented such that it is operating at a maximum possible frequency—maximum possible trade off area—and the frequency gap between the BIST frequency and the operating frequency of the memory is then compensated by appropriate timing of the delivery of the address bits and data bits and the start of the memory operation.
  • FIG. 6 illustrates a simulation similar to that of FIG. 4 with the timing arranged according to an embodiment of the present invention.
  • the simulation 600 shows that the delay fault is detected when the appropriate timing of the delivery of the address bits and data bits and the start of the memory operation is applied.
  • the memory outputs q — 1 and q — 2 provide unexpected logic values 620 at 50 ns, while all memory outputs provide incorrect logic values 630 at 240 ns.
  • the method according to the invention is easily implemented in conventional BIST circuitry or tester circuitry enabling operation of the BIST or the tester at a lower frequency than the operating frequency of the memory under test while enabling detection of small delay faults.

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
US10/892,696 2004-03-26 2004-07-15 Method for detecting resistive-open defects in semiconductor memories Expired - Fee Related US7536610B2 (en)

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US10/892,696 US7536610B2 (en) 2004-03-26 2004-07-15 Method for detecting resistive-open defects in semiconductor memories

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US (1) US7536610B2 (ja)
EP (1) EP1738375B1 (ja)
JP (1) JP2007531191A (ja)
CN (1) CN1934655B (ja)
AT (1) ATE396484T1 (ja)
DE (1) DE602005007003D1 (ja)
WO (1) WO2005093761A1 (ja)

Families Citing this family (5)

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KR100582391B1 (ko) * 2004-04-08 2006-05-22 주식회사 하이닉스반도체 반도체 소자에서의 지연 요소의 지연 검출 장치 및 방법
US7475314B2 (en) * 2005-12-15 2009-01-06 Intel Corporation Mechanism for read-only memory built-in self-test
CN102486938B (zh) * 2010-12-06 2015-01-07 北大方正集团有限公司 一种快速检测存储器的方法及装置
US9104635B2 (en) 2011-12-28 2015-08-11 Intel Corporation Memory timing optimization using pattern based signaling modulation
US9076558B2 (en) * 2012-11-01 2015-07-07 Nanya Technology Corporation Memory test system and memory test method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621739A (en) * 1996-05-07 1997-04-15 Intel Corporation Method and apparatus for buffer self-test and characterization
US5787092A (en) * 1997-05-27 1998-07-28 Hewlett-Packard Co. Test chip circuit for on-chip timing characterization
US5936977A (en) * 1997-09-17 1999-08-10 Cypress Semiconductor Corp. Scan path circuitry including a programmable delay circuit
US20020059543A1 (en) * 2000-11-13 2002-05-16 Wu-Tung Cheng Full-speed bist controller for testing embedded synchronous memories

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399912A (en) * 1992-01-13 1995-03-21 Hitachi, Ltd. Hold-type latch circuit with increased margin in the feedback timing and a memory device using same for holding parity check error
JPH09507945A (ja) * 1994-11-09 1997-08-12 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ メモリアドレスデコーダと誤り許容メモリアドレスデコーダをテストする方法
KR100211609B1 (ko) * 1997-06-30 1999-08-02 윤종용 이중에지 클록을 사용한 집적회로 소자 검사방법
TW535161B (en) * 1999-12-03 2003-06-01 Nec Electronics Corp Semiconductor memory device and its testing method
DE10035169A1 (de) * 2000-07-19 2002-02-07 Infineon Technologies Ag Verfahren und Vorrichtung zum Testen von Setup-Zeit und Hold-Zeit von Signalen einer Schaltung mit getakteter Datenübertragung
CN1791943B (zh) * 2003-05-22 2011-08-17 Nxp股份有限公司 用于电阻开路缺陷的ram地址译码器的测试

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621739A (en) * 1996-05-07 1997-04-15 Intel Corporation Method and apparatus for buffer self-test and characterization
US5787092A (en) * 1997-05-27 1998-07-28 Hewlett-Packard Co. Test chip circuit for on-chip timing characterization
US5936977A (en) * 1997-09-17 1999-08-10 Cypress Semiconductor Corp. Scan path circuitry including a programmable delay circuit
US20020059543A1 (en) * 2000-11-13 2002-05-16 Wu-Tung Cheng Full-speed bist controller for testing embedded synchronous memories
US6829728B2 (en) * 2000-11-13 2004-12-07 Wu-Tung Cheng Full-speed BIST controller for testing embedded synchronous memories

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ATE396484T1 (de) 2008-06-15
EP1738375B1 (en) 2008-05-21
CN1934655B (zh) 2011-06-08
JP2007531191A (ja) 2007-11-01
EP1738375A1 (en) 2007-01-03
WO2005093761A1 (en) 2005-10-06
CN1934655A (zh) 2007-03-21
US20050216799A1 (en) 2005-09-29
DE602005007003D1 (de) 2008-07-03

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