US7494839B2 - Method for manufacturing a membrane sensor - Google Patents

Method for manufacturing a membrane sensor Download PDF

Info

Publication number
US7494839B2
US7494839B2 US11/011,888 US1188804A US7494839B2 US 7494839 B2 US7494839 B2 US 7494839B2 US 1188804 A US1188804 A US 1188804A US 7494839 B2 US7494839 B2 US 7494839B2
Authority
US
United States
Prior art keywords
region
epitaxy layer
doping
layer
stabilizing element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/011,888
Other languages
English (en)
Other versions
US20050181529A1 (en
Inventor
Hubert Benzel
Frank Schaefer
Simon Armbruster
Gerhard Lammel
Christoph Schelling
Joerg Brasas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102004036032A external-priority patent/DE102004036032A1/de
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Assigned to ROBERT BOSCH GMBH reassignment ROBERT BOSCH GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARMBRUSTER, SIMON, BENZEL, HUBERT, BRASAS, JOERG, LAMMEL, GERHARD, SCHELLING, CHRISTOPH, SCHAEFER, FRANK
Publication of US20050181529A1 publication Critical patent/US20050181529A1/en
Priority to US12/359,904 priority Critical patent/US7843025B2/en
Application granted granted Critical
Publication of US7494839B2 publication Critical patent/US7494839B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/00158—Diaphragms, membranes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0064—Constitution or structural means for improving or controlling the physical properties of a device
    • B81B3/0067—Mechanical properties
    • B81B3/007—For controlling stiffness, e.g. ribs
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0264—Pressure sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/01—Suspended structures, i.e. structures allowing a movement
    • B81B2203/0127—Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0315—Cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0111—Bulk micromachining
    • B81C2201/0115—Porous silicon
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0111—Bulk micromachining
    • B81C2201/0116—Thermal treatment for structural rearrangement of substrate atoms, e.g. for making buried cavities
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0135—Controlling etch progression
    • B81C2201/0136—Controlling etch progression by doping limited material regions

Definitions

  • the present invention relates to a method for manufacturing a semiconductor component.
  • Semiconductor elements, and membrane sensors, in particular, as well as methods for producing membrane sensors on the base of semiconductor substrates such as silicon wafers are already known.
  • flat porous membrane regions are arranged on the semiconductor substrate as substrate for sensor structures, and a cavity is produced underneath the membrane, e.g., for the thermal insulation of the membrane.
  • the membrane sensors currently on the market are mostly fashioned as thin film membrane sensors.
  • layer systems in thicknesses of between several 10 nm and several ⁇ m are deposited on a carrier substrate, and the carrier substrate is subsequently removed in predefined areas in order to obtain self-supporting membrane areas.
  • the structural elements of the sensor can then be arranged in the center of the membrane.
  • SMM Surface micromechanics
  • a sacrificial layer in which a sacrificial layer is generally used that is deposited on the front side of a carrier substrate before membrane deposition, is another possibility for exposing the membrane.
  • the sacrificial layer is later removed from the front side of the sensor through “detachment openings” in the membrane, whereby a self-supporting structure is created.
  • Published German patent document DE 100 32 579 discloses a method for manufacturing a semiconductor element and also a semiconductor element produced according to the method, in which, e.g., for a membrane sensor, a layer of semiconductor carrier material that was rendered porous is arranged above a cavity. Two layers having different porosities are formed to produce the cavity using appropriate etching parameters. Whereas the first layer has lower porosity and seals up during a subsequent first annealing step, the porosity of the second layer increases during the annealing step in such a way that a cavity is formed. In a second process step, at a higher annealing temperature, a relatively thick epitaxy layer as second membrane layer is grown on top of the first membrane layer formed from the first porous layer.
  • a thin epitaxy layer be grown during the first annealing step in order to ensure complete sealing of the porous first layer, which is used as starting layer for the epitaxy growth of the thick epitaxy layer.
  • a lower growth rate is selected at a lower temperature compared to the subsequent deposition of the thick epitaxy layer.
  • an SMM semiconductor element can be simplified considerably since no additionally deposited sacrificial layer is required and, furthermore, the membrane itself or an essential portion of the membrane is produced from semiconductor substrate material.
  • German patent document DE 101 38 759 provides a method for manufacturing a semiconductor element having a semiconductor substrate, in which the semiconductor substrate receives a different doping in the region of the porous membrane layer than the doping of the region of the subsequent cavity. After doping, the semiconductor material of the membrane layer is rendered porous, and the semiconductor material underneath the semiconductor material, rendered porous, is at least partially removed or relocated to provide a cavity.
  • German patent document DE 100 30 352 discloses a micromechanical component which has a support body made from silicon and a regionally self-supporting membrane which is joined to the support body.
  • the membrane is regionally and superficially provided with at least one stabilizing element for support.
  • the silicon is rendered porous in a first region and is selectively removed via an etch opening once the membrane layer has been deposited.
  • the present invention provides a manufacturing method for a micromechanical semiconductor element as well as a semiconductor component fabricated by this method.
  • a patterned stabilizing element having at least one opening be produced on a semiconductor substrate.
  • the opening is arranged such that it allows access to a first region in the semiconductor substrate, this first region having a first doping.
  • the semiconductor material having the first doping is to be dissolved out of the first region of the semiconductor substrate.
  • a membrane is produced above the first region.
  • at least a portion of the first region is used to produce a cavity underneath the stabilizing element.
  • the produced membrane advantageously has greater stability since, first of all, the stabilizing element supports the first epitaxy layer and, secondly, a uniform growing of the first epitaxy layer on the stabilizing element is possible without crystal faults.
  • the epitaxy conditions be selected such that the first epitaxy layer, starting from at least a portion of the stabilizing element, seals the at least one opening above the first region in a lateral and/or vertical direction.
  • the epitaxy conditions are advantageously chosen such that the epitaxial growth occurs only on the stabilizing element and not on the first region. One way of achieving this is by separate passivation of the first region.
  • the stabilizing element be largely covered.
  • the cavity of the semiconductor element may be produced in an additional method step by a thermally induced relocation process of the semiconductor material of the first region. It may be provided, in particular, that this relocation be implemented after the epitaxial growth of the first epitaxy layer and thus after production of the membrane.
  • the stabilizing element is built from the second epitaxy layer.
  • the second epitaxy layer is provided with openings in such a way that the doped semiconductor material of the first region is able to be removed through these openings.
  • One possibility for producing these openings is to expose the second epitaxy layer at least regionally to a light source and remove the areas of the second epitaxy layer exposed to light in this manner.
  • the removal of the light-exposed material of the second epitaxy layer and the selective removal of the semiconductor material provided with the first doping from the first region be implemented in the same method step.
  • the illuminated areas on the semiconductor substrate or on the second epitaxy layer are precisely not attacked during an etching process. As a result, the illuminated regions would remain standing in the form of webs, for instance above a first region rendered porous by etching.
  • the second epitaxy layer deposited on the surface of the semiconductor substrate may be patterned locally, for instance via an additionally applied passivation layer. It may be provided here that the second epitaxy layer patterned in this manner form a cohesive second region above the first region.
  • This second region may be embodied in the form of a lattice, for instance, and/or in the form of interconnected webs.
  • an SiC layer is epitaxially deposited on the semiconductor substrate and subsequently patterned. If this patterned SiC layer is not processed further, the first epitaxy layer is able to grow on the SiC layer in polycrystalline form in a further epitaxy step. In contrast, in a thermal treatment of the patterned SiC layer, it is possible for the second epitaxy layer to grow in a monocrystalline manner.
  • the stabilizing element advantageously has at least one web and/or lattice above the cavity.
  • the stabilizing element may also have an edging at the rim of the cavity.
  • the thickness of the stabilizing element vary.
  • the edging has a greater thickness compared to the lattice and/or the at least one web.
  • the manufacturing method according to the present invention provides the particular advantage that the rigidity of the membrane may be adjusted via the positioning of the openings on the stabilizing element, and/or that the webs may be designed by varying different manufacturing parameters.
  • the parameters during the epitaxial growth, the geometric arrangement of the openings and/or the lateral or vertical extensions of the webs may be considered manufacturing parameters. For instance, webs having a triangular cross section or having different vertical and/or lateral extensions are able to be produced.
  • the lattice or the at least one web in the surface area of the semiconductor substrate may be created by combining at least two implantation steps.
  • a second doping that is differentiable from the first doping of the first region may be produced in a second region of the semiconductor substrate.
  • this second region may then be further developed into the stabilizing element or into the lattice and/or a web. This may be done, for instance, in that only the semiconductor material is removed from of the first region during the following selective removal, but the material of the second region remains on or within the semiconductor substrate.
  • a third region which likewise has the first doping, is produced above the first region, having the first doping, in the semiconductor substrate.
  • the doping of the third region has a higher doping concentration than the doping of the first region.
  • the second epitaxy layer be produced with a second doping that is differentiable from the first doping.
  • the surface of the semiconductor substrate is patterned across at least a portion of the first region having the first doping. Afterwards, a second epitaxy layer having a second doping is produced on the surface of the patterned semiconductor substrate and likewise patterned. It is provided in this context that the patterned second epitaxy layer form the stabilizing element.
  • the semiconductor material is then selectively removed from the first region, and the first epitaxy layer is deposited on the first and second regions patterned in this manner.
  • the first and the second doping regions have different dopings.
  • the first region may have a p ⁇ doping
  • the second region, the edging or the lattice and/or the at least one web may have an n ⁇ doping.
  • An example embodiment of the present invention may provide that both the first epitaxy layer and the stabilizing element or the lattice or the at least one web have a monocrystalline form. However, it may additionally be provided that the first epitaxy layer and the stabilizing element have a polycrystalline design.
  • FIGS. 1 a - 1 d illustrate various stages of a conventional method for manufacturing a micromechanical membrane.
  • FIGS. 2 a - 2 b illustrate the various stages of an exemplary embodiment of the method of the present invention.
  • FIGS. 3 a - 3 b illustrate the steps of a treatment of the surface to prevent the deposition of epitaxy material according to the present invention.
  • FIGS. 4 a - 4 b illustrate the steps of an additional exemplary embodiment for the manufacture of a membrane according to the present invention.
  • FIGS. 5 a - 5 f illustrate various example embodiments of the webs on which the membrane is deposited according to the present invention.
  • FIGS. 6 a - 6 c show the steps of an example embodiment of a method for producing webs or lattices above a cavity.
  • FIGS. 7 a - 7 c show the steps of another example embodiment of a method for producing webs or lattices.
  • FIGS. 8 a - 8 b show the steps of another example embodiment of a method for producing webs or lattices.
  • FIGS. 9 a - 9 b show the steps of another example embodiment of a method for producing webs or lattices.
  • FIGS. 10 a - 10 c show the steps of another example embodiment of a method for producing webs or lattices.
  • FIGS. 11 a - 11 b and 12 a - 12 c show example embodiments of various lattice and hole geometries according to the present invention.
  • FIGS. 13 a - 13 g show various example embodiments of a method for producing a lattice having a desired cross-section profile.
  • FIGS. 14 a - 14 c show the steps of an example embodiment of a method for producing a lattice.
  • FIGS. 15 a - 15 d show the steps of an example embodiment of a method for producing a lattice and/or a membrane.
  • FIGS. 16 a - 16 c show the steps of an example embodiment of a method for producing a lattice and/or a membrane.
  • FIGS. 17 a - 17 d show the steps of an example embodiment of a method for producing a lattice and/or a membrane.
  • a conventional method for producing a membrane provides using a porous double layer in a semiconductor substrate 100 ,i.e., using a low-porosity layer 110 and a high-porosity layer 120 situated underneath it, it is possible to produce a starting layer 160 that is suitable for the growth of epitaxy layer 140 , as well as a cavity 150 (cf. FIG. 1 b ).
  • the transformation is accomplished by a first annealing step (at approximately 900 to 1000° C.), during which the semiconductor atoms of low-porosity layer 110 relocate in such a way that the surface seals.
  • cavity 150 is then able to be formed as well by relocation of the semiconductor atoms out of high-porosity layer 120 . This is accomplished in that the pores enlarge under the influence of the annealing step and finally unite to form a “giant pore,” which then constitutes the cavity.
  • An epitaxy layer 140 may then be deposited on starting layer 160 to produce the membrane, the epitaxy layer determining the characteristics of the membrane. However, there will be some pores that do not close in the production of such a membrane since the available silicon is insufficient. In some areas several small pores also unite to form a large pore so that pores having diameters of up to 0.5 ⁇ m are created.
  • the epitaxy layer which forms the later membrane, is unable to grow on these unsealed areas in the starting layer in a monocrystalline manner.
  • crystal faults form in the epitaxy layer (for instance due to stacking faults).
  • piezoresistive resistors for instance, which are required for the functioning of a pressure sensor, are produced on the upper surface of the membrane. Crystal faults in the epitaxy layer may degrade these resistors over the service life of the sensor and result in drift of the sensor signal.
  • a first thin epitaxy layer (thinner than 1 ⁇ m, preferably 200 to 600 ⁇ m), during which additional semiconductor material is offered for the complete sealing of the starting layer immediately at the outset, during or at the end of the first annealing process, may remedy this situation. It may be the same semiconductor material which is already present in layer 110 and/or is used in epitaxy layer 140 that is deposited. If semiconductor substrate 100 is made of silicon, for instance, such a method gives the offered silicon atoms sufficient time to arrange themselves according to the silicon crystal of the base. A lower temperature and a reduced growth speed compared to the subsequent, thick epitaxy layer are advantageously selected during the growing of the thin epitaxy layer. As an example, the temperature during the deposition of the thin epitaxy layer is approximately 900 to 1000° C., whereas the growth speed is selected to be less than 0.5 ⁇ m/min.
  • the substrate is exposed to a higher temperature (preferably 1100 to 1200° C.) so that a second, thick epitaxy layer 140 may then be grown there (a few ⁇ m).
  • a higher temperature preferably 1100 to 1200° C.
  • further annealing at the higher temperature may also be carried out in order to heal any possible crystal faults in the sealed starting layer.
  • the second epitaxy layer forms the actual membrane. This membrane may then be used for a pressure sensor, for instance or, following further patterning, for an acceleration sensor as well.
  • Depositing a single-crystalline, micromechanical membrane on a porous starting layer has various weak points, which may have a negative effect on the production or the service life of the membrane.
  • cracks may form in the porous starting layer, such cracks spreading to the epitaxy layer deposited thereon.
  • transitions may occur from the, for instance, p+ doped starting layer 160 to an edging of the starting layer.
  • the p+ doping is reduced to a p ⁇ doping (see 130 , FIG. 1 d ).
  • a lower p ⁇ doping also causes higher porosity. This effect is also utilized in the production of the double layer according to FIG.
  • low-porosity layer 110 has a p+ doping, for instance, and high-porosity layer 120 has a lower p ⁇ doping. Therefore, the low-porosity layer is joined to the edge via a high-porosity, and therefore fragile, region. Cracks, among others, may form here during the production.
  • first region 220 and a first portion of a second region 210 having different dopings are produced on a semiconductor substrate 200 , as shown in FIG. 2 a .
  • First region 220 may also have the substrate doping.
  • semiconductor substrate 200 has a p ⁇ doping
  • first and second portions 210 and 230 of the second region have an n ⁇ or n+ doping.
  • the first portion of the second region denoted by reference numeral 210 in FIG.
  • portion 230 and portion 210 of the first region have different dopings, such as n + or n.
  • first region 220 is etched to be rendered porous.
  • first region 220 may be both a portion of untreated semiconductor substrate 200 and an additionally doped region. The latter has the advantage of allowing a sharper delimitation in the production of porous region 220 .
  • first region 220 is etched to be rendered porous up to a depth of 5 to 20 ⁇ m, for instance, starting from the surface of semiconductor substrate 200 , second region 210 essentially will not be changed by the etching process.
  • first region 220 may be rendered porous by etching underneath second region 210 as well.
  • first region 220 have high porosity, e.g., having pore sizes of 1 nm up to several ⁇ m in diameter.
  • high porosity may be achieved by producing very many small pores ( ⁇ 5 nm) or a few very large pores (e.g., up to several 100 nm).
  • semiconductor substrate 200 is made of silicon, a (natural) oxide layer can be found on the surface of the untreated semiconductor substrate. For this reason, a reduction of the (natural) oxide layer on the silicon surface is obtained in a following process step by short annealing of the semiconductor substrate or the silicon substrate being carried out under a hydrogen atmosphere.
  • an “HF load” method or an HF GPE (gas phase etching) method with subsequent low-temperature epitaxy may be used to achieve the same effect.
  • FIG. 2 b shows the membrane after epitaxy layer 240 has been grown.
  • the highly porous silicon has relocated to form a large cavity 250 .
  • the form resulting from the overgrowth of the free regions between the webs can be seen on the underside of the membrane in FIG. 2 b . Further annealing allows this form to fuse in a planar manner.
  • the highly porous silicon between monocrystalline webs 210 is advantageous here since it prevents the growth of silicon inside the cavity region. If the cavity were completely free, depending on the growth conditions, silicon would be able to grow on the cavity walls from the beginning of the epitaxy growth. However, due to the initially porous surface between webs 210 , which relocates over course of the epitaxy process, it is prevented that silicon grows between webs 210 or that a significant portion of the epitaxy material enters cavity 250 .
  • an epitaxy layer having a cavity situated underneath it by means of a “pororization” as it is described in the present invention may also be carried out when other materials or semiconductor materials are used and is not restricted to the use of silicon. However, this requires that these other materials or semiconductor materials are also able to be rendered porous.
  • the region between and underneath the webs is not etched to be rendered porous, but is completely dissolved out. This may be accomplished by electropolishing, for instance, and the porosity is increased by varying the etching parameters (such as increasing the current, reducing the HF concentration), to such a degree that it reaches 100 percent.
  • the webs are now able to grow together, which entails the danger of silicon growing inside the cavity as well. To avoid this, the inside of the cavity may be protected by a layer that prevents silicon from growing there.
  • Such a protection is able to be achieved, for instance, by the application of a silicon nitride layer (SiN) 360 on the surface of second regions 310 , as shown in FIG. 3 a .
  • SiN silicon nitride layer
  • second regions 310 which are embodied in the form of webs and connected to each other and to framing 330 , may subsequently be exposed by removal of the first region (cf. cross section through the semiconductor substrate in FIG. 3 a ).
  • An oxide 370 is produced on the exposed regions of future cavity 350 via thermal oxidation, for instance.
  • nitride 360 is subsequently able to be selectively detached with respect to oxide 370 .
  • Such preparation allows a selective epitaxy to be achieved, i.e., the epitaxy material 340 (such as silicon) will grow only on the regions that are not protected by oxide 370 , thereby preventing silicon growth inside cavity 350 .
  • Another possibility for selectively preventing the growth of silicon is to apply a thin ( ⁇ 60 nm) silicon oxide layer (SiO) on those regions that are not to be electropolished prior to the application of silicon nitride layer (SiN) 360 .
  • a suitable etching process for instance by electropolishing, an oxide may be produced on the exposed regions via thermal oxidation, as in the already discussed example. However, it must be taken into account that this oxide has to be thicker than the oxide underneath the SiN overlay-mask.
  • the nitride may later be selectively removed with respect to the oxide.
  • a dry-etching process in which the oxide and the nitride have the same etching rates may be carried out as well. By suitable selection of the etching time it may be ensured that a sufficiently thick oxide layer remains on the cavity walls once the oxide that was situated underneath the SiN has been dissolved.
  • a selective epitaxy may then be carried out analogously to the above exemplary embodiment.
  • the semiconductor substrate is made of silicon
  • the silicon is rendered porous by etching between and underneath the webs. Afterwards a thin layer of oxide, which is a few nm thick, for example, will be produced on all silicon surfaces (i.e., wafer surface as well as on the surface of the pore walls).
  • This oxide prevents the relocation of the porous silicon during additional high-temperature steps as they are required in epitaxy or other kiln processes.
  • the oxide on the wafer surface may then be removed by means of a brief HF dip using diluted hydrofluoric acid (HF). Due to the surface tension the hydrofluoric acid does not penetrate the pores so that the oxide layer on the pore walls remains as before.
  • the membrane produced in this manner may be used, for instance, for a pressure sensor having piezoresistive resistors.
  • a circuit may be integrated adjacent to or on top of the membrane. If an access hole for the selective removal of the semiconductor material in the second region was produced on the backside, a backside sensor or differential-pressure sensor is obtained, which has a precisely defined membrane thickness compared to the related art. If an access hole is made from the front, this hole must be sealed again in a pressure-tight manner for the pressure-sensor application.
  • a step for smoothing the surface may generally be performed as an option.
  • One possible method for achieving the smoothing is chemical-mechanical polishing (CMP).
  • the membrane is patterned in the form of resonator structures.
  • the use of such structures makes is possible to realize acceleration sensors and/or yaw-rate sensors, for instance.
  • One possibility for stabilizing the webs before the epitaxy layer is grown is to optionally produce supports underneath the webs, which melt away during subsequent high-temperature steps (epitaxy or annealing steps (oxidation diffusion) for the production of integrated circuits) due to relocation of the silicon atoms.
  • regions 460 columns are produced if webs 410 are wider than half of the etching depth in first region 420 .
  • the isotropic undercut-type etching during anodization is then insufficient to anodize the silicon underneath the broadened webs 410 or to dissolve it out.
  • silicon relocates at high temperatures (>1000° C.).
  • the column (region 470 ) “melts” and the firm connection between substrate and membrane is interrupted. As a result, the membrane is able to move freely, as shown in FIG. 4 b.
  • the second region above the cavity may also be arranged in the form of a lattice, porous regions 510 and webs 500 alternating with each other.
  • FIGS. 5 a to 5 f various possible example embodiments are shown. However, the mentioned examples should not be considered as final, limiting illustrations. In this context, better resist adhesion is noticeable in FIGS. 5 e and 5 f , for example.
  • the webs or the lattice are/is not produced by local n ⁇ doping, but by local amorphization of the single-crystalline Si substrate.
  • the single-crystalline semiconductor substrate made of silicon 520 is bombarded with high-energy ions 540 such as argon ions. Due to this bombardment and the use of an implantation mask 530 , for instance made of SiO 2 , the single-crystalline structure is destroyed and regions 550 of amorphous silicon are created.
  • the amorphous Si 550 remaining behind will not be attacked in the following anodization in hydrofluoric acid, so that underneath amorphous regions 550 a region 560 of porous Si is produced ( FIG. 6 b ), which is able to relocate to form a cavity in a subsequent annealing process. In this way an amorphous Si lattice 550 is produced, which may be overgrown by an epitaxy process prior to or after this subsequent annealing operation.
  • epitaxial layer 590 ( FIG. 6 c ) does not become single-crystalline, but polycrystalline, in contrast to layer 570 growing on top of monocrystalline region 520 .
  • the transition between polycrystalline region 590 and monocrystalline region 570 is determined by the epitaxy parameters.
  • additional annealing may be carried out before the epitaxy layer is grown. Due to this annealing, the amorphous webs are able to recrystalize and relocate in the form of a single-crystalline lattice. This recrystallization step makes it possible to produce a monocrystalline Si epitaxy on the lattice webs.
  • the illumination selectivity of the anodization process may be utilized.
  • a p ⁇ doped silicon substrate 700 is illuminated during anodizing (using ions 710 or laser beam 735 ), so that regions 705 are produced, which counteract the anodizing process due to the charge carriers produced by the internal photo effect.
  • a suitable shadow mask 715 a diffraction pattern 720 or a holographic lattice ( FIG. 7 c )
  • a lattice-shaped region 705 of substrate 700 to be anodized may be illuminated and thereby protected from being rendered porous. Since the penetration depth of the light is limited as a function of the wavelength, the region protected in this manner is ultimately etched in an undercut manner.
  • the following epitaxy process or the production of the cavity may then be implemented in a manner that is analogous to the method already described.
  • a laser beam 735 as shown in FIG. 7 c may be guided onto a beam splitter 730 , the two partial beams being reflected at mirrors 740 and 745 and interacting with one another on the substrate surface in region 705 .
  • n ⁇ doped Si epitaxy layer 755 on a p ⁇ doped Si substrate 750 , as it is shown in FIG. 8 a .
  • n ⁇ doped Si epitaxy layer 755 is illuminated by means of suitable lighting 760 and a shadow mask 770 (made from metal, for instance).
  • the epitaxially produced n ⁇ Si is etched non-porous without illumination since no defect electrons are present.
  • the local illumination produced by means of mask 770 generates the required charge carriers in the n ⁇ doped region, so that the n ⁇ doped epitaxy layer is able to be rendered locally porous by etching in these areas 780 . If the etching procedure reaches the p ⁇ doted substrate 750 situated underneath, undercut-type etching is performed across the entire surface. Such undercut-type etching makes it possible to render substrate 750 porous by etching in region 765 since no illumination is required in the p ⁇ doped region. In addition to a shadow mask 770 , diffraction patterns and/or holographic lattices as shown in FIGS. 7 b and 7 c may be used as well to produce local illumination on the surface of epitaxy layer 755 .
  • n ⁇ doped Si epitaxy layer 805 is deposited on a p ⁇ doped Si substrate 800 as shown in FIG. 9 a , Si epitaxy layer 805 still being unpatterned at this stage.
  • an oxide mask 810 is deposited, which may be patterned by HF, for instance.
  • n ⁇ doped Si epitaxy layer 805 may then be patterned by means of trenches 815 via the trench mask produced in oxide 805 .
  • oxide 810 , n ⁇ doped epitaxy 805 and p ⁇ doped substrate 800 is then rendered porous by etching via anodization in HF, as shown in FIG. 9 b .
  • Oxide 810 and n ⁇ doped epitaxy layer 805 are not attacked in the process, whereas p ⁇ doped Si substrate 800 is rendered porous by etching.
  • oxide 810 Prior to the subsequent epitaxial deposition of the membrane, oxide 810 will be removed so that the membrane is able to grow on the n ⁇ doped lattice webs.
  • a lattice may be produced on porous silicon 845 in that an n ⁇ doped Si epitaxy layer 840 is selectively grown on a patterned SiO 2 or Si 3 N 4 mask 835 .
  • SiO 2 or Si 3 N 4 mask 835 has such a passivizing effect that single-crystalline silicon 840 is able to grow only on exposed Si substrate 830 , i.e., between oxide or nitride regions 835 , as illustrated in FIG. 10 b .
  • it is subsequently possible to produce a porous region 845 in substrate 830 which may be transformed into a cavity in a later annealing process.
  • An additional exemplary embodiment utilizes different porosities in the lattice and in the cavity region.
  • Such an adaptation of the porosities in the mentioned regions allows the relocation of the porous silicon into a cavity or the growth of the epitaxial silicon membrane in a more optimal manner. For instance, it may be provided that a higher or lower porosity be produced in the cavity region than in the region of the holes. In addition to a sharp separation of the different porosity regions, a porosity gradient is also conceivable.
  • the cavity layer forms a sufficiently stable basis, so that an excessively high porosity in the cavity layer would be disadvantageous.
  • By appropriate selection of a (high) porosity in the lattice area it may thus be prevented that the growth begins on the relocated silicon in the lattice holes. For if at least a portion of the epitaxial growth were to begin on the silicon between the lattice webs during the relocation, this might cause crystal faults, which would propagate in the membrane layer, for example as stack faults.
  • the lattice and hole geometries may be varied locally, as is shown in FIGS. 11 a and 11 b by way of example. Such a local variation may achieve an improved edge fixation of membrane 855 on substrate 850 . It is conceivable in this case that lattice holes 860 are omitted in a regular pattern, for instance at the membrane edge, as it is illustrated in FIG. 11 a . In this example, each second lattice hole at the outermost edge of the hole geometry is omitted, so that no lattice hole 860 may be found at location 865 , for instance. In addition, however, it may also be provided that the outermost hole row have a smaller diameter than the more inwardly lying holes.
  • the (hole) lattice may also be arranged across only a portion of the membrane region, so that a self-supporting membrane is produced as shown in FIG. 11 b .
  • Substrate 850 encloses the etching area, which in turn is covered by regions 875 having lattice holes 860 and regions 870 without lattice holes 860 .
  • the membrane may then be epitaxially deposited on regions 870 and 875 patterned in this manner.
  • the mechanical properties of the membrane such as the resonant frequency and/or the rigidity may also be varied by correspondingly adapted geometries of the lattice webs and holes.
  • One possibility for increasing the rigidity is to omit holes in the center of the membrane.
  • reliable undercut-type etching of the holes must be ensured. This requirement results in a limit for the maximum number of holes that may be omitted.
  • Piezoresistive resistors such as for a pressure sensor, for example, may be located in a region that stands out as a result of an especially defect-free epitaxy (avoidance of leakage currents and shunts via so-called diffusion pipes). This may be accomplished in that an especially low number of lattice holes, to be overgrown epitaxially, is present in these regions and/or that an especially adapted lattice and hole geometry is used, which becomes overgrown in a particular satisfactory manner.
  • FIG. 12 a shows the simultaneous use of two different rectangular geometries.
  • a second monocrystalline lattice 890 or 895 having broader or thicker webs is superposed on top of first monocrystalline lattice 885 having narrow webs and including porous regions 880 .
  • Such a combination may allow not only an additional local membrane reinforcement but also provides a stronger enclosure of the membrane in substrate 850 .
  • FIG. 12 b A schematic cross section through a membrane region having different lattice geometries is shown in FIG. 12 b . It can be seen clearly that webs 885 and 890 have different lateral extensions. The superpositioning of different geometries in the form of a lattice may also be achieved by different implantations. Variations of the web profiles of the lattice are likewise possible here as is illustrated by the cross section shown in FIG. 12 c . In this example two different webs 885 and 895 have been produced by different implantation energies and therefore different penetration depth.
  • implantation areas 905 e.g., n ⁇ doped regions in a p ⁇ doped substrate
  • Masks 910 of photoresist or Si oxide, which are irradiated by means of an implantation method 915 are used for the selective patterning of implantation regions 910 .
  • the energy or the particles used in implantation method 915 may be adapted to the substrate.
  • substrate 900 may be rendered porous around implantation areas 905 , thereby creating webs 920 in porous region 925 .
  • Suitable selection of the pattern of mask 910 (such as a gray-tone mask of photoresist or Si oxide) in conjunction with an appropriate implantation method 915 allows the lattice profile to be influenced in a variety of ways as is shown in FIGS. 13 c and 13 d .
  • the triangular cross-section form of implantation regions 905 illustrated in these figures has advantages with respect to the relocation of porous silicon and the subsequent epitaxy.
  • the holes seal faster as a result of the smaller hole diameter on the substrate surface.
  • the region that must be overgrown by the epitaxy is smaller, which leads to fewer crystal faults in the epitaxy layer forming the membrane.
  • FIGS. 13 e through 13 g One possible result of a twofold implantation with an increase in the implantation energy in the second implantation step ( FIG. 13 f ) is shown in FIGS. 13 e through 13 g .
  • FIG. 13 g a similar lattice profile results as that previously achieved in a masking of the substrate according to FIG. 13 c.
  • FIGS. 14 a and 14 b illustrate another possibility for producing a lattice on or within a region rendered porous by etching.
  • an SiC layer 960 is deposited via CVD (silane & propane) on a p ⁇ doped Si substrate 950 and patterned by means of an oxide mask 970 , for instance in a wet process (in KOH, KC10 3 or similar) or a dry process (for instance SF 6 ).
  • CVD silane & propane
  • oxide mask 970 for instance in a wet process (in KOH, KC10 3 or similar) or a dry process (for instance SF 6 ).
  • the p ⁇ doped silicon may be etched to be rendered porous by selective anodizing with respect to the SiC in region 980 .
  • the reason for this selective etching is that SiC with 2.4 eV (indirect) or 5.3 eV (direct) has a markedly greater band gap than Si.
  • SiC layer 960 may be removed from the surface of the semiconductor substrate down to lattice 965 and a frame 990 , which surround lattice 965 . Silicon may then be epitaxially deposited on semiconductor substrate 950 or lattice 965 to form a membrane.
  • a monocrystalline Si layer 955 is grown on the edge of semiconductor substrate 950 , and a polycrystalline Si layer 995 is grown on SiC 965 and 990 , as shown in FIG. 14 c .
  • the transition between monocrystalline region 955 and polycrystalline region 995 is determined by the epitaxy parameters. Angle 999 essentially depends on these parameters.
  • the porous region may be transformed into a cavity region via an annealing step prior to or following the epitaxy operation.
  • the lattice and membrane production may be accomplished via an additional p+ doping.
  • This additional p+ doping is able to broaden and improve on the method described in published German patent document DE 10 138 759, for instance.
  • a layer 1010 having an additional p+ doping is produced on a p ⁇ doped semiconductor substrate 1000 , such as an Si substrate, prior to semiconductor substrate 1000 and layer 1010 being covered by an n ⁇ doped epitaxy layer 1020 .
  • N ⁇ doped epitaxy layer 1020 may subsequently be patterned by means of an oxide mask 1030 , for instance via a trench process.
  • holes or trenches 1060 are created in epitaxy layer 1020 via which an anodization process may be implemented in order to produce a (nano)porous, p ⁇ doped layer 1040 in semiconductor substrate 1000 . Since p+ doped layer 1010 is less susceptible with respect to this anodizing process, a layer 1050 which has meso pores and is located above the layer having nano pores is produced in this region, layer 1050 having lower porosity than layer 1040 . In a subsequent annealing process, the material in nanoporous layer 1040 relocates into a cavity, whereas the material in the mesoporous layer 1050 relocates to form a sealed layer. The formation of the sealed layer facilitates both the sealing and the overgrowing of lattice holes 1060 during the following epitaxy and also improves the mechanical stability of the lattice during annealing prior to the epitaxy.
  • a further advantage of using an additional p+ doping results from a better adaptation of the anodization during the production of the lattice.
  • the p ⁇ doped substrate is etched beneath lattice 1070 in an undercut manner in the form of a beak 1080 , as illustrated in FIG. 15 c .
  • This beak may be reduced or prevented by additional p+ doping 1010 , so that a considerably rounder shape will be formed on the underside of lattice webs 1070 , as illustrated in FIG. 15 d.
  • n ⁇ doped layer 1110 is introduced in p ⁇ substrate 1100 by means of implantation or by coating or thin epitaxy.
  • P+ doped regions 1120 are then introduced in n ⁇ doped layer 1100 .
  • This introduction is advantageously implemented by an implantation process in which the p+ doping must be sufficiently strong to locally redope n ⁇ doped layer 1110 .
  • other methods that produce p+ doped regions 1120 within n ⁇ doped layer 1110 may be utilized as well.
  • the structure thus produced and illustrated in FIG. 16 b may be anodized in a following step, n ⁇ doped layer 1110 not being attacked and remaining on substrate 1100 in monocrystalline form.
  • local p+ doping 1140 is etched to be rendered porous.
  • both p+ doped regions 1140 and region 1130 are etched to be rendered porous as shown in FIG. 16 c , region 1130 being located in p ⁇ substrate 1100 underneath p+ doped region 1140 .
  • lattice webs of n ⁇ doped material are therefore obtained, between which p+ doped material is located, which is etched to be rendered porous.
  • a p ⁇ doped substrate 1200 may first be patterned by means of a first patterning.
  • This first patterning essentially defines the later membrane region.
  • the first patterning is advantageously selected such that it has half of the period of the later lattice constant, i.e., the clearance of holes 1210 with respect to each other.
  • An n ⁇ doped epitaxy layer 1220 is deposited on p ⁇ doped substrate 1200 patterned in this fashion. Naturally, it may also be provided that n ⁇ doped layer 1220 be produced directly within substrate 1200 by a diffusion process.
  • n ⁇ doped layer 1220 is subsequently removed by a physical etching step, so that the lattice constant is reduced as illustrated in FIG. 17 c by way of example. If the thickness of layer 1220 has been selected appropriately, the lattice constant is able to be halved as a result. Due to the lowering of the lattice constant, a considerably finer structure of the lattice webs or holes 1210 will be obtained on the surface of substrate 1200 , so that it is easier for holes 1210 to become overgrown.
  • An anodizing process follows, which once again does not attack the n ⁇ doping, but renders the p ⁇ doping of the substrate porous by etching, ultimately forming a region 1230 , which etches the n ⁇ doped lattice webs in an undercut manner ( FIG. 17 d ).
  • annealing and/or an epitaxy are/is implemented as final step in the production of the membrane. The annealing relocates the porous semiconductor material in region 1230 and seals the holes between the lattice webs.
  • the actual membrane is formed by the epitaxy.
  • n ⁇ doped lattice Due to the manner in which the n ⁇ doped lattice is produced in this exemplary embodiment, only geometries that form cohesive lattice webs after physical etching may be used, for instance a chessboard-type geometry (see, e.g., FIG. 5 e ) or a rod-shaped lattice (see, e.g., FIG. 5 f ).
  • Silicon is utilized as semiconductor material in the afore-described manufacturing method for producing a lattice above a porous layer. It should be noted, however, that materials or semiconductor materials other than silicon, which are able to be rendered porous by etching via an electrochemical method, for instance, may be used in the manufacturing method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Pressure Sensors (AREA)
US11/011,888 2003-12-16 2004-12-13 Method for manufacturing a membrane sensor Active 2025-06-21 US7494839B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/359,904 US7843025B2 (en) 2003-12-16 2009-01-26 Micromechanical semiconductor sensor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10358859 2003-12-16
DE10358859.0 2003-12-16
DE102004036032A DE102004036032A1 (de) 2003-12-16 2004-07-24 Verfahren zur Herstellung eines Halbleiterbauelements sowie ein Halbleiterbauelement, insbesondere ein Membransensor
DE102004036032.4 2004-07-24

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/359,904 Division US7843025B2 (en) 2003-12-16 2009-01-26 Micromechanical semiconductor sensor

Publications (2)

Publication Number Publication Date
US20050181529A1 US20050181529A1 (en) 2005-08-18
US7494839B2 true US7494839B2 (en) 2009-02-24

Family

ID=34839485

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/011,888 Active 2025-06-21 US7494839B2 (en) 2003-12-16 2004-12-13 Method for manufacturing a membrane sensor

Country Status (2)

Country Link
US (1) US7494839B2 (de)
EP (1) EP1544163B1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090170231A1 (en) * 2007-12-28 2009-07-02 Commissariat A L'energie Atomique Method of producing mechanical components of mems or nems structures made of monocrystalline silicon
DE102011006332A1 (de) * 2011-03-29 2012-10-04 Robert Bosch Gmbh Verfahren zum Erzeugen von monokristallinen Piezowiderständen
EP2599745A1 (de) 2011-11-30 2013-06-05 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Verfahren zum Herstellen eines MEMS Bauteil mit bewegliche Teile unterschiedlicher Dicke
US8716052B2 (en) 2011-11-30 2014-05-06 Commissariat à l'énergie atomique et aux énergies alternatives Method for making a structure comprising at least one multi-thick active part

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007053750A1 (en) * 2005-11-01 2007-05-10 Sensicore, Inc. Improved adhesion of membranes on nitride layer in electrochemical sensors by attachment to underlying oxide layer
WO2009114818A2 (en) * 2008-03-13 2009-09-17 University Of Utah Research Foundation Methods of forming an embedded cavity for sensors
IT202200008822A1 (it) 2022-05-02 2023-11-02 St Microelectronics Srl Struttura mems includente una cavita' sepolta con protuberanze antiadesione, e relativi procedimenti di fabbricazione

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766666A (en) * 1985-09-30 1988-08-30 Kabushiki Kaisha Toyota Chuo Kenkyusho Semiconductor pressure sensor and method of manufacturing the same
US5242863A (en) * 1990-06-02 1993-09-07 Xiang Zheng Tu Silicon diaphragm piezoresistive pressure sensor and fabrication method of the same
US5445991A (en) * 1993-12-24 1995-08-29 Kyungdook National University Sensor Technology Research Center Method for fabricating a semiconductor device using a porous silicon region
US5510276A (en) * 1992-12-28 1996-04-23 Commissariat A L'energie Atomique Process for producing a pressure transducer using silicon-on-insulator technology
DE10030352A1 (de) 2000-06-21 2002-01-10 Bosch Gmbh Robert Mikromechanisches Bauelement, insbesondere Sensorelement, mit einer stabilisierten Membran und Verfahren zur Herstellung eines derartigen Bauelements
DE10032579A1 (de) 2000-07-05 2002-01-24 Bosch Gmbh Robert Verfahren zur Herstellung eines Halbleiterbauelements sowie ein nach dem Verfahren hergestelltes Halbleiterbauelement
US6376291B1 (en) * 1999-04-29 2002-04-23 Stmicroelectronics S.R.L. Process for manufacturing buried channels and cavities in semiconductor material wafers
DE10138759A1 (de) 2001-08-07 2003-03-06 Bosch Gmbh Robert Verfahren zur Herstellung eines Halbleiterbauelements sowie Halbleiterbauelement, insbesondere Membransensor
US20030116813A1 (en) * 2000-11-03 2003-06-26 Hubert Benzel Micromechanical component and corresponing production method
US6743654B2 (en) * 2000-12-15 2004-06-01 Stmicroelectronics S.R.L. Method of fabricating pressure sensor monolithically integrated

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4766666A (en) * 1985-09-30 1988-08-30 Kabushiki Kaisha Toyota Chuo Kenkyusho Semiconductor pressure sensor and method of manufacturing the same
US5242863A (en) * 1990-06-02 1993-09-07 Xiang Zheng Tu Silicon diaphragm piezoresistive pressure sensor and fabrication method of the same
US5510276A (en) * 1992-12-28 1996-04-23 Commissariat A L'energie Atomique Process for producing a pressure transducer using silicon-on-insulator technology
US5445991A (en) * 1993-12-24 1995-08-29 Kyungdook National University Sensor Technology Research Center Method for fabricating a semiconductor device using a porous silicon region
US6376291B1 (en) * 1999-04-29 2002-04-23 Stmicroelectronics S.R.L. Process for manufacturing buried channels and cavities in semiconductor material wafers
DE10030352A1 (de) 2000-06-21 2002-01-10 Bosch Gmbh Robert Mikromechanisches Bauelement, insbesondere Sensorelement, mit einer stabilisierten Membran und Verfahren zur Herstellung eines derartigen Bauelements
DE10032579A1 (de) 2000-07-05 2002-01-24 Bosch Gmbh Robert Verfahren zur Herstellung eines Halbleiterbauelements sowie ein nach dem Verfahren hergestelltes Halbleiterbauelement
US20030116813A1 (en) * 2000-11-03 2003-06-26 Hubert Benzel Micromechanical component and corresponing production method
US6743654B2 (en) * 2000-12-15 2004-06-01 Stmicroelectronics S.R.L. Method of fabricating pressure sensor monolithically integrated
DE10138759A1 (de) 2001-08-07 2003-03-06 Bosch Gmbh Robert Verfahren zur Herstellung eines Halbleiterbauelements sowie Halbleiterbauelement, insbesondere Membransensor

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Low-pressure vapor-phase epitaxy of silicon on porous silicon," Material Letters 94 (1988), by L. Vescan et al.
Steiner, P. et al., "Mikrostrukturierung mit porösem Silizium," ("Microconstruction with Porous Silicium"), Mar. 1994, pp. 285-290, ITG-Fachberichte, VDE Verlag, Berlin, Germany.

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090170231A1 (en) * 2007-12-28 2009-07-02 Commissariat A L'energie Atomique Method of producing mechanical components of mems or nems structures made of monocrystalline silicon
US7932118B2 (en) * 2007-12-28 2011-04-26 Commissariat A L'energie Atomique Method of producing mechanical components of MEMS or NEMS structures made of monocrystalline silicon
DE102011006332A1 (de) * 2011-03-29 2012-10-04 Robert Bosch Gmbh Verfahren zum Erzeugen von monokristallinen Piezowiderständen
US8759136B2 (en) 2011-03-29 2014-06-24 Robert Bosch Gmbh Method for creating monocrystalline piezoresistors
EP2599745A1 (de) 2011-11-30 2013-06-05 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Verfahren zum Herstellen eines MEMS Bauteil mit bewegliche Teile unterschiedlicher Dicke
JP2013111745A (ja) * 2011-11-30 2013-06-10 Commissariat A L'energie Atomique & Aux Energies Alternatives 異なる厚さの領域を有する少なくとも１つの活性部を備える構造を製造する方法
US20130267049A1 (en) * 2011-11-30 2013-10-10 Commissariat A I'energie Atomique Et Aux Energies Alternatives Method for producing a structure comprising at least one active part having zones of different thicknesses
US8716052B2 (en) 2011-11-30 2014-05-06 Commissariat à l'énergie atomique et aux énergies alternatives Method for making a structure comprising at least one multi-thick active part
US8785330B2 (en) * 2011-11-30 2014-07-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for producing a structure comprising at least one active part having zones of different thicknesses

Also Published As

Publication number Publication date
US20050181529A1 (en) 2005-08-18
EP1544163B1 (de) 2021-02-24
EP1544163A3 (de) 2006-07-05
EP1544163A2 (de) 2005-06-22

Similar Documents

Publication Publication Date Title
US7843025B2 (en) Micromechanical semiconductor sensor
US7679154B2 (en) Method for manufacturing a semiconductor component and a semiconductor component, in particular a diaphragm sensor
US6342427B1 (en) Method for forming micro cavity
US7755152B2 (en) Semiconductor component configured as a diaphragm sensor
CN1657401B (zh) 微机械的半导体元件及其制造方法
US6677249B2 (en) Method for manufacturing breakaway layers for detaching deposited layer systems
US20020094435A1 (en) Micromechanical component, in particular a sensor element, having a stabilized membrane and a method of producing such a component
JP2004502555A (ja) 半導体構成素子の製造方法並びにその方法により製造された半導体構成素子
KR101116993B1 (ko) 집적 회로의 제조 방법
US7494839B2 (en) Method for manufacturing a membrane sensor
JP4327456B2 (ja) マイクロメカニックス構成素子及びその製造方法
JP2001351865A (ja) 半導体装置の製造方法
US6972447B2 (en) Semiconductor component having a first earlier structure differing from a second earlier structure
US7232631B2 (en) Mask for charged particle beam exposure, and method of forming the same
JP2012009576A (ja) 半導体装置の製造方法
JP3191960B2 (ja) Ｓｉ基体の加工方法
GB2333531A (en) Production of a monocrystalline layer
JPH0590113A (ja) Ｓｉ基体及びその加工方法
JPH0590243A (ja) Ｓｉ基体の加工方法
GB2415828A (en) Method for closing perforated membranes
JPS62182186A (ja) 単結晶薄膜の形成方法
JPS6281711A (ja) 堆積膜の選択形成方法
JPH0590114A (ja) Ｓｉ基体及びその加工方法
JPH0399421A (ja) Ｓｏｉ構造の形成方法
JPS61276341A (ja) 素子分離領域の形成方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: ROBERT BOSCH GMBH, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BENZEL, HUBERT;SCHAEFER, FRANK;ARMBRUSTER, SIMON;AND OTHERS;REEL/FRAME:016488/0029;SIGNING DATES FROM 20050131 TO 20050204

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12