US7483327B2 - Apparatus and method for adjusting an operating parameter of an integrated circuit - Google Patents

Apparatus and method for adjusting an operating parameter of an integrated circuit Download PDF

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US7483327B2
US7483327B2 US11/366,286 US36628606A US7483327B2 US 7483327 B2 US7483327 B2 US 7483327B2 US 36628606 A US36628606 A US 36628606A US 7483327 B2 US7483327 B2 US 7483327B2
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memory
speed
shift register
memory access
logic
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US20070220388A1 (en
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Qadeer A. Qureshi
James D. Burnett
Jack M. Higman
Thomas Jew
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Shenzhen Xinguodu Tech Co Ltd
NXP BV
NXP USA Inc
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Freescale Semiconductor Inc
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Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to PCT/US2007/061189 priority patent/WO2007117745A2/en
Priority to EP07756489.6A priority patent/EP1994420B1/en
Priority to JP2008557438A priority patent/JP4932856B2/ja
Priority to KR1020087024174A priority patent/KR101367063B1/ko
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Priority to TW096105319A priority patent/TWI459403B/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates generally to integrated circuits, and more particularly, to an apparatus and method for adjusting an operating parameter of an integrated circuit.
  • an integrated circuit it is desirable for an integrated circuit to operate with the lowest possible power consumption.
  • One way to reduce power consumption is to lower the power supply voltage to the integrated circuit.
  • lowering the power supply voltage reduces the switching speed of the transistors of the integrated circuit.
  • the rate of change in access time of memory circuits may be different than the rate of change in switching speed of logic circuits.
  • FIG. 1 illustrates, in block diagram form, an integrated circuit in accordance with an embodiment of the present invention.
  • FIG. 2 illustrates, in block diagram form, a portion of the integrated circuit of FIG. 1 .
  • FIG. 3 illustrates several comparison results for the compare logic of FIG. 2 .
  • FIG. 4 illustrates a method for changing an operating parameter of the integrated circuit of FIG. 1 .
  • bus is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status.
  • the conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa.
  • the plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.
  • the present invention provides an apparatus and method for adjusting an operating parameter of an integrated circuit having both a logic circuit and a memory.
  • the operating parameter to be adjusted is the power supply voltage to a memory on the integrated circuit.
  • the operating parameter may be a clock frequency of the integrated circuit or an element of the integrated circuit environment, such as for example, temperature.
  • the apparatus includes a ring oscillator, a shift register and compare logic.
  • the ring oscillator provides a clock signal that is dependent on the ring oscillator's power supply voltage, temperature, and process.
  • the clock signal is used to clock a shift register.
  • the shift register begins a shifting operation in response to a read access to the memory. The shifting operation is terminated in response to completing the read access.
  • the number of shifting operations is then compared to a predetermined value, where the predetermined value represents a desired operating speed of the memory. If the number of shifting operations is greater than the predetermined value, then the memory is slower than desired, and if the number of shifting operations is less than the predetermined value, then the memory is faster than desired.
  • the power supply voltage can be adjusted to change the operating speed of the memory based on the comparison. In the illustrated embodiment, the speed of the memory is determined using a dummy path representing the worst case access time for the memory.
  • the disclosed embodiment provides a way to track the difference between logic performance and memory performance against changes in process, temperature, and voltage dynamically, in real time.
  • the power supply voltages for the integrated circuit can then be adjusted for optimal performance of both the memory and the logic circuits.
  • FIG. 1 illustrates, in block diagram form, an integrated circuit 10 in accordance with an embodiment of the present invention.
  • the integrated circuit 10 includes logic circuits 12 and a memory 14 .
  • the logic circuits 12 may include any type of digital circuit, such as for example, a data processor, an ASIC (application specific integrated circuit), or the like.
  • the integrated circuit 10 can be characterized as being a data processing system having an embedded memory.
  • the memory 14 is coupled to the logic circuit 14 via a bus 16 and can be any kind of volatile or non-volatile memory.
  • memory 14 is a static random access memory (SRAM).
  • memory 14 may be a dynamic random access memory (DRAM), a magneto-resistive random access memory (MRAM), ferro-electric random access memory (FeRAM), flash, electrically erasable programmable read only memory (EEPROM), and the like.
  • the logic circuits 12 may be coupled directly to the memory 14 instead of via the bus 16 .
  • the integrated circuit 10 may be a stand-alone memory where the logic circuits 12 are the peripheral circuitry for accessing the memory.
  • the logic circuits 12 are coupled to a power supply voltage terminal labeled “VDD 1 ” and the memory 14 is coupled to a power supply voltage terminal labeled “VDD 2 ”.
  • VDD 1 and VDD 2 receive positive power supply voltages with respect to ground and are supplied separately.
  • power supply voltage VDD 1 may, or may not, be equal to VDD 2 .
  • the illustrated embodiment shows two independent power supply voltages. In other embodiments, there may be more than two power supply voltages. Also, in other embodiments, there may be only one power supply voltage. In addition, the power supply voltages may be negative with respect to ground in other embodiments.
  • FIG. 2 illustrates, in block diagram form, a portion of the integrated circuit 10 of FIG. 1 .
  • FIG. 2 includes the memory 14 , a ring oscillator 20 , a shift register 22 , a register 24 , a compare logic circuit 26 , and a control circuit 28 .
  • the memory 14 includes a memory array 30 , a row decoder 34 , and column logic 36 .
  • the memory array 30 is a conventional SRAM array and includes a plurality of SRAM cells coupled to bit line pairs and to word lines.
  • the memory array 14 may also have the memory cells organized into multiple blocks of memory cells (not shown).
  • the memory array 30 includes a “dummy path” for duplicating a worst case critical timing path for a memory access.
  • a dummy path may be implemented as part of the memory or as a separate circuit having elements for copying each of the delays in the memory.
  • the dummy path is also implemented to track any changes in process and/or temperature in the same way as the memory 14 .
  • the dummy path is represented by a dummy memory cell 32 coupled to a dummy word line (DWL) and to a dummy bit line pair (DBL/DBL*).
  • DWL dummy word line
  • DBL/DBL* dummy bit line pair
  • the asterisk (*) is used to represent that the dummy bit line DBL* is the logical complement of the dummy bit line DBL.
  • the dummy bit lines, dummy word lines, and the dummy memory cell are identical to the actual bit lines, word lines and memory cells of memory array 30 .
  • the memory 14 has an input for receiving a clock signal labeled “CLK”, an input for receiving a plurality of address signals labeled “ROW ADDRESS” and “COLUMN ADDRESS”, an input for receiving a memory enable signal labeled “MEM EN”, and an input for receiving a read/write signal labeled “R/W”.
  • the column logic 36 receives the signals COLUMN ADDRESS and includes column decoders and sense amplifiers for sensing and amplifying the relatively small bit line voltages.
  • the memory array 30 is coupled to the power supply voltage terminal VDD 2 and to a power supply voltage terminal labeled “VSS”.
  • VDD 2 is for receiving a power supply voltage of about 1.2 volts and VSS is coupled to ground.
  • a plurality of bidirectional terminals is used for transmitting data signals DATA to and from the memory 14 .
  • the memory 14 operates as a conventional embedded RAM.
  • the memory enable signal MEM EN is asserted to start an access to memory 14 .
  • the read/write signal R/W determines whether the access is a read access or a write access.
  • a row address is provided to select a word line and a column address is provided to select a bit line pair. Note that in some embodiments, there may be only a single bit line coupled to a column of memory cells instead of a pair.
  • a memory cell coupled to the selected word line and bit line pair is accessed for a read or write operation depending on the state of read/write signal R/W. In the case of a write cycle, a data bit is transmitted to the bit line pair via the column logic 36 and stored in the memory cell.
  • a data bit is provided by the memory cell to the selected bit line pair and output from the memory via the column logic 36 as data signals DATA.
  • the data signals DATA may be provided to, for example, the bus 16 of FIG. 1 for use by logic circuits 12 .
  • a data processor may provide the control, data, and address signals that are provided to the memory 14 .
  • Ring oscillator 20 is a conventional ring oscillator having a plurality of inverters coupled in a feedback path and is coupled to a power supply voltage terminal labeled “VDD 1 ” and to a power supply voltage terminal labeled “VSS”.
  • the ring oscillator 20 provides a clock signal labeled “SHIFT CLK” that varies in response to changes in power supply voltage, process, and temperature.
  • the clock signal is provided to a clock input of the shift register 22 .
  • the ring oscillator 20 tracks process, temperature, and power supply variations in the same manner as the logic circuits 12 , and the power supply voltage provided to ring oscillator 20 is the same as the power supply voltage provided to logic circuits 12 .
  • the power supply voltage provided to VDD 1 may be the same as the voltage provided to VDD 2 or may be different.
  • the shift register 22 is a conventional shift register having a plurality of stages coupled together in series. The number of stages is dependent upon the number of inverters in the ring oscillator 20 and the speed of the logic circuits 12 and memory 14 .
  • the shift register 22 is enabled by a control signal labeled “SR EN” from the control circuit 28 .
  • the control circuit 28 receives the memory enable signal MEM EN, the read/write signal R/W, and a signal representing the operating state of the memory labeled “MEM BUSY”.
  • the control signal SR EN enables the shift register 22 to begin a shifting operation in response to the start of a read access of the memory 14 .
  • the shift register 22 shifts, for example, a logic one from an input stage toward the output stage in response to the clock signal SHIFT CLK.
  • the control signal SR EN causes the shift register 22 to end a shifting operation.
  • the number of stages that contain a logic one is compared against a predetermined value, or threshold, stored in the register 24 .
  • the compare logic 26 has an input for receiving the output from the shift register 22 labeled “SR OUTPUT” and an input for receiving the predetermined value labeled “TH” from the register 24 .
  • the value TH represents the desired operating speed of the memory.
  • the compare logic 26 compares the value SR OUTPUT to the value TH and provides one of a memory slow signal labeled “MEM SLOW” and a memory fast signal labeled “MEM FAST”.
  • the MEM SLOW signal indicates that the memory is slower than the desired operating speed of the memory.
  • the operating speed of the memory may be increased by, for example, increasing the power supply voltage to the power supply voltage terminal VDD 2 to the memory.
  • the MEM FAST signal indicates that the memory is operating faster than the desired operating speed of the memory. If the MEM FAST signal is provided, the power supply voltage provided to VDD 2 may be decreased to conserve power consumption of the integrated circuit 10 .
  • the desired operating speed of the memory 14 is relative to the speed of the logic circuits 12 as determined by the speed of the ring oscillator 20 . Note that in other embodiments, there may be more than one predetermined threshold voltage TH to compare against the signal SR OUTPUT.
  • the shift register 22 is cleared upon completion of the comparison step. Also, the shift register 22 may be cleared when and if the integrated circuit 10 is cleared. For the purposes of clarity and simplicity, the means for resetting or clearing the shift register 22 is not shown but is well known in the art. Also, in other embodiments, the shift register 22 may be replaced with a counter that outputs a count value to compare with the threshold TH.
  • FIG. 3 illustrates several possible comparison results for the compare logic of FIG. 2 .
  • shift register 22 is shown having 8 bits for illustration purposes. In an actual embodiment, shifter register 22 may have, for example, 32 or 64 bits. The mid point of the shift register 22 is marked with “TH”, indicating the bit position for the desired memory operating speed in the illustrated embodiment. In other embodiments, the desired memory operating speed may coincide with another bit position of shift register 22 .
  • a logic one is shifted into the left side of shift register 22 in response to a memory read operation being started as indicated by control signal SR EN being asserted.
  • the logic one has been shifted to the fourth bit position. Because the SR output is equal to value TH, the output signal MEM SLOW is zero and the output signal MEM FAST is zero, indicating that the memory is operating at the desired speed and therefore the power supply voltage VDD 2 provided to the memory 14 is optimal.
  • a logic one is shifted into the left side of shift register 22 in response to a memory read operation being started as indicated by control signal SR EN being asserted. At the end of the read operation, the logic one has been shifted to the second bit position.
  • the SR OUTPUT is less than the value TH, indicating that the memory is faster than desired.
  • the compare logic 26 outputs a logic zero MEM SLOW and a logic one MEM FAST.
  • a system that includes memory 14 may cause an interrupt to be generated and the power supply voltage to memory 14 to be lowered by a predetermined amount. On the next memory read access, the speed will be checked again and another incremental adjustment to VDD 2 will be made if necessary.
  • An example 39 illustrates a case where the SR OUTPUT is higher than the value TH.
  • the logic one has been shifted to the sixth bit position.
  • the compare logic 26 will output a logic one MEM SLOW and a logic zero MEM FAST.
  • An interrupt may be generated in the integrated circuit 10 and the power supply voltage VDD 2 adjusted higher to increase the speed of the memory operations. On the next and subsequent read operations, the speed will be checked and other adjustments made to the power supply voltage VDD 2 if necessary.
  • FIG. 4 illustrates a method for changing an operating parameter of the integrated circuit of FIG. 1 .
  • the operating parameter is the power supply voltage to the memory.
  • the operating parameter may be another user-controlled or environment variable for the memory.
  • a “user” can be a human operator or another portion of a system that includes integrated circuit 10 .
  • an access to the memory is begun and a worst case critical path for the access is timed using the dummy path in the memory.
  • a portion of the dummy path includes the dummy word line DWL and the dummy bit line pair DBL/DBL* as illustrated in FIG. 2 .
  • the shift register 22 is enabled in response to the read access by an asserted control signal SR EN.
  • the end of the read access is detected by the control logic 28 receiving a deasserted MEM BUSY signal.
  • the control signal SR EN is deasserted causing the shift register 22 to stop shifting.
  • the shift register output SR OUTPUT is provided as an input to the compare logic 26 .
  • the state of the shift register 22 is compared with a value representing the desired operating speed of the memory. The state of shift register 22 is determined by how many stages across the shift register a bit is shifted as discussed above in reference to FIG.
  • the shift register 22 is cleared by a reset signal (not shown) as discussed above. If the number of shifted bits is greater than the threshold TH, then the memory is slower than desired. If the number of shifted bits is less than the threshold TH, the memory is faster than desired.
  • an operating parameter of the memory is changed in response to the comparison of step 46 . In the case where the number of shifted bits is less than the threshold TH, the power supply voltage VDD 2 may be reduced to slow down the memory and conserve power. In the case where the number of shifted bits is greater than the threshold TH, the power supply voltage VDD 2 is raised to increase the speed of the memory.
  • the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

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US11/366,286 2006-03-02 2006-03-02 Apparatus and method for adjusting an operating parameter of an integrated circuit Active 2027-06-13 US7483327B2 (en)

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Application Number Priority Date Filing Date Title
US11/366,286 US7483327B2 (en) 2006-03-02 2006-03-02 Apparatus and method for adjusting an operating parameter of an integrated circuit
PCT/US2007/061189 WO2007117745A2 (en) 2006-03-02 2007-01-29 Apparatus and method for adjusting an operating parameter of an integrated circuit
EP07756489.6A EP1994420B1 (en) 2006-03-02 2007-01-29 Apparatus and method for adjusting an operating parameter of an integrated circuit
JP2008557438A JP4932856B2 (ja) 2006-03-02 2007-01-29 集積回路の動作パラメータを調整するための装置及び方法
KR1020087024174A KR101367063B1 (ko) 2006-03-02 2007-01-29 집적 회로의 동작 파라미터를 조정하기 위한 장치 및 방법
TW096105319A TWI459403B (zh) 2006-03-02 2007-02-13 調整積體電路之操作參數之方法及裝置

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Cited By (8)

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US20080028175A1 (en) * 2006-07-26 2008-01-31 Gerald Keith Bartley Self Timed Memory Chip Having an Apportionable Data Bus
US20090185435A1 (en) * 2008-01-17 2009-07-23 Chad Allen Adams Method and Circuit for Implementing Enhanced SRAM Write and Read Performance Ring Oscillator
US20140036608A1 (en) * 2012-07-31 2014-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Tracking signals in memory write or read operation
US8811069B2 (en) 2011-08-22 2014-08-19 Samsung Electronics Co., Ltd. Memory device and systems including the same
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