US7376003B2 - Magnetic random access memory - Google Patents

Magnetic random access memory Download PDF

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US7376003B2
US7376003B2 US10/465,616 US46561603A US7376003B2 US 7376003 B2 US7376003 B2 US 7376003B2 US 46561603 A US46561603 A US 46561603A US 7376003 B2 US7376003 B2 US 7376003B2
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write
current
bit line
data
magnetic field
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US20040042297A1 (en
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Yoshihisa Iwata
Yoshiaki Asao
Kentaro Nakajima
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Toshiba Corp
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Toshiba Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

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  • the present invention relates to a magnetic random access memory (MRAM) which constitutes a memory cell using a MTJ (Magnetic Tunnel Junction) element which stores “1”- and “0”-information using a tunneling magnetoresistive effect.
  • MRAM magnetic random access memory
  • TMR tunneling magneto-resistive
  • a magnetic random access memory stores “1”- and “0”-information using MTJ elements.
  • a MTJ element has a structure in which an insulating layer (tunneling barrier) is sandwiched between two magnetic layers (ferromagnetic layers), as shown in FIG. 41 .
  • Information to be stored in the MTJ element is determined on the basis of whether the magnetizing directions of the two magnetic layers are parallel or antiparallel.
  • parallel means that the two magnetic layers have the same magnetizing direction.
  • Antiparallel means that the two magnetic layers have opposite magnetizing directions (the arrows indicate the magnetizing directions).
  • an antiferromagnetic layer is arranged on the side of one of the two magnetic layers.
  • the antiferromagnetic layer serves as a member which fixes the magnetizing direction of one magnetic layer and changes only the magnetizing direction of the other magnetic layer, thereby easily rewriting information.
  • the magnetic layer whose magnetizing direction is fixed is called a fixed layer or pinning layer.
  • the magnetic layer whose magnetizing direction can freely be changed is called a free layer or storing layer.
  • MTJ elements are arranged at the intersections between write word lines and write bit lines which cross each other.
  • a write is done by supplying a current to each of a write word line and a write bit line and setting the magnetizing direction of a MTJ element in the parallel or antiparallel state using a magnetic field generated by the currents flowing through the two lines.
  • the easy-axis (axis of easy magnetization or easy magnetization axis) of an MTJ element corresponds to the X-direction
  • a write word line runs in the X-direction
  • a write bit line runs in the Y-direction perpendicular to the X-direction.
  • a current that flows in one direction is supplied to the write word line
  • a current that flows in one or the other direction is supplied to the write bit line in accordance with write data.
  • the magnetizing direction of the MTJ element When a current that flows in one direction is supplied to the write bit line, the magnetizing direction of the MTJ element is set in the parallel state (“1”-state). On the other hand, when a current that flows in the other direction is supplied to the write bit line, the magnetizing direction of the MTJ element is set in the antiparallel state (“0”-state).
  • the magnetizing direction of the MTJ element changes in accordance with the following mechanism.
  • the resistance value of the MTJ element changes by, e.g., about 17%.
  • the change ratio i.e., the ratio of the resistance difference between the anti-parallel state and the parallel state and the resistance of the parallel state is called “MR ratio”.
  • the MR ratio changes depending on the structure, composition and morphology of the MTJ element. Currently, even a MTJ element with an MR ratio of about 50% is available.
  • the synthesized magnetic field of the magnetic field Hy in the easy-axis direction and a magnetic field Hx in the hard-axis (axis of hard magnetization or hard magnetization axis) direction is applied to the MTJ element.
  • the intensity of the magnetic field Hy in the easy-axis direction which is necessary for changing the resistance value of the MTJ element, changes depending on the intensity of the magnetic field Hx in the hard-axis direction.
  • a MTJ element has an asteroid curve indicated by, e.g., the solid line in FIG. 45 .
  • the direction of the magnetic field Hx in the write mode is constant.
  • Write data is determined by the direction of the magnetic field Hy.
  • the magnetizing direction of the free layer of the MTJ element can be reversed (downward ⁇ upward).
  • the data write for the MTJ element can be controlled.
  • a read can easily be performed by supplying a current to a selected MTJ element and detecting the resistance value of the MTJ element.
  • switch elements are connected in series to the MTJ elements. Only the switch element connected to a selected read word line is turned on to form a current path. Consequently, a current flows to only the selected MTJ element. Hence, data of the MTJ element can be read.
  • the data write is executed by, e.g., supplying write currents to a write word line and a write bit line and causing a thus generated synthesized magnetic field to act on a MTJ element.
  • the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed by a predetermined synthesized magnetic field necessary for magnetization inversion independently of the reversing direction (upward or downward).
  • chips, memory cell arrays, word lines/bit lines, or MTJ elements have different MTJ element asteroid curves (asymmetrical shapes with respect to the X- and Y-axes), as shown in, e.g., FIGS. 46 to 49 .
  • the intensity of the synthesized magnetic field Hx+Hy may sometimes not be able to reach outside the asteroid curve depending on the magnetization reversing direction, and the magnetizing direction of the MTJ element cannot be reversed.
  • the asteroid curve of the MTJ element becomes asymmetrical with respect to the X- and Y-axes because of various variations in the manufacturing process. Detailed examples are as follows.
  • the shape of a MTJ element determines the magnitude of a magnetic domain or the intensity of an antimagnetic field (a magnetic field which is generated in a magnetic material and has a direction reverse to the external magnetic field). For this reason, that the MTJ elements have different shapes means that they have different magnetic domain magnitudes or antimagnetic field intensities. That is, the magnetic field intensity necessary for reversing the magnetizing direction of the MTJ element changes between the MTJ elements. Hence, the asteroid curve of the MTJ element becomes asymmetrical with respect to the X- and Y-axes.
  • the magnetic field intensity necessary for reversing the magnetizing direction also increases. That is, a variation in magnetic layer thickness between MTJ elements makes the asteroid curve of a MTJ element asymmetrical with respect to the X- and Y-axes.
  • an alloy made of iron group elements Fe, Ni, Co, and the like
  • an alloy can have a variation in composition.
  • an alloy that forms the free layer of each MTJ element has a variation in composition, saturation magnetization changes between the MTJ elements.
  • an alloy that forms the free layer of each MTJ element generally has a polycrystalline structure.
  • the magnetic anisotropy of the crystal axis increases, it becomes very difficult to make the asteroid curves of all MTJ elements symmetrical with respect to the X- and Y-axes.
  • the write operation may be impossible when the positional relationship between a write line and a MTJ element shifts. That is, even when a necessary synthesized magnetic field is applied to the MTJ element, the magnetizing direction of the free layer of the MTJ element may not reverse.
  • the write operation may be impossible when the positional relationship between the write line and the MTJ element shifts due to mask misalignment at the time of manufacturing.
  • some MTJ elements have asteroid curves asymmetrical with respect to the X- and Y-axes because of a variation in shape between the MTJ elements or a variation in thickness/composition between the MTJ elements at the time of manufacturing. Even when the asteroid curve is symmetrical with respect to the X- and Y-axes, the write operation may be impossible when the positional relationship between the write line and the MTJ element shifts. Such phenomena often occur at the early stage of development of magnetic random access memories.
  • a writing method of a magnetic random access memory comprises a series of steps of testing write characteristics of a magnetoresistive element having a hard-axis and an easy-axis, independently determining a value of a first write current which generates a magnetic field in the hard-axis direction and a value of a second write current which generates a magnetic field in the easy-axis direction on the basis of the write characteristics, which is necessary for magnetization inversion of the magnetoresistive element, programming the values of the first and second write currents as setting data, and generating the first and second write currents on the basis of the setting data to write data in the magnetoresistive element.
  • a magnetic random access memory comprises first and second write lines which cross each other, a magnetoresistive element which is arranged at an intersection between the first and second write lines, a first driver which supplies a first write current to the first write line, a second driver which supplies a second write current to the second write line, and a setting circuit in which first setting data to control a current waveform of the first write current and second setting data to control a current waveform of the second write current are registered.
  • FIG. 1 is a view showing Example 1 of Write Principle 1 according to the present invention
  • FIG. 2 is a view showing Example 2 of Write Principle 1 according to the present invention.
  • FIG. 3 is a view showing Example 3 of Write Principle 1 according to the present invention.
  • FIG. 4 is a view showing Example 4 of Write Principle 1 according to the present invention.
  • FIG. 5 is a view showing Example 1 of Write Principle 2 according to the present invention.
  • FIG. 6 is a view showing Example 2 of Write Principle 2 according to the present invention.
  • FIG. 7 is a view showing Example 3 of Write Principle 2 according to the present invention.
  • FIG. 8 is a view showing Example 4 of Write Principle 2 according to the present invention.
  • FIG. 9 is a view showing Example 1 of Write Principle 3 according to the present invention.
  • FIG. 10 is a view showing Example 2 of Write Principle 3 according to the present invention.
  • FIG. 11 is a view showing Example 1 of Write Principle 4 according to the present invention.
  • FIG. 12 is a view showing Example 2 of Write Principle 4 according to the present invention.
  • FIG. 13 is a flow chart showing write method I according to the present invention.
  • FIG. 14 is a flow chart showing write method II according to the present invention.
  • FIG. 15 is a flow chart showing write method III according to the present invention.
  • FIG. 16 is a view showing the overall arrangement of an MRAM according to an embodiment of the present invention.
  • FIG. 17 is a view showing an example of a write word line driver/sinker
  • FIG. 18 is a view showing an example of a write bit line driver/sinker
  • FIG. 19 is a view showing an example of a write current waveform control circuit
  • FIG. 20 is a view showing an example of a setting circuit
  • FIG. 21 is a view showing an example of a register in the setting circuit
  • FIG. 22 is a view showing another example of the register in the setting circuit.
  • FIG. 23 is a view showing an example of a Vclamp generation circuit
  • FIG. 24 is a view showing an example of a decoder in the setting circuit
  • FIG. 25 is a waveform chart showing an example of the current waveform of a write word line current
  • FIG. 26 is a waveform chart showing an example of the current waveform of a write bit line current
  • FIG. 27 is a view showing the overall arrangement of an MRAM according to another example of the present invention.
  • FIG. 28 is a view showing an example of a write word line driver/sinker
  • FIG. 29 is a view showing an example of a write bit line driver/sinker
  • FIG. 30 is a view showing an example of a write current waveform control circuit/setting circuit
  • FIG. 31 is a view showing another example of a write current waveform control circuit/setting circuit
  • FIG. 32 is a view showing still another example of a write current waveform control circuit/setting circuit
  • FIG. 33 is a view showing an example of a write word line driver/sinker trigger circuit
  • FIG. 34 is a view showing an example of a write bit line driver/sinker trigger circuit
  • FIG. 35 is a view showing another example of the write bit line driver/sinker trigger circuit
  • FIG. 36 is a view showing an example of the setting circuit
  • FIG. 37 is a view showing another example of the setting circuit
  • FIG. 38 is a view showing still another example of the setting circuit
  • FIG. 39 is a perspective view showing Example 1 in which the circuit scheme according to the present invention is applied to an MRAM having memory cell arrays stacked in a plurality of stages;
  • FIG. 40 is a perspective view showing Example 2 in which the circuit scheme according to the present invention is applied to an MRAM having memory cell arrays stacked in a plurality of stages;
  • FIG. 41 is a view showing a structural example of a MTJ element
  • FIG. 42 is a view showing two states of the MTJ element
  • FIG. 43 is a view showing the write operation principle of a magnetic random access memory
  • FIG. 44 is a view showing a TMR curve
  • FIG. 45 is a view showing an asteroid curve
  • FIG. 46 is a view showing an example of the pattern of the shift of the asteroid curve
  • FIG. 47 is a view showing another example of the pattern of the shift of the asteroid curve.
  • FIG. 48 is a view showing still another example of the pattern of the shift of the asteroid curve.
  • FIG. 49 is a view showing still another example of the pattern of the shift of the asteroid curve.
  • the write principle for the magnetic random access memory i.e., a method of applying magnetic fields Hx and Hy to a MTJ element (MTJ) will be described first.
  • the pattern of the shift (asymmetry with respect to the X- or Y-axis) of the asteroid curve of a MTJ element is recognized. Then, the magnitude of a write current to be supplied to a write word/bit line (i.e., the intensities of the magnetic fields Hx and Hy) is determined in accordance with the pattern of shift of the asteroid curve (write characteristics).
  • the write principle of this example is based on the premise that the asteroid curve of a MTJ element shifts in the hard-axis direction.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • ideal asteroid curve means an asteroid curve having a symmetrical shape with respect to the X- and Y-axes (this also applies to all examples to be described below).
  • Example 1 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the same side as the direction of the magnetic field in the hard-axis direction with respect to the ideal asteroid curve, as shown in FIG. 1 .
  • the shift amount (offset amount) which is converted into a magnetic field intensity is Ho.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located inside the actual asteroid curve (solid line). For this reason, in the write mode, even when the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is applied to the MTJ element, the magnetizing direction of the free layer (storing layer) of the MTJ element does not reverse. As a consequence, the write operation is impossible.
  • Example 1 the offset amount Ho generated due to the shift of the asteroid curve is added to the magnetic field H 1 in the hard-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (Ho) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (Ho) ⁇ )+ ⁇ right arrow over (H 2 ) ⁇ is located outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (Ho) ⁇ ) in the hard-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the intensity of the magnetic field in the shift direction is controlled to cancel the offset between the ideal asteroid curve and the actual asteroid curve.
  • the disabled write operation in the write mode can be avoided, and the reliability of the write operation can be increased.
  • Example 1 only the intensity of the magnetic field in the direction (hard-axis direction) of the shift of the asteroid curve is controlled in accordance with the offset amount.
  • Example 2 a technique will be proposed in which each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled in accordance with the offset amount independently of the direction (hard-axis direction) of the shift of the asteroid curve, thereby increasing the reliability of write operation.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • Example 2 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the same side as the direction of the magnetic field in the hard-axis direction with respect to the ideal asteroid curve, as shown in FIG. 2 .
  • the shift amount (offset amount) which is converted into a magnetic field intensity is Ho.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located inside the actual asteroid curve (solid line). For this reason, in the write mode, even when the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is applied to the MTJ element, the magnetizing direction of the free layer (storing layer) of the MTJ element does not reverse, and the write operation is impossible.
  • part H 3 e.g., Ho/2 of the offset amount Ho generated due to the shift of the asteroid curve is added to the magnetic field H 1 in the hard-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • part H 4 e.g., Ho/2 of the offset amount Ho is added to the magnetic field H 2 in the easy-axis direction.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) is located outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ ) in the hard-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) in the easy-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled independently of the shift direction (hard-axis direction in this example), thereby increasing the reliability of the write operation.
  • a selected MTJ element not only a selected MTJ element but also a plurality of unselected MTJ elements are arranged along a selected write word line.
  • the increase amount of the write current to be supplied to the write word line can be decreased by an amount corresponding to the increase in write current to be supplied to the write bit line.
  • the risk of write errors for the unselected MTJ elements arranged along the selected write word line can be reduced.
  • Example 3 is different from Example 1 in that the asteroid curve of a MTJ element shifts to the opposite side of the direction of the magnetic field in the hard-axis direction with respect to an ideal asteroid curve.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 1 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • Example 3 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the opposite side of the direction of the magnetic field in the hard-axis direction with respect to the ideal asteroid curve, as shown in FIG. 3 .
  • the shift amount (offset amount) which is converted into a magnetic field intensity is Ho.
  • Example 3 the offset amount Ho generated due to the shift of the asteroid curve is subtracted from the magnetic field H 1 in the hard-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (Ho) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (Ho) ⁇ )+ ⁇ right arrow over (H 2 ) ⁇ is located near and outside the actual asteroid curve (solid line). For this reason, only the magnetizing direction of the free layer (storing layer) of the selected MTJ element can be reversed without any write errors for unselected MTJ elements.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (Ho) ⁇ ) in the hard-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the intensity of the magnetic field in the shift direction is controlled to cancel the offset between the ideal asteroid curve and the actual asteroid curve.
  • the disabled write operation in the write mode can be avoided, and the reliability of the write operation can be increased.
  • Example 4 will be proposed in correspondence with Example 2.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled in accordance with the offset amount independently of the direction (hard-axis direction) of the shift of an asteroid curve, thereby increasing the reliability of write operation.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • Example 4 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the opposite side of the direction of the magnetic field in the hard-axis direction with respect to the ideal asteroid curve, as shown in FIG. 4 .
  • the shift amount (offset amount) which is converted into a is magnetic field intensity is Ho.
  • part H 3 (e.g., Ho/2) of the offset amount Ho generated due to the shift of the asteroid curve is subtracted from the magnetic field H 1 in the hard-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (H 3 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • part H 4 (e.g., Ho/2) of the offset amount Ho is subtracted from the magnetic field H 2 in the easy-axis direction.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (H 4 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (H 3 ) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ right arrow over (H 4 ) ⁇ ) is located near and outside the actual asteroid curve (solid line). For this reason, only the magnetizing direction of the free layer (storing layer) of the selected MTJ element can be reversed without any write errors for unselected MTJ elements.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (H 3 ) ⁇ ) in the hard-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (H 4 ) ⁇ ) in the easy-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled independently of the shift direction (hard-axis direction in this example), thereby increasing the reliability of the write operation.
  • the write principle of this example is based on the premise that the asteroid curve of a MTJ element shifts in the easy-axis direction.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • ideal asteroid curve means an asteroid curve having a symmetrical shape with respect to the X- and Y-axes (this also applies to all examples to be described below).
  • Example 1 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the same side as the direction of the magnetic field (its direction changes in accordance with write data) in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 5 .
  • the shift amount (offset amount) which is converted into a magnetic field intensity is Ho.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located inside the actual asteroid curve (solid line). For this reason, in the write mode, even when the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is applied to the MTJ element, the magnetizing direction of the free layer (storing layer) of the MTJ element does not reverse. As a consequence, the write operation is impossible.
  • Example 1 the offset amount Ho generated due to the shift of the asteroid curve is added to the magnetic field H 2 in the easy-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Ho) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ +( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Ho) ⁇ ) is located outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Ho) ⁇ ) in the easy-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • the intensity of the magnetic field in the shift direction is controlled to cancel the offset between the ideal asteroid curve and the actual asteroid curve.
  • the disabled write operation in the write mode can be avoided, and the reliability of the write operation can be increased.
  • Example 1 only the intensity of the magnetic field in the direction (easy-axis direction) of the shift of the asteroid curve is controlled in accordance with the offset amount.
  • Example 2 each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled in accordance with the offset amount independently of the direction (easy-axis direction) of the shift of the asteroid curve, thereby increasing the reliability of write operation.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • Example 2 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the same side as the direction of the magnetic field (its direction changes in accordance with write data) in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 6 .
  • the shift amount (offset amount) which is converted into a magnetic field intensity is Ho.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located inside the actual asteroid curve (solid line). For this reason, in the write mode, even when the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is applied to the MTJ element, the magnetizing direction of the free layer (storing layer) of the MTJ element does not reverse. As a consequence, the write operation is impossible.
  • part H 4 e.g., Ho/2 of the offset amount Ho generated due to the shift of the asteroid curve is added to the magnetic field H 2 in the easy-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • part H 3 e.g., Ho/2 of the offset amount Ho is added to the magnetic field H 1 in the hard-axis direction.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) is located outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ ) in the hard-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) in the easy-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled independently of the shift direction (easy-axis direction in this example), thereby increasing the reliability of the write operation.
  • Example 3 is different from Example 1 in that the asteroid curve of a MTJ element shifts to the opposite side of the direction of the magnetic field (its direction changes in accordance with write data) in the easy-axis direction with respect to an ideal asteroid curve.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • Example 3 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the opposite side of the direction of the magnetic field in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 7 .
  • the shift amount (offset amount) which is converted into a magnetic field intensity is Ho.
  • Example 3 the offset amount Ho generated due to the shift of the asteroid curve is subtracted from the magnetic field H 2 in the easy-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (Ho) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ +( ⁇ right arrow over (H 2 ) ⁇ right arrow over (Ho) ⁇ ) is located near and outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (Ho) ⁇ ) in the easy-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • the intensity of the magnetic field in the shift direction is controlled to cancel the offset between the ideal asteroid curve and the actual asteroid curve.
  • the disabled write operation in the write mode can be avoided, and the reliability of the write operation can be increased.
  • Example 4 will be proposed in correspondence with Example 2.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled in accordance with the offset amount independently of the direction (easy-axis direction) of the shift of an asteroid curve, thereby increasing the reliability of write operation.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • Example 4 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the opposite side of the direction of the magnetic field in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 8 .
  • the shift amount (offset amount) which is converted into a magnetic field intensity is Ho.
  • part H 4 e.g., Ho/2 of the offset amount Ho generated due to the shift of the asteroid curve is subtracted from the magnetic field H 2 in the easy-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (H 4 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • part H 3 (e.g., Ho/2) of the offset amount Ho generated due to the shift of the asteroid curve is subtracted from the magnetic field H 1 in the hard-axis direction.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (H 3 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (H 3 ) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ right arrow over (H 4 ) ⁇ ) is located near and outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (H 3 ) ⁇ ) in the hard-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (H 4 ) ⁇ ) in the easy-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled independently of the shift direction (hard-axis direction in this example), thereby increasing the reliability of the write operation.
  • Principle 2 is based on an example in which the asteroid curve shifts in the easy-axis direction.
  • the data value of a MTJ element is determined by the magnetizing direction in the easy-axis direction.
  • Example 3 when the situation described in Example 1 (or Example 2) occurs in a specific MTJ element, the situation described in Example 3 (or Example 4) also occurs in the specific MTJ element.
  • the situation described in Example 1 (or Example 2) occurs when data “1” is to be written in a specific MTJ element.
  • the situation described in Example 3 occurs when data “0” is to be written in the specific MTJ element.
  • Examples 1 and 3 (or Examples 2 and 4) may be combined.
  • the magnitude of the write current for the write word/bit line is controlled such that the synthesized magnetic field has an intensity given by ⁇ right arrow over (H 1 ) ⁇ +( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Ho) ⁇ ) or ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ).
  • the magnitude of the write current for the write word/bit line is controlled such that the synthesized magnetic field has an intensity given by ⁇ right arrow over (H 1 ) ⁇ +( ⁇ right arrow over (H 2 ) ⁇ right arrow over (Ho) ⁇ ) or ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (H 3 ) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ right arrow over (H 4 ) ⁇ )
  • the write principle of this example is based on the premise that the asteroid curve of a MTJ element shifts in the hard- and easy-axis directions.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • ideal asteroid curve means an asteroid curve having a symmetrical shape with respect to the X- and Y-axes (this also applies to all examples to be described below).
  • Example 1 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the same side as the direction of the magnetic field in the hard-axis direction and also to the same side as the direction of the magnetic field in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 9 .
  • the shift amounts (offset amounts) are Hox in the hard-axis direction and Hoy in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located inside the actual asteroid curve (solid line). For this reason, in the write mode, even when the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is applied to the MTJ element, the magnetizing direction of the free layer (storing layer) of the MTJ element does not reverse. As a consequence, the write operation is impossible.
  • Example 1 the offset amount Hox generated due to the shift of the asteroid curve is added to the magnetic field H 1 in the hard-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (Hox) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • the offset amount Hoy generated due to the shift of the asteroid curve is added to the magnetic field H 2 in the easy-axis direction.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Hoy) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (Hox) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Hoy) ⁇ ) is located outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (Hox) ⁇ ) in the hard-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Hoy) ⁇ ) in the easy-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • the intensities of the magnetic fields in the shift directions are controlled to cancel the offset between the ideal asteroid curve and the actual asteroid curve.
  • the disabled write operation in the write mode can be avoided, and the reliability of the write operation can be increased.
  • Example 2 is different from Example 1 in that the asteroid curve of a MTJ element shifts to the opposite side of the direction of the magnetic field in the hard-axis direction and also to the opposite side of the direction of the magnetic field in the easy-axis direction with respect to an ideal asteroid curve.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • Example 2 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory shifts to the opposite side of the direction of the magnetic field in the hard-axis direction and also to the opposite side of the direction of the magnetic field in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 10 .
  • the shift amounts (offset amounts) are Hox in the hard-axis direction and Hoy in the easy-axis direction.
  • Example 2 the offset amount Hox generated due to the shift of the asteroid curve is subtracted from the magnetic field H 1 in the hard-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (Hox) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • the offset amount Hoy generated due to the shift of the asteroid curve is subtracted from the magnetic field H 2 in the easy-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (Hoy) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (Hox) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ right arrow over (Hoy) ⁇ ) is located near and outside the actual asteroid curve (solid line). For this reason, only the magnetizing direction of the free layer (storing layer) of the selected MTJ element can be reversed without any write errors for unselected MTJ elements.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ right arrow over (Hox) ⁇ ) in the hard-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ right arrow over (Hoy) ⁇ ) in the easy-axis direction can easily be generated by decreasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • the intensities of the magnetic fields in the shift directions are controlled to cancel the offset between the ideal asteroid curve and the actual asteroid curve.
  • the disabled write operation in the write mode can be avoided, and the reliability of the write operation can be increased.
  • the write principle of this example is based on the premise that the asteroid curve of a MTJ element partially spreads in the hard-axis direction, and consequently, the asteroid curve becomes asymmetrical with respect to the Y-axis (easy-axis).
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • ideal asteroid curve means an asteroid curve having a symmetrical shape with respect to the X- and Y-axes (this also applies to all examples to be described below).
  • Example 1 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory partially spreads in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 11 .
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located inside the actual asteroid curve (solid line). For this reason, in the write mode, even when the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is applied to the MTJ element, the magnetizing direction of the free layer (storing layer) of the MTJ element does not reverse. As a consequence, the write operation is impossible.
  • Example 1 an offset amount Hoy generated due to the shift of the asteroid curve is added to the magnetic field H 2 in the easy-axis direction in the write mode.
  • a magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Hoy) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ +( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Hoy) ⁇ ) is located outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (Hoy) ⁇ ) in the easy-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • the intensity of the magnetic field in the spreading direction is controlled.
  • the disabled write operation in the write mode can be avoided, and the reliability of the write operation can be increased.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled in accordance with the offset amount independently of the deformation pattern of an asteroid curve, thereby increasing the reliability of write operation.
  • a synthesized magnetic field necessary for magnetization inversion which is determined on the basis of an ideal asteroid curve (broken line), is defined as ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ .
  • H 1 is a magnetic field in the X-axis (hard-axis) direction
  • H 2 is a magnetic field in the Y-axis (easy-axis) direction.
  • a point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located outside the ideal asteroid curve.
  • Example 2 assume that the asteroid curve (solid line) of a MTJ element of an actually manufactured magnetic random access memory partially spreads in the easy-axis direction with respect to the ideal asteroid curve, as shown in FIG. 12 .
  • the point that indicates the intensity of the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is located inside the actual asteroid curve (solid line). For this reason, in the write mode, even when the synthesized magnetic field ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 2 ) ⁇ is applied to the MTJ element, the magnetizing direction of the free layer (storing layer) of the MTJ element does not reverse. As a consequence, the write operation is impossible.
  • Example 2 ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ ) is defined as a magnetic field in the hard-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the hard-axis direction.
  • ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) is defined as a magnetic field in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) is caused to act on the MTJ element as the magnetic field in the easy-axis direction.
  • the point that indicates the intensity of the synthesized magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ )+( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) is located outside the actual asteroid curve (solid line). For this reason, the magnetizing direction of the free layer (storing layer) of the MTJ element can be reversed.
  • the magnetic field ( ⁇ right arrow over (H 1 ) ⁇ + ⁇ right arrow over (H 3 ) ⁇ ) in the hard-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a predetermine direction) to be supplied to a write word line that runs in the easy-axis direction.
  • the magnetic field ( ⁇ right arrow over (H 2 ) ⁇ + ⁇ right arrow over (H 4 ) ⁇ ) in the easy-axis direction can easily be generated by increasing, by a predetermined amount, the value of the write current (having a direction which changes in accordance with write data) to be supplied to a write bit line that runs in the hard-axis direction.
  • each of the intensities of the magnetic fields in the hard- and easy-axis directions is controlled independently of the deformation pattern, thereby increasing the reliability of the write operation.
  • Principles 1 to 4 are based on the premises that the asteroid curve of a MTJ element shifts or deforms. The techniques for canceling the offset of the asteroid curve due to the shift or deformation have been described above.
  • the asteroid curve of the MTJ element is actually symmetrical with respect to the X- and Y-axes, if the write characteristics of a MTJ element may change from the ideal value (design value), and for example, the positional relationship between the write word/bit line and the MTJ element changes, the examples of the present invention can also be used as a means for correcting the positional relationship.
  • the distance between the write word/bit line and the MTJ element may be smaller or larger than the ideal value due to mask misalignment or the like.
  • the distance between the write word/bit line and the MTJ element decreases, the magnetic field applied to the MTJ element becomes strong. Conversely, when the distance increases, the magnetic field applied to the MTJ element becomes weak.
  • control of the intensity of the magnetic field (the magnitude of the write current) according to the examples of the present invention is very effective.
  • the write principles described in Principles 1 to 5 are implemented by hardware in the magnetic random access memory (chip or cell array block). These write principles are set for each chip, each cell array block, each write word/bit line, or each MTJ element.
  • a write test is executed for MTJ elements in the memory cell array to grasp the write characteristics (e.g., asteroid curve) of each MTJ element (step ST 1 ).
  • the current waveforms (current values or the like) of the write word line current and write bit line current are determined for each chip, each cell array block, each write word/bit line, or each MTJ element in consideration of the variation in write characteristics between the MTJ elements (step ST 2 ).
  • FIG. 13 shows an example in which the current waveform of the write word/bit line current is determined for each chip (or for each cell array block).
  • FIG. 14 shows an example in which the current waveform of the write word/bit line current is determined for each write word/bit line.
  • FIG. 15 shows an example in which the current waveform of the write word/bit line current is determined for each MTJ element.
  • the write principle i.e., the current waveforms of the write word line current and write bit line current which are determined for each chip, each cell array block, each write word/bit line, or each MTJ element
  • the write principle i.e., the current waveforms of the write word line current and write bit line current which are determined for each chip, each cell array block, each write word/bit line, or each MTJ element
  • Programming is performed for a setting circuit arranged at a predetermined portion in a chip.
  • programming can be executed for, e.g., a laser blow fuse, a MTJ element (MTJ), or an antifuse which breaks the tunneling barrier of a MTJ element.
  • MTJ MTJ element
  • the current waveforms of the write word line current and write bit line current may be programmed in a programming element in the setting circuit.
  • the write principle according to an example of the present invention may be tested.
  • the current waveforms of the write word line current and write bit line current are determined on the basis of programming data stored in the setting circuit.
  • the write current is supplied from a driver connected to one end of a write word/bit line and absorbed by a sinker connected to the other end.
  • the function of the driver is stopped first.
  • the function of the sinker is stopped. With this arrangement, the potential of the write word/bit line can be completely set to 0 V.
  • a circuit including a function capable of setting the magnetic field intensity individually for each magnetizing reversing direction
  • which sets the magnitude of a write current i.e., the intensity of a write magnetic field necessary for reversing the magnetizing direction of the free layer (storing layer) of a MTJ element for each chip or cell array in consideration of such a variation in write characteristics (e.g., a shift of an asteroid curve) will be described first.
  • FIG. 16 shows the arrangement of main part of a magnetic random access memory according to an embodiment of the present invention.
  • a magnetic random access memory (MRAM) 11 may construct one memory chip by itself or one block in a chip having a specific function.
  • a memory cell array (data cell) 12 has a function of actually storing data.
  • a reference cell array 13 has a function of setting a criterion to be used to determine the value of read data in read operation.
  • a row decoder & driver (row decoder & write word line driver and row decoder & read word line driver) 14 is arranged at one of two Y-direction (easy-axis direction) ends of a cell array formed from the memory cell array 12 and reference cell array 13 .
  • a write word line sinker 15 is arranged at the other end.
  • the row decoder & driver 14 has a function of, e.g., selecting one of a plurality of write word lines on the basis of a row address signal and supplying a write current to the selected write word line in the write operation.
  • the write word line sinker 15 has a function of, e.g., absorbing the write current supplied to the selected write word line in the write operation.
  • the row decoder & driver 14 has a function of, e.g., selecting one of a plurality of read word lines (the read word lines may be integrated with the write word lines) on the basis of a row address signal and supplying a read current to the selected read word line in the read operation.
  • a sense amplifier 20 detects, e.g., the read current and determines read data.
  • a column decoder & write bit line driver/sinker 16 A is arranged at one of two X-direction (hard-axis direction) ends of the memory cell array 12 .
  • a column decoder & write bit line driver/sinker (including a column transfer gate and column decoder) 17 A is arranged at the other end.
  • the column decoders & write bit line drivers/sinkers 16 A and 17 A have a function of, e.g., selecting one of a plurality of write bit lines (or data lines) on the basis of a column address signal and supplying a write current having a direction corresponding to write data to the selected write bit line in the write operation.
  • the column transfer gate and column decoder have a function of electrically connecting the data line selected by the column address signal to the sense amplifier 20 in the read operation.
  • a reference cell column decoder & write bit line driver/sinker 16 B is arranged at one of two X-direction ends of the reference cell array 13 .
  • a reference cell column decoder & write bit line driver/sinker (including a column transfer gate and column decoder) 17 B is arranged at the other end.
  • the reference cell column decoders & write bit line drivers/sinkers 16 B and 17 B have a function of storing reference data in the reference cell array 13 .
  • the column transfer gate and column decoder have a function of reading out the reference data and transferring it to the sense amplifier 20 in the read operation.
  • An address receiver 18 receives an address signal and transfers, e.g., a row address signal to the row decoder & driver 14 and a column address signal to the column decoders & write bit line drivers/sinkers 16 A and 17 A.
  • a data input receiver 19 transfers the write data to the column decoders & write bit line drivers/sinkers 16 A and 17 A.
  • An output driver 21 outputs the read data detected by the sense amplifier 20 from the magnetic random access memory 11 .
  • a control circuit 22 receives a /CE (Chip Enable) signal, /WE (Write Enable) signal, and /OE (Output Enable) signal and controls the operation of the magnetic random access memory 11 .
  • the control circuit 22 supplies a write signal WRITE to a write current waveform control circuit 24 .
  • the write current waveform control circuit 24 Upon receiving the write signal WRITE, the write current waveform control circuit 24 generates a write word line drive signal WWLDRV, write word line sink signal WWLSNK, write bit line drive signal WBLDRV, and write bit line sink signal WBLSNK.
  • the write word line drive signal WWLDRV is supplied to the row decoder & driver 14 .
  • the write word line sink signal WWLSNK is supplied to the write word line sinker 15 .
  • the write bit line drive signal WBLDRV and write bit line sink signal WBLSNK are supplied to the column decoders & write bit line drivers/sinkers 16 A and 17 A.
  • a setting circuit 23 has a programming element. Setting data which determines the current waveform of the write word/bit line current is programmed in the programming element.
  • a programming element for example, a laser blow fuse, a MTJ element (MTJ), or an antifuse which breaks the tunneling barrier of a MTJ element can be used.
  • the setting circuit 23 In the write operation, the setting circuit 23 generates write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > and write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 > on the basis of the setting data.
  • the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > are supplied to the row decoder & driver 14 through the write current waveform control circuit 24 (or without intervening the write current waveform control circuit 24 ).
  • the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 > are supplied to the column decoder & write bit line driver/sinker 16 A through or without intervening the write current waveform control circuit 24 .
  • the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 > are supplied to the column decoder & write bit line driver/sinker 17 A through or without intervening the write current waveform control circuit 24 .
  • the row decoder & driver 14 determines the value (magnitude) of the write current to be supplied to a write word line selected by a row address signal, on the basis of the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the write word line sinker 15 and column decoders & write bit line drivers/sinkers 16 A and 17 A determine the value (magnitude) of the write current to be supplied to a write bit line selected by a column address signal, on the basis of the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 >.
  • the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 > determine the value of the write bit line current.
  • the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 > determine the value of the write bit line current.
  • the potential of the write word/bit line can be completely set to 0 V.
  • a write test for the MTJ element can be executed on the basis of, e.g., setting data D ⁇ j> input from a data input/output terminal.
  • the write characteristics of the MTJ elements in the memory cell array 12 are grasped, and the value of the write word/bit line current (the intensity of the synthesized magnetic field Hx+Hy) in the normal write operation is determined.
  • the setting data D ⁇ j> may be input from an address terminal.
  • the programming operation of setting data is performed in accordance with the result of the test mode.
  • the programming operation is operation of programming the result of the test mode, i.e., the value of the write word/bit line current in the programming element in the setting circuit 23 .
  • a program signal PROG changes to “H”.
  • the value of the write word/bit line current in the normal write operation is programmed in the programming element in the setting circuit 23 by controlling the value of the setting data D ⁇ j> input from the data input/output terminal or address terminal.
  • FIG. 17 shows a circuit example of the row decoder & write word line driver/sinker.
  • the row decoder & write word line driver (for one row) 14 is formed from an AND gate circuit AD 1 , NAND gate circuits NDWS 0 to NDWS 3 , and PMOS transistors WS 0 to WS 3 .
  • a write word line current waveform signal WS ⁇ i> is input to one of the two input terminals of the NAND gate circuit NDWSi.
  • the output signal from the AND gate circuit AD 1 is input to the other input terminal.
  • the write word line drive signal WWLDRV and a row address signal (changes for each row i) formed from a plurality of bits are input to the AND gate circuit AD 1 .
  • the write word line sinker (for one row) 15 is formed from an NMOS transistor TN 1 .
  • the source of the NMOS transistor TN 1 is connected to a ground terminal VSS, and the drain is connected to the other end of the write word line WWLi.
  • the write word line sink signal WWLSNK is input to the gate of the NMOS transistor TN 1 .
  • the write word line drive signal WWLDRV changes to “H”.
  • all bits of the row address signal change to “H”. That is, in the selected row i, since the output signal from the AND circuit AD 1 changes to “H”, a write word line current having a predetermined value (magnitude) is supplied to the write word line WWLi in accordance with the values of the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the write word line drive signal WWLDRV is set to “L”
  • the write word line sink signal WWLSNK is set to “L”
  • the potential of the write word line WWLi after the write operation can be completely set to 0 V. It is convenient for initialization.
  • the following control methods can be used.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors WS 0 to WS 3 are set to the same value.
  • the number of PMOS transistors WS 0 to WS 3 in the ON state is changed using the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors WS 0 to WS 3 are set to different values. Then, one of the plurality of PMOS transistors WS 0 to WS 3 is selectively turned on using write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the third method is a combination of the first and second methods. That is, the sizes of the PMOS transistors WS 0 to WS 3 are set to different values, and the number of PMOS transistors WS 0 to WS 3 in the ON state is changed, thereby controlling the value (magnitude) of the write current.
  • FIG. 18 shows a circuit example of the column decoder & write bit line driver/sinker.
  • the column decoder & write bit line driver/sinker (for one column) 16 A is formed from NAND gate circuits NDBSO to NDBS 3 , AND gate circuits AD 2 and AD 3 , PMOS transistors BS 0 to BS 3 , and NMOS transistor BN 0 .
  • the output signal from the AND gate circuit AD 2 is input to the other input terminal.
  • the write bit line drive signal WBLDRV, a column address signal (changes for each column i) formed from a plurality of bits, and write data DATA are input to the AND gate circuit AD 2 .
  • the write bit line sink signal WBLSNK, a column address signal (changes for each column i) formed from a plurality of bits, and an inverted signal bDATA of the write data are input to the AND gate circuit AD 3 .
  • the column decoder & write bit line driver/sinker (for one column) 17 A is formed from NAND gate circuits NDBS 4 to NDBS 7 , AND gate circuits AD 4 and AD 5 , PMOS transistors BS 4 to BS 7 , and NMOS transistor BN 1 .
  • the output signal from the AND gate circuit AD 4 is input to the other input terminal.
  • the write bit line drive signal WBLDRV, a column address signal (changes for each column i) formed from a plurality of bits, and the inverted signal bDATA of the write data are input to the AND gate circuit AD 4 .
  • the write bit line sink signal WBLSNK, column address signal (changes for each column i) formed from a plurality of bits, and write data DATA are input to the AND gate circuit AD 5 .
  • both the write bit line drive signal WBLDRV and the write bit line sink signal WBLSNK change to “H”.
  • all the bits of the column address signal change to “H”.
  • the value (magnitude) of the write current flowing from the column decoder & write bit line driver/sinker 16 A to the column decoder & write bit line driver/sinker 17 A is determined by the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >.
  • the value (magnitude) of the write current flowing from the column decoder & write bit line driver/sinker 17 A to the column decoder & write bit line driver/sinker 16 A is determined by the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 >.
  • the direction of the write current flowing to the write bit line WBLi is determined by the value of the write data DATA.
  • at least one of the PMOS transistors BS 0 to BS 3 is turned on by the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >.
  • the NMOS transistor BN 1 is also turned on. For this reason, the write current flows from the column decoder & write bit line driver/sinker 16 A to the column decoder & write bit line driver/sinker 17 A.
  • at least one of the PMOS transistors BS 4 to BS 7 is turned on by the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 >.
  • the NMOS transistor BN 0 is also turned on. For this reason, the write current flows from the column decoder & write bit line driver/sinker 17 A to the column decoder & write bit line driver/sinker 16 A.
  • the write bit line drive signal WBLDRV is set to “L”
  • the write bit line sink signal WBLSNK is set to “L”
  • the potential of the write bit line WBLi after the write operation can be completely set to 0 V. It is convenient for initialization.
  • the following control methods can be used.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors BS 0 to BS 7 are set to the same value.
  • the number of PMOS transistors BS 0 to BS 7 in the ON state is changed using the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 >.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors BS 0 to BS 7 are set to different values. Then, one of the plurality of PMOS transistors BS 0 to BS 7 is selectively turned on using write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 >.
  • the third method is a combination of the first and second methods. That is, the sizes of the PMOS transistors BS 0 to BS 7 are set to different values, and the number of PMOS transistors BS 0 to BS 7 in the ON state is changed, thereby controlling the value (magnitude) of the write current.
  • write current waveform control circuit which generates the write word line drive signal WWLDRV, write word line sink signal WWLSNK, write bit line drive signal WBLDRV, and write bit line sink signal WBLSNK will be described next.
  • FIG. 19 shows an example of the write current waveform control circuit.
  • the write current waveform control circuit 24 is constituted by a WWLDRV generation circuit 25 X, WWLSNK generation circuit 25 Y, WBLDRV generation circuit 26 X, and WBLSNK generation circuit 26 Y.
  • the WWLDRV generation circuit 25 X is formed from inverters IV 0 and IV 1 .
  • the WWLDRV generation circuit 25 X generates the write word line drive signal WWLDRV on the basis of the write signal WRITE.
  • the WWLSNK generation circuit 25 Y is formed from a NAND gate circuit ND 1 and delay circuit 27 .
  • the WWLSNK generation circuit 25 Y generates the write word line sink signal WWLSNK on the basis of the write signal WRITE.
  • the WBLDRV generation circuit 26 X is formed from inverters IV 2 and IV 3 .
  • the WBLDRV generation circuit 26 X generates the write bit line drive signal WBLDRV on the basis of the write signal WRITE.
  • the WBLSNK generation circuit 26 Y is formed from a NAND gate circuit ND 2 and delay circuit 28 .
  • the WBLSNK generation circuit 26 Y generates the write bit line sink signal WBLSNK on the basis of the write signal WRITE.
  • the write signal WRITE changes to “H”.
  • the write word/bit line drive signals WWLDRV and WBLDRV and write word/bit line sink signals WWLSNK and WBLSNK almost simultaneously change from “L” to “H”.
  • the delay circuits 27 and 28 determine the time (interval) from the change of the write signal WRITE from “H” to “L” and the change of the write word/bit line drive signals WWLDRV and WBLDRV from “H” to “L” to the change of the write word/bit line sink signals WWLSNK and WBLSNK from “H” to “L”.
  • the setting circuit which generates the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > and write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 > will be described next.
  • FIG. 20 shows an example of the setting circuit.
  • the setting circuit 23 is formed from a first portion which generates the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > and a second portion which generates the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >.
  • the first portion has registers ⁇ 0 > and ⁇ 1 > in which setting data that determine the current waveform (magnitude) of the write word line current are programmed, and decoders WS ⁇ 0 > to WS ⁇ 3 > which decode output signals TD ⁇ 0 >, TD ⁇ 1 >, bTD ⁇ 0 >, and bTD ⁇ 1 > from the registers ⁇ 0 > and ⁇ 1 > and output the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the second portion has registers ⁇ 2 > to ⁇ 4 > in which setting data that determine the current waveform (magnitude) of the write bit line current are programmed, and decoders BS ⁇ 0 > to BS ⁇ 7 > which decode output signals TD ⁇ 2 > to TD ⁇ 4 > and bTD ⁇ 2 > to bTD ⁇ 4 > from the registers ⁇ 2 > to ⁇ 4 > and output the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 >.
  • the write word/bit line current is set for each chip or cell array.
  • the write word/bit line current is to be set for each chip, only one setting circuit 23 is arranged in the chip.
  • the setting circuits 23 equal in number to that of the cell arrays are arranged.
  • Setting data which determine the current waveform of the write word line current are programmed in the registers ⁇ 0 > and ⁇ 1 >.
  • the current waveform of the write word line current is controlled by the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >, as shown in FIG. 17 .
  • one of the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > changes to “H” in accordance with 2-bit setting data registered in the registers ⁇ 0 > and ⁇ 1 >.
  • the number of write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > to be changed to “H” may be controlled by the 2-bit setting data registered in the registers ⁇ 0 > and ⁇ 1 >. In this case, even when the PMOS transistors WS 0 to WS 3 shown in FIG. 17 have the same size, four current waveforms can be implemented.
  • D ⁇ 0 > and D ⁇ 1 > are setting data which are input from the outside of the magnetic random access memory (chip) in the test mode.
  • the current waveform of the write word line current can be determined on the basis of these setting data, and the characteristics of the MTJ element can be tested.
  • D ⁇ 0 > and D ⁇ 1 > are also setting data which are input from the outside of the magnetic random access memory (chip) in the setting data registration mode.
  • the setting data can electrically be programmed in the storage elements in the registers ⁇ 0 > and ⁇ 1 > on the basis of these setting data.
  • Setting data which determine the current waveform of the write bit line current are programmed in the registers ⁇ 2 > to ⁇ 4 >.
  • the current waveform of the write bit line current is controlled by the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >, as shown in FIG. 18 .
  • one of the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 > changes to “H” in accordance with 3-bit setting data registered in the registers ⁇ 2 > to ⁇ 4 >.
  • the number of write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 > to be changed to “H” may be controlled by the 3-bit setting data registered in the registers ⁇ 2 > to ⁇ 4 >. In this case, even when the PMOS transistors BS 0 to BS 7 shown in FIG. 18 have the same size, four current waveforms can be implemented for each direction of the write bit line current.
  • D ⁇ 2 > to D ⁇ 4 > are setting data which are input from the outside of the magnetic random access memory (chip) in the test mode.
  • the current waveform of the write bit line current can be determined on the basis of these setting data, and the characteristics of the MTJ element can be tested.
  • D ⁇ 2 > to D ⁇ 4 > are also setting data which are input from the outside of the magnetic random access memory (chip) in the setting data registration mode.
  • the setting data can electrically be programmed in the storage elements in the registers ⁇ 2 > to ⁇ 4 > on the basis of these setting data.
  • FIG. 21 shows a circuit example of the register.
  • the program data output circuit 29 has a laser blow fuse 29 A to store setting data. One-bit data is stored in accordance with whether the laser blow fuse 29 A is cut.
  • a PMOS transistor P 1 and laser blow fuse 29 A are connected in series between the power supply terminal VDD and the ground terminal VSS. Since the gate of the PMOS transistor P 1 is connected to the ground terminal VSS, the PMOS transistor P 1 is always ON.
  • connection point between the PMOS transistor P 1 and the laser blow fuse 29 A is connected to the input terminal of an inverter I 7 through an inverter I 9 and transfer gate TG 4 .
  • the output signal from the inverter I 7 is bTD ⁇ j>, and the output signal from an inverter I 8 is TD ⁇ j>.
  • the input data transfer circuit 30 is formed from transfer gates TG 1 to TG 3 and inverters I 5 and I 6 .
  • the inverters I 5 and I 6 and transfer gate TG 3 constitute a latch circuit.
  • a test signal VCTEST changes to “L”
  • a test signal bVCTEST changes to “H”.
  • the transfer gate TG 4 is turned on, and the transfer gates TG 1 and TG 2 are turned off.
  • the setting data programmed in the laser blow fuse 29 A is output as the output signals TD ⁇ j> and bTD ⁇ j> through the transfer gate TG 4 and inverters I 7 to I 9 .
  • test signal VCTEST changes to “H”
  • test signal bVCTEST changes to “L”.
  • the transfer gates TG 1 and TG 2 are turned on, and the transfer gates TG 3 and TG 4 are turned off.
  • the setting data D ⁇ j> input from an external terminal is output as the output signals TD ⁇ j> and bTD ⁇ j> through the transfer gates TG 1 and TG 2 and inverters I 5 to I 8 .
  • test signal VCTEST changes to “L”
  • test signal bVCTEST changes to “H”.
  • the transfer gates TG 1 and TG 2 are turned off, and the transfer gates TG 3 and TG 4 are turned on.
  • the setting data D ⁇ j> input from the external terminal is latched by the latch circuit formed from the transfer gate TG 3 and inverters I 5 and I 6 . After that, a write test can be performed on the basis of the setting data latched by the latch circuit.
  • MTJ MTJ element
  • MTJ element which stores data in accordance with the magnetized state
  • MTJ element which stores data on the basis of whether the tunneling barrier is broken
  • FIG. 22 shows another circuit example of the register.
  • the register ⁇ j> of this example has its characteristic feature in the structure of the program data output circuit 29 , as compared to the register ⁇ j> shown in FIG. 21 . More specifically, the register ⁇ j> shown in FIG. 21 uses the laser blow fuse 29 A as an element for storing setting data. The register ⁇ j> of this example uses a MTJ element (MTJ) as an element for storing setting data.
  • MTJ MTJ element
  • the program data output circuit 29 has a MTJ element MTJ which stores setting data.
  • Setting data can be stored in the MTJ element MTJ in accordance with the magnetized state of the MTJ element, i.e., the relationship (parallel or antiparallel) between the magnetizing direction of the fixed layer and that of the storing layer.
  • this example does not use the above method.
  • the MR ratio of the MTJ element MTJ is 20% to 40%
  • a high voltage may be applied across the MTJ element MTJ in reading the setting data, and a read error may occur.
  • the MR ratio decreases. For this reason, when setting data is stored in accordance with the magnetized state of the MTJ element, and a high bias voltage is used to obtain a large read signal amount, the MR ratio (the difference in read signal amount between “1” data and “0” data) becomes low, and a read error occurs at a high probability.
  • the setting data is programmed on the basis of not the relationship between the magnetizing direction of the fixed layer and that of the storing layer but whether dielectric breakdown occurs in the tunneling barrier.
  • the setting data can be kept stored semipermanently.
  • One terminal of the MTJ element MTJ is connected to the power supply terminal VDD through the PMOS transistor P 1 and an NMOS transistor N 1 .
  • the other terminal is connected to the ground terminal VSS through an NMOS transistor N 2 .
  • the gate of the PMOS transistor P 1 is connected to the ground terminal VSS, and the gate of the NMOS transistor N 2 is connected to the ground terminal VSS. For this reason, the MOS transistors P 1 and N 2 are always ON.
  • a clamp potential Vclamp is input to the gate of the NMOS transistor N 1 .
  • the clamp potential Vclamp is set to an appropriate value, any high voltage application between the electrodes of the MTJ element MTJ can be prevented in reading the setting data.
  • FIG. 23 shows an example of a Vclamp generation circuit which generates the clamp potential Vclamp.
  • a Vclamp generation circuit 31 of this example obtains the clamp potential Vclamp by resistance-dividing the output voltage from a BGR circuit.
  • the clamp potential Vclamp is 0.3 to 0.5 V.
  • a NAND gate circuit ND 4 and PMOS transistor P 2 are elements which are necessary when the setting data programming method using dielectric breakdown of the MTJ element MTJ should be employed.
  • a program signal PROG changes to “H”.
  • the output signal from the NAND gate circuit ND 4 changes to “L”, and the PMOS transistor P 2 is turned on.
  • a high voltage is applied across the MTJ element MTJ to break the tunneling barrier of the MTJ element MTJ.
  • the setting data “1” is programmed in the MTJ element MTJ.
  • TD ⁇ j> is “L”
  • bTD ⁇ j> is “H”.
  • the output signal from the NAND gate circuit ND 4 changes to “H”, and the PMOS transistor P 2 is turned off. Since no high voltage is applied across the MTJ element MTJ, the tunneling barrier of the MTJ element MTJ is not broken. As a result, the setting data “0” is programmed in the MTJ element MTJ. In this case, TD ⁇ j> is “H”, and bTD ⁇ j> is “L”.
  • connection point between the PMOS transistor P 1 and the NMOS transistor N 1 is connected to the input terminal of the inverter I 7 through the inverter I 9 and transfer gate TG 4 .
  • the output signal from the inverter I 7 is bTD ⁇ j>, and the output signal from the inverter I 8 is TD ⁇ j>.
  • FIG. 24 shows a circuit example of the decoder.
  • Each of the decoders WS ⁇ 0 > to WS ⁇ 3 > and BS ⁇ 0 > to BS ⁇ 7 > is formed from a NAND gate circuit ND 3 and inverter I 10 .
  • Three input signals A, B, and C are input to the NAND gate circuit ND 3 .
  • the output signal from the NAND gate circuit ND 3 is input to the inverter I 10 .
  • An output signal D from the inverter I 10 is one of the write word/bit line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > and BS ⁇ 0 > to BS ⁇ 7 >.
  • Table 1 is the decoding table (the relationship between the input signals and the output signals) of the decoders WS ⁇ 0 > to WS ⁇ 3 > and BS ⁇ 0 > to BS ⁇ 7 >.
  • FIG. 25 shows an example of the operation waveforms of the write word line driver/sinker shown in FIG. 17 .
  • the write word line drive signal WWLDRV changes to “L” first.
  • the write word line sink signal WWLSNK changes to “L”. This predetermined time is prepared to set the potential of the write word line WWLi to 0 V after the end of write operation.
  • FIG. 26 shows an example of the operation waveforms of the write bit line driver/sinker shown in FIG. 18 .
  • the write bit line drive signal WBLDRV changes to “L” first.
  • the write bit line sink signal WBLSNK changes to “L”. This predetermined time is prepared to set the potential of the write bit line WBLi to 0 V after the end of write operation.
  • the current waveform (magnitude) of the write current for the write word/bit line can be set for each chip or memory cell array by programming.
  • the current waveform of the write word line current and that of the write bit line current can independently be determined.
  • the current waveform of the write bit line current can be determined individually for each write data value (direction of the write current).
  • Write characteristics or asteroid curves of MTJ elements may change between write word/bit lines due to manufacturing variations.
  • a circuit including a function capable of setting the magnetic field intensity individually for each magnetizing reversing direction
  • which sets the magnitude of a write current i.e., the intensity of a write magnetic field necessary for reversing the magnetizing direction of the free layer (storing layer) of a MTJ element for each write word/bit line in consideration of such a variation in write characteristics (e.g., a shift of an asteroid curve) will be described.
  • FIG. 27 shows the arrangement of main part of a magnetic random access memory according to another embodiment of the present invention.
  • a magnetic random access memory (MRAM) 11 may construct one memory chip by itself or one block in a chip having a specific function.
  • a memory cell array (data cell) 12 has a function of actually storing data.
  • a reference cell array 13 has a function of setting a criterion to be used to determine the value of read data in read operation.
  • a row decoder & driver (row decoder & write word line driver and row decoder & read word line driver) 14 - 1 is arranged at one of two X-direction ends of a cell array formed from the memory cell array 12 and reference cell array 13 .
  • a write word line sinker 15 is arranged at the other end.
  • the row decoder & driver 14 - 1 has a function of, e.g., selecting one of a plurality of write word lines on the basis of a row address signal and supplying a write current to the selected write word line in the write operation.
  • the write word line sinker 15 has a function of, e.g., absorbing the write current supplied to the selected write word line in the write operation.
  • the row decoder & driver 14 - 1 has a function of, e.g., selecting one of a plurality of read word lines (the read word lines may be integrated with the write word lines) on the basis of a row address signal and supplying a read current to the selected read word line in the read operation.
  • a sense amplifier 20 detects, e.g., the read current and determines read data.
  • a column decoder & write bit line driver/sinker 16 A- 1 is arranged at one of two Y-direction ends of the memory cell array 12 .
  • a column decoder & write bit line driver/sinker (including a column transfer gate and column decoder) 17 A- 1 is arranged at the other end.
  • the column decoders & write bit line drivers/sinkers 16 A- 1 and 17 A- 1 have a function of, e.g., selecting one of a plurality of write bit lines (or data lines) on the basis of a column address signal and supplying a write current having a direction corresponding to write data to the selected write bit line in the write operation.
  • the column transfer gate and column decoder have a function of electrically connecting the data line selected by the column address signal to the sense amplifier 20 in the read operation.
  • a reference cell column decoder & write bit line driver/sinker 16 B is arranged at one of two Y-direction ends of the reference cell array 13 .
  • a reference cell column decoder & write bit line driver/sinker (including a column transfer gate and column decoder) 17 B is arranged at the other end.
  • the reference cell column decoders & write bit line drivers/sinkers 16 B and 17 B have a function of storing reference data in the reference cell array 13 .
  • the column transfer gate and column decoder have a function of reading out the reference data and transferring it to the sense amplifier 20 in the read operation.
  • An address receiver 18 receives an address signal and transfers, e.g., a row address signal to the row decoder & driver 14 - 1 and a column address signal to the column decoders & write bit line drivers/sinkers 16 A- 1 and 17 A- 1 .
  • a data input receiver 19 transfers the write data to the column decoders & write bit line drivers/sinkers 16 A- 1 and 17 A- 1 .
  • An output driver 21 outputs the read data detected by the sense amplifier 20 from the magnetic random access memory 11 .
  • a control circuit 22 receives a /CE (Chip Enable) signal, /WE (Write Enable) signal, and /OE (Output Enable) signal and controls the operation of the magnetic random access memory 11 .
  • the control circuit 22 supplies a write signal WRITE to write current waveform control circuits/setting circuits 14 - 2 , 16 A- 2 , and 17 A- 2 .
  • each of the write current waveform control circuits/setting circuits 14 - 2 , 16 A- 2 , and 17 A- 2 determines the current waveforms (magnitudes and the like) of write currents on the basis of, e.g., setting data that are programmed in the setting circuit in advance.
  • the write current waveform control circuit/setting circuit 14 - 2 supplies a write word line drive signal WWLDRV and write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > to the row decoder & driver 14 - 1 and a write word line sink signal WWLSNK to the write word line sinker 15 .
  • the write current waveform control circuits/setting circuits 16 A- 2 and 17 A- 2 supply a write bit line drive signal WBLDRV, write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 >, and write bit line sink signal WBLSNK to the column decoders & write bit line drivers/sinkers 16 A- 1 and 17 A- 1 .
  • the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > are supplied, individually for each write word line, to the row decoders & write word line drivers arranged in correspondence with the write word lines. With this arrangement, the current waveform of the write current can be controlled for each write word line.
  • the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 > are supplied, individually for each write bit line, to the column decoders & write bit line drivers arranged in correspondence with the write bit lines. With this arrangement, the current waveform of the write current can be controlled for each write bit line.
  • the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 > determine the current waveforms of the write bit line currents that flow in one direction.
  • the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 > determine the current waveforms of the write bit line currents that flow in the other direction reverse to one direction. Hence, the current waveform of the write current can be controlled for each write word/bit line and each write data.
  • the potential of the write word/bit line can be completely set to 0 V.
  • the values of the write word line drive signals WS ⁇ 0 > to WS ⁇ 3 > are determined on the basis of, e.g., setting data programmed in the setting circuit in advance.
  • the values of the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 > are also determined on the basis of, e.g., setting data programmed in the setting circuit.
  • a programming element which stores setting data for example, a laser blow fuse, a MTJ element (MTJ), or an antifuse which breaks the tunneling barrier of a MTJ element can be used.
  • MTJ MTJ element
  • an antifuse which breaks the tunneling barrier of a MTJ element can be used.
  • a write test for the MTJ element may be executed on the basis of setting data D ⁇ j> input from, e.g., a data input/output terminal.
  • the setting data may be input from an address terminal.
  • the programming operation of setting data is performed in accordance with the result of the test mode.
  • the programming operation is operation of programming the result of the test mode, i.e., the value of the write word/bit line current in the programming element in the setting circuit.
  • a program signal PROG changes to “H”.
  • the value of the write word/bit line current in the normal write operation is programmed in, e.g., the programming element in the setting circuit 23 by controlling the value of the setting data D ⁇ j> input from the data input/output terminal or address terminal.
  • FIG. 28 shows a circuit example of the row decoder & write word line driver/sinker.
  • the row decoder & write word line driver (for one row) 14 - 1 is formed from an AND gate circuit AD 1 , NAND gate circuits NDWS 0 to NDWS 3 , and PMOS transistors WS 0 to WS 3 .
  • a write word line current waveform signal WS ⁇ i> is input to one of the two input terminals of the NAND gate circuit NDWSi.
  • the output signal from the AND gate circuit AD 1 is input to the other input terminal.
  • the write word line drive signal WWLDRV and a row address signal (changes for each row i) formed from a plurality of bits are input to the AND gate circuit AD 1 .
  • the write word line sinker (for one row) 15 is formed from an NMOS transistor TN 1 .
  • the source of the NMOS transistor TN 1 is connected to a ground terminal VSS, and the drain is connected to the other end of the write word line WWLi.
  • the write word line sink signal WWLSNK is input to the gate of the NMOS transistor TN 1 .
  • the write word line drive signal WWLDRV changes to “H”.
  • all bits of the row address signal change to “H”. That is, in the selected row i, since the output signal from the AND circuit AD 1 changes to “H”, a write word line current having a predetermined value (magnitude) is supplied to the write word line WWLi in accordance with the values of the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the write word line drive signal WWLDRV is set to “L”
  • the write word line sink signal WWLSNK is set to “L”
  • the potential of the write word line WWLi after the write operation can be completely set to 0 V. It is convenient for initialization.
  • the following control methods can be used.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors WS 0 to WS 3 are set to the same value.
  • the number of PMOS transistors WS 0 to WS 3 in the ON state is changed using the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors WS 0 to WS 3 are set to different values. Then, one of the plurality of PMOS transistors WS 0 to WS 3 is selectively turned on using write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 >.
  • the third method is a combination of the first and second methods. That is, the sizes of the PMOS transistors WS 0 to WS 3 are set to different values, and the number of PMOS transistors WS 0 to WS 3 in the ON state is changed, thereby controlling the value (magnitude) of the write current.
  • FIG. 29 shows a circuit example of the column decoder & write bit line driver/sinker.
  • the column decoder & write bit line driver/sinker (for one column) 16 A- 1 is formed from NAND gate circuits NDBS 0 to NDBS 3 , AND gate circuits AD 2 and AD 3 , PMOS transistors BS 0 to BS 3 , and NMOS transistor BN 0 .
  • the output signal from the AND gate circuit AD 2 is input to the other input terminal.
  • the write bit line drive signal WBLDRV, a column address signal (changes for each column i) formed from a plurality of bits, and write data DATA are input to the AND gate circuit AD 2 .
  • the write bit line sink signal WBLSNK, a column address signal (changes for each column i) formed from a plurality of bits, and an inverted signal bDATA of the write data are input to the AND gate circuit AD 3 .
  • the column decoder & write bit line driver/sinker (for one column) 17 A- 1 is formed from NAND gate circuits NDBS 4 to NDBS 7 , AND gate circuits AD 4 and AD 5 , PMOS transistors BS 4 to BS 7 , and NMOS transistor BN 1 .
  • the output signal from the AND gate circuit AD 4 is input to the other input terminal.
  • the write bit line drive signal WBLDRV, a column address signal (changes for each column i) formed from a plurality of bits, and the inverted signal bDATA of the write data are input to the AND gate circuit AD 4 .
  • the write bit line sink signal WBLSNK, column address signal (changes for each column i) formed from a plurality of bits, and write data DATA are input to the AND gate circuit ADS.
  • both the write bit line drive signal WBLDRV and the write bit line sink signal WBLSNK change to “H”.
  • all the bits of the column address signal change to “H”.
  • the value (magnitude) of the write current flowing from the column decoder & write bit line driver/sinker 16 A- 1 to the column decoder & write bit line driver/sinker 17 A- 1 is determined by the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >.
  • the value (magnitude) of the write current flowing from the column decoder & write bit line driver/sinker 17 A- 1 to the column decoder & write bit line driver/sinker 16 A- 1 is determined by the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 >.
  • the direction of the write current flowing to the write bit line WBLi is determined by the value of the write data DATA.
  • at least one of the PMOS transistors BS 0 to BS 3 is turned on by the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >.
  • the NMOS transistor BN 1 is also turned on. For this reason, the write current flows from the column decoder & write bit line driver/sinker 16 A- 1 to the column decoder & write bit line driver/sinker 17 A- 1 .
  • at least one of the PMOS transistors BS 4 to BS 7 is turned on by the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 >.
  • the NMOS transistor BN 0 is also turned on. For this reason, the write current flows from the column decoder & write bit line driver/sinker 17 A- 1 to the column decoder & write bit line driver/sinker 16 A- 1 .
  • the write bit line drive signal WBLDRV is set to “L”
  • the write bit line sink signal WBLSNK is set to “L”
  • the potential of the write bit line WBLi after the write operation can be completely set to 0 V. It is convenient for initialization.
  • the following control methods can be used.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors BS 0 to BS 7 are set to the same value.
  • the number of PMOS transistors BS 0 to BS 7 in the ON state is changed using the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 >.
  • the sizes (channel widths), i.e., the driving capabilities of the plurality of PMOS transistors BS 0 to BS 7 are set to different values. Then, one of the plurality of PMOS transistors BS 0 to BS 7 is selectively turned on using write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 7 >.
  • the third method is a combination of the first and second methods. That is, the sizes of the PMOS transistors BS 0 to BS 7 are set to different values, and the number of PMOS transistors BS 0 to BS 7 in the ON state is changed, thereby controlling the value (magnitude) of the write current.
  • write current waveform control circuit/setting circuit which generates the write word line drive signal WWLDRV, write word line sink signal WWLSNK, write bit line drive signal WBLDRV, and write bit line sink signal WBLSNK will be described next.
  • FIG. 30 shows an example of the write current waveform control circuit/setting circuit 14 - 2 in FIG. 27 .
  • FIG. 30 shows the write current waveform control circuit/setting circuit 14 - 2 corresponding to only one row. Hence, the actual number of each of the elements (write word line driver/sinker trigger circuit 25 and setting circuit 23 A) shown in FIG. 30 equals the number of rows.
  • the write current waveform control circuit/setting circuit 14 - 2 is formed from the write word line driver/sinker trigger circuit 25 and setting circuit 23 A.
  • the write word line driver/sinker trigger circuit 25 generates the write word line drive signal WWLDRV and write word line sink signal WWLSNK on the basis of the write signal WRITE.
  • the setting circuit 23 A outputs the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > on the basis of setting data.
  • the setting data is programmed in advance in a programming element (fuse element, MTJ element, or the like) in the setting circuit 23 A on the basis of the program signal PROG, address signal (row i), and input data D ⁇ 0 > to D ⁇ 3 >.
  • the setting data can be programmed at any time, e.g., in a wafer state or in a product state after assembly.
  • the setting data can be registered in the setting circuit 23 A by inputting the input data D ⁇ 0 > to D ⁇ 3 > from, e.g., a data input pin, address pin, or dedicated pin.
  • the write signal WRITE changes to “H” in the write operation.
  • the write word line driver/sinker trigger circuit 25 changes the write word line drive signal WWLDRV and write word line sink signal WWLSNK to “H”.
  • the setting circuit 23 A always outputs the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > based on the setting data.
  • the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > determine the current waveform of the write word line current.
  • FIG. 31 shows an example of the write current waveform control circuit/setting circuit 16 A- 2 in FIG. 27 .
  • FIG. 31 shows the write current waveform control circuit/setting circuit 16 A- 2 corresponding to only one column.
  • the actual number of each of the elements (write bit line driver/sinker trigger circuit 26 - 1 and setting circuit 23 B- 1 ) shown in FIG. 31 equals the number of columns.
  • the write current waveform control circuit/setting circuit 16 A- 2 is formed from the write bit line driver/sinker trigger circuit 26 - 1 and setting circuit 23 B- 1 .
  • the write bit line driver/sinker trigger circuit 26 - 1 generates the write bit line drive signal WBLDRV and write bit line sink signal WBLSNK on the basis of the write signal WRITE.
  • the setting circuit 23 B- 1 outputs the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 > on the basis of setting data.
  • the setting data is programmed in advance in a programming element (fuse element, MTJ element, or the like) in the setting circuit 23 B- 1 on the basis of the program signal PROG, address signal (column i), and input data D ⁇ 0 > to D ⁇ 3 >.
  • the setting data can be programmed at any time, e.g., in a wafer state or in a product state after assembly.
  • the setting data can be registered in the setting circuit 23 B- 1 by inputting the input data D ⁇ 0 > to D ⁇ 3 > from, e.g., a data input pin, address pin, or dedicated pin.
  • the write signal WRITE changes to “H” in the write operation.
  • the write bit line driver/sinker trigger circuit 26 - 1 changes the write bit line drive signal WBLDRV and write bit line sink signal WBLSNK to “H”.
  • the setting circuit 23 B- 1 always outputs the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >.
  • the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 > determine the current waveform of the write bit line current.
  • FIG. 32 shows an example of the write current waveform control circuit/setting circuit 17 A- 2 in FIG. 27 .
  • FIG. 32 shows the write current waveform control circuit/setting circuit 17 A- 2 corresponding to only one column.
  • the actual number of each of the elements (write bit line driver/sinker trigger circuit 26 - 2 and setting circuit 23 B- 2 ) shown in FIG. 32 equals the number of columns.
  • the write current waveform control circuit/setting circuit 17 A- 2 is formed from the write bit line driver/sinker trigger circuit 26 - 2 and setting circuit 23 B- 2 .
  • the write bit line driver/sinker trigger circuit 26 - 2 generates the write bit line drive signal WBLDRV and write bit line sink signal WBLSNK on the basis of the write signal WRITE.
  • the setting circuit 23 B- 2 outputs the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 > on the basis of setting data.
  • the setting data is programmed in advance in a programming element (fuse element, MTJ element, or the like) in the setting circuit 23 B- 2 on the basis of the program signal PROG, address signal (column i), and input data D ⁇ 4 > to D ⁇ 7 >.
  • the setting data can be programmed at any time, e.g., in a wafer state or in a product state after assembly.
  • the setting data can be registered in the setting circuit 23 B- 2 by inputting the input data D ⁇ 4 > to D ⁇ 7 > from, e.g., a data input pin, address pin, or dedicated pin.
  • the write signal WRITE changes to “H” in the write operation.
  • the write bit line driver/sinker trigger circuit 26 - 2 changes the write bit line drive signal WBLDRV and write bit line sink signal WBLSNK to “H”.
  • the setting circuit 23 B- 2 always outputs the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 >.
  • the write bit line current waveform signals BS ⁇ 4 > to BS ⁇ 7 > determine the current waveform of the write bit line current.
  • FIG. 33 shows an example of the write word line driver/sinker trigger circuit shown in FIG. 30 .
  • the write word line driver/sinker trigger circuit 25 is formed from a current supply/cutoff timing determining circuit 25 X which determines the current supply/cutoff timing of the write current and a current absorption timing determining circuit 25 Y which determines the current absorption timing of the write current.
  • the current supply/cutoff timing determining circuit 25 X is formed from a plurality of (in this example, two) inverters IV 0 and IV 1 .
  • the current supply/cutoff timing determining circuit 25 X determines the timing to change the write word line drive signal WWLDRV to “H” or “L” in accordance with the timing to change the write signal WRITE to “H” or “L”.
  • the current absorption timing determining circuit 25 Y is formed from a NAND gate circuit ND 1 and delay circuit 27 .
  • the current absorption timing determining circuit 25 Y almost simultaneously changes the write word line sink signal WWLSNK to “H”.
  • the current absorption timing determining circuit 25 Y changes the write word line sink signal WWLSNK to “L”.
  • the write signal WRITE is changed to “L” first.
  • the write word line sink signal WWLSNK is changed to “L”.
  • the write word line WWLi can be completely set to 0 V after the end of write operation.
  • FIG. 34 shows an example of the write bit line driver/sinker trigger circuit shown in FIG. 31 .
  • the write bit line driver/sinker trigger circuit 26 - 1 is formed from a current supply/cutoff timing determining circuit 26 X which determines the current supply/cutoff timing of the write current and a current absorption timing determining circuit 26 Y which determines the current absorption timing of the write current.
  • the current supply/cutoff timing determining circuit 26 X is formed from the plurality of (in this example, two) inverters IV 0 and IV 1 .
  • the current supply/cutoff timing determining circuit 26 X determines the timing to change the write bit line drive signal WBLDRV to “H” or “L” in accordance with the timing to change the write signal WRITE to “H” or “L”.
  • the current absorption timing determining circuit 26 Y is formed from a NAND gate circuit ND 2 and delay circuit 28 .
  • the current absorption timing determining circuit 26 Y almost simultaneously changes the write bit line sink signal WBLSNK to “H”.
  • the current absorption timing determining circuit 26 Y changes the write bit line sink signal WBLSNK to “L”.
  • the write signal WRITE is changed to “L” first.
  • the write bit line sink signal WBLSNK is changed to “L”.
  • FIG. 35 shows an example of the write bit line driver/sinker trigger circuit shown in FIG. 32 .
  • the write bit line driver/sinker trigger circuit 26 - 2 is formed from the current supply/cutoff timing determining circuit 26 X which determines the current supply/cutoff timing of the write current and a current absorption timing determining circuit 26 Y which determines the current absorption timing of the write current.
  • the current supply/cutoff timing determining circuit 26 X is formed from the plurality of (in this example, two) inverters IV 0 and IV 1 .
  • the current supply/cutoff timing determining circuit 26 X determines the timing to change the write bit line drive signal WBLDRV to “H” or “L” in accordance with the timing to change the write signal WRITE to “H” or “L”.
  • the current absorption timing determining circuit 26 Y is formed from the NAND gate circuit ND 2 and delay circuit 28 .
  • the current absorption timing determining circuit 26 Y almost simultaneously changes the write bit line sink signal WBLSNK to “H”.
  • the current absorption timing determining circuit 26 Y changes the write bit line sink signal WBLSNK to “L”.
  • the write signal WRITE is changed to “L” first.
  • the write bit line sink signal WBLSNK is changed to “L”.
  • FIG. 36 shows an example of the setting circuit 23 A shown in FIG. 30 .
  • the setting circuit 23 A has a MTJ element MTJ which stores setting data.
  • 1-bit data is stored on the basis of the presence/absence of breakdown of the tunneling barrier of the MTJ element MTJ. Note that 1-bit data may be stored in accordance with the magnetized state (parallel or antiparallel) of the MTJ element MTJ.
  • One terminal of the MTJ element MTJ is connected to the ground point VSS through an NMOS transistor N 2 .
  • the NMOS transistor N 2 is always ON because the power supply potential VDD is applied to the gate of the NMOS transistor N 2 .
  • the other terminal of the MTJ element MTJ is connected to the power supply potential VDD through an NMOS transistor N 1 and PMOS transistor P 1 .
  • the PMOS transistor P 1 is always ON because the ground potential VSS is applied to the gate of the PMOS transistor P 1 .
  • a clamp potential Vclamp is applied to the gate of the NMOS transistor N 1 .
  • the NMOS transistor N 1 whose gate receives the clamp potential Vclamp has a function of preventing any high voltage from being applied to the MTJ element MTJ (preventing breakdown of the MTJ element MTJ) in the is normal operation, i.e., when the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > are output from the setting circuit 23 A in the write operation.
  • a Vclamp generation circuit which generates the clamp potential Vclamp can be formed from the circuit as shown in FIG. 23 .
  • a NAND gate circuit ND 4 and PMOS transistor P 2 are used when setting data which determines the current waveform or the like of the write current is to be written in the MTJ element MTJ.
  • the setting data is stored in the MTJ element MTJ semipermanently on the basis of the presence/absence of breakdown of the tunneling barrier.
  • the PMOS transistor P 2 is turned on to apply a high voltage across the MTJ element MTJ.
  • the program signal PROG changes to “H” in writing setting data.
  • the program signal PROG can be supplied from the data input pin or address pin after assembly.
  • the program signal PROG may be supplied from a dedicated pin.
  • the value of the output signal from the NAND gate circuit ND 4 changes in accordance with the values of the input data D ⁇ 0 > to D ⁇ 3 > in the setting circuit 23 A in the row i.
  • the output signal from the NAND gate circuit ND 4 is “L”. For this reason, the PMOS transistor P 2 is turned on to break the tunneling barrier of the MTJ element MTJ, and “1” is stored in the MTJ element MTJ. In this case, the write word line current waveform signal WS ⁇ 0 > is “H”.
  • the output signal from the NAND gate circuit ND 4 is “H”. For this reason, the PMOS transistor P 2 is turned off. The tunneling barrier of the MTJ element MTJ is not broken, and “0” is stored in the MTJ element MTJ. In this case, the write word line current waveform signal WS ⁇ 0 > is “L”.
  • setting data can be written in the setting circuit 23 A in accordance with the input data D ⁇ 0 > to D ⁇ 3 >, and the values of the write word line current waveform signals WS ⁇ 0 > to WS ⁇ 3 > are determined.
  • FIG. 37 shows an example of the setting circuit 23 B- 1 shown in FIG. 31 .
  • FIG. 38 shows an example of the setting circuit 23 B- 2 shown in FIG. 32 .
  • the setting circuits 23 B- 1 and 23 B- 2 shown in FIGS. 37 and 38 have the same arrangement as that of the setting circuit 23 A in FIG. 36 described above.
  • Setting data is stored semipermanently on the basis of the presence/absence of breakdown of the tunneling barrier of the MTJ element MTJ.
  • the program signal PROG changes to “H” in writing setting data.
  • setting data should be written in the setting circuit 23 B- 1 or 23 B- 2 in the column i, all the bits of the address signal for selecting the column i change to “H”.
  • the value of the output signal from the NAND gate circuit ND 4 changes in accordance with the values of the input data D ⁇ 0 > to D ⁇ 7 > in the setting circuit 23 B- 1 or 23 B- 2 in the column i.
  • the output signal from the NAND gate circuit ND 4 is “L”. For this reason, the PMOS transistor P 2 is turned on to break the tunneling barrier of the MTJ element MTJ, and “1” is stored in the MTJ element MTJ.
  • the write bit line current waveform signal BS ⁇ 0 > is “H”.
  • the write bit line current waveform signal BS ⁇ 0 > is “L”.
  • the input data D ⁇ 0 > to D ⁇ 3 > determine the current waveform of the write bit line current in one direction
  • the input data D ⁇ 4 > to D ⁇ 7 > determine the current waveform of the write bit line current in the other direction opposite to one direction.
  • each write bit line when the write bit lines should have the same current waveform independently of the write data, i.e., the direction of the write bit line current, the setting circuit 23 B- 2 shown in FIG. 38 can be omitted.
  • both the write bit line drivers/sinkers 16 A- 1 and 17 A- 1 are controlled by the write bit line current waveform signals BS ⁇ 0 > to BS ⁇ 3 >.
  • the current waveform (magnitude) of the write current for the write word/bit line can be set for each write word line and each write bit line by programming.
  • the current waveform of the write current can be determined individually for each write data value (direction of the write current).
  • the setting circuits 23 A, 23 B- 1 , and 23 B- 2 shown in FIGS. 36 to 38 are prepared to be equal in number to the MTJ elements and selected by a row address signal and column address signal.
  • the circuit scheme can theoretically be implemented although the numbers of setting circuits 23 A, 23 B- 1 , and 23 B- 2 largely increase.
  • FIG. 39 shows the schematic arrangement of a magnetic random access memory having memory cell arrays stacked in a plurality of stages.
  • This example corresponds to a case wherein above-described circuit examples for “(1) Setting for Each Chip or Cell Array” are applied to the magnetic random access memory having memory cell arrays stacked in a plurality of stages.
  • Memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n are stacked in n (n is an integer: n ⁇ 2) stages on a semiconductor substrate (magnetic random access memory chip) 11 A.
  • Each of the memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n includes some peripheral circuits, e.g., a row decoder & write word line driver/sinker, column decoder & write bit line driver/sinker, and the like.
  • Input data is input to a selector 34 through a data input receiver 19 .
  • the selector 34 transfers the input data to a selected memory cell array 12 -i.
  • a demultiplexer may be used in place of the selector 34 .
  • Output data is transferred from a sense amplifier 20 of a corresponding one of the memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n to a data output driver 21 through a selector 35 .
  • the selector 35 transfers the output data from the sense amplifier 20 of the selected memory cell array 12 -i to the data output driver 21 .
  • a multiplexer may be used in place of the selector 35 .
  • a setting circuit 23 stores setting data which determines the current waveform of a write word/bit line current.
  • a write current waveform control circuit 24 actually determines the current waveform of the write word/bit line current on the basis of a write signal WRITE from the control circuit 22 and the setting data from the setting circuit 23 .
  • the current waveform may be common to all the memory cell arrays (the current waveform is set for each chip) or may be changed between the memory cell arrays (the current waveform is set for each memory cell array). In the latter case, for example, the setting circuit 23 and write current waveform control circuit 24 are arranged for each memory cell array.
  • FIG. 40 shows the schematic arrangement of a magnetic random access memory having memory cell arrays stacked in a plurality of stages.
  • This example corresponds to a case wherein above-described circuit examples for “(2) Setting for Each Write Word/Bit Line” are applied to the magnetic random access memory having memory cell arrays stacked in a plurality of stages.
  • the memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n are stacked in n (n is an integer: n ⁇ 2) stages on the semiconductor substrate (magnetic random access memory chip) 11 A.
  • Each of the memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n includes some peripheral circuits, e.g., a row decoder & write word line driver/sinker, column decoder & write bit line driver/sinker, and the like.
  • Input data is input to the selector 34 through the data input receiver 19 .
  • the selector 34 transfers the input data to the selected memory cell array 12 -i.
  • a demultiplexer may be used in place of the selector 34 .
  • Output data is transferred from the sense amplifier 20 of a corresponding one of the memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n to the data output driver 21 through the selector 35 .
  • the selector 35 transfers the output data from the sense amplifier 20 of the selected memory cell array 12 -i to the data output driver 21 .
  • a multiplexer may be used in place of the selector 35 .
  • the write signal WRITE from the control circuit 22 is supplied to the memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n.
  • Each of the memory cell arrays 12 - 1 , 12 - 2 , . . . , 12 -n has a write current waveform control circuit/setting circuit.
  • a setting circuit in the write current waveform control circuit/setting circuit stores setting data which determines the current waveform of a write word/bit line current.
  • the write current waveform control circuit/setting circuit actually determines the current waveform of the write word/bit line current on the basis of the write signal WRITE and setting data.
  • the write principles according to the embodiments of the present invention and circuit schemes which implement them can also be applied to a magnetic random access memory having memory cell arrays stacked in a plurality of stages.
  • the current waveform of the write current for the write word/bit line can be set for each write word/bit line by programming.
  • the magnetization of the storing layer of an MTJ element can reliably be inverted, and the write characteristics can be improved.
  • the write principles according to the present invention and the circuit schemes that implement them can be applied to even a magnetic random access memory having a cross-point cell array structure as shown in FIG. 43 or a magnetic random access memory having a cell array structure in which a read select switch (MOS transistor) is connected to one or a plurality of MTJ elements.
  • MOS transistor read select switch
  • the write principles according to the present invention and the circuit schemes that implement them can also be applied to a magnetic random access memory which is not of a cross-point type and has no read select switch, a magnetic random access memory having read bit lines and write bit lines separated from each other, or a magnetic random access memory which stores a plurality of bits in one MTJ element.
  • the current waveform of the write word/bit line current is determined for each chip, each memory cell array, or each word line/bit line.
  • the value of the write word line current and the value of the write bit line current are individually controlled to eliminate the influence of the variation.
  • the magnetizing direction of the storing layer of a MTJ element can reliably be reversed, the write characteristics and yield can be improved, and the manufacturing cost can be reduced.

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