US7366033B2 - 3-level non-volatile semiconductor memory device and method of driving the same - Google Patents

3-level non-volatile semiconductor memory device and method of driving the same Download PDF

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US7366033B2
US7366033B2 US11/460,580 US46058006A US7366033B2 US 7366033 B2 US7366033 B2 US 7366033B2 US 46058006 A US46058006 A US 46058006A US 7366033 B2 US7366033 B2 US 7366033B2
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latch
memory cell
data
threshold voltage
bit
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US20070025161A1 (en
Inventor
Ki-tae Park
Jung-Dal Choi
Sung-Kyu JO
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Definitions

  • This disclosure relates, in general, to semiconductor memory devices and, more particularly, to a non-volatile semiconductor memory device having 3-level memory cells, and methods of operating the non-volatile semiconductor memory device.
  • Non-volatile semiconductor memory devices preserve stored data when power is disconnected therefrom.
  • Various types of memory cells appropriate for non-volatile semiconductor memory devices have been known.
  • One such memory cell for a non-volatile semiconductor memory device is a single transistor type memory cell.
  • a transistor type memory cell MC in general, includes a source S and a drain D on a semiconductor substrate, a floating gate FG formed between a dielectric oxide film DOX and a gate oxide film GOX, and a control gate CG.
  • the floating gate FG traps electrons. The trapped electrons establish the threshold voltage of the memory cell MC.
  • the threshold voltage of the memory cell MC is detected, and detected data is stored therein.
  • program and erase operations may be repeatedly performed.
  • the various functions of single transistor memory cells MCs are determined by various types of applied voltage.
  • Such a single transistor memory cell MC is programmed as electrons move to the floating gate FG. Electrons may move to the floating gate FG by Fowler-Nordheim tunneling (FN) or electron injection.
  • the electron injection may be Channel Hot-Electron injection (CHE) or Channel-Initiated Secondary Electron Injection (CISEI).
  • FN is widely used in flash memory that erases data all at one time.
  • the transistor memory cell MC stores one of two values.
  • the two data values are stored by a threshold value that is set to one of two levels. For example, data are read as “1” when the threshold voltage of the memory cell MC is lower than a reference voltage VM, whereas data are read as “0” when the threshold voltage of the memory cell MC is higher than the reference voltage VM.
  • a 4-level memory cell As semiconductor memory devices have become highly integrated, a 4-level memory cell has been developed.
  • the 4-level memory cell as illustrated in FIG. 3 , may be programmed to one of four threshold voltage levels.
  • the 4-level memory cell can store one of four types of data. Therefore, a non-volatile semiconductor memory device having 4-level memory cells (hereinafter referred to as a ‘4-level non-volatile semiconductor memory device’) has data storage capacity two times that of a non-volatile semiconductor memory device having 2-level memory cells (hereinafter referred to as a ‘2-level non-volatile semiconductor memory device’).
  • the margin between the threshold voltage of neighboring levels is typically 0.67 V, which is very narrow.
  • the threshold voltage of each memory cell may shift due to the leakage of electrons, etc. Accordingly, the threshold voltage of the memory cell MC programmed to one of the 4 threshold levels may shift to a neighboring threshold voltage.
  • the 4-level non-volatile semiconductor memory device has the problem of low reliability.
  • the margin between the threshold voltages of neighboring levels is very narrow, and a program voltage applied to the control gate of the memory cell requires increments having very narrow intervals. Accordingly, the 4-level non-volatile semiconductor memory device has a problem in that the time required for programming is very long.
  • a non-volatile semiconductor memory device having 3-level memory cells (hereinafter referred to as a ‘3-level non-volatile semiconductor memory device’) have been proposed.
  • the 3-level memory cell MC as illustrated in FIG. 4 , has 3-level threshold voltage groups G 1 , G 2 and G 3 . In this case, two memory cells MC form a set and operate to store 3-bit data.
  • the 3-level memory cell has a larger number of storage states compared to the 2-level memory cell, thus having a relatively higher degree of integration. Furthermore, the 3-level memory cell has larger intervals between threshold voltage groups than does the 4-level memory cell. Thus, the 3-level memory cell has relatively higher reliability and the time required for programming is relatively reduced.
  • the existing 3-level non-volatile semiconductor memory device uses a method of reading a 3-level (G 1 , G 2 , G 3 ) state from each of the two memory cells MC 1 and MC 2 and converting read states into 3-bit (BIT 1 , BIT 2 and BIT 3 ) information as a basic operation. Therefore, the existing 3-level non-volatile semiconductor memory device, as illustrated in FIG. 6 , has a disadvantage in that it requires a 3-level code conversion circuit 40 between a page buffer 20 and a data Input/Output (I/O) line 30 , so that restrictions to layout increase.
  • I/O Input/Output
  • a 3-bit data value is determined by examining a 3-level state of each of the two memory cells at the time of a read operation. Accordingly, even in the case where a one-bit data value is determined, a total of four data fetch operations are required. As a result, the existing 3-level non-volatile semiconductor memory device has the disadvantage of overall low fetch speed.
  • An embodiment includes a page buffer for a non-volatile semiconductor memory device including a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
  • Another embodiment includes a method of programming a non-volatile semiconductor memory device including programming a first memory cell threshold voltage in response to a first data bit, programming one of the first memory cell threshold voltage and a second memory cell threshold voltage in response to a second data bit and the first memory cell threshold voltage, and programming one of the first memory cell threshold voltage and the second memory cell threshold voltage in response to a third data bit and the second memory cell threshold voltage.
  • Another embodiment includes a method of reading a non-volatile semiconductor memory including sensing a first memory cell threshold voltage with a first reference voltage, sensing a second memory cell threshold voltage with a second reference voltage, and generating a data bit in response to the sensing of the first memory cell threshold voltage and the second memory cell threshold voltage.
  • FIG. 1 is a cross sectional view showing a typical transistor type memory cell
  • FIG. 2 is a diagram illustrating the distribution of threshold voltages of a typical 2-level memory cell
  • FIG. 3 is a diagram illustrating the distribution of threshold voltages of a typical 4-level memory cell
  • FIG. 4 is a diagram illustrating the distribution of threshold voltages of a typical 3-level memory cell
  • FIG. 5 is a table of 3-bit data and associated threshold voltages in a conventional non-volatile semiconductor memory device
  • FIG. 6 is a block diagram showing part of the conventional non-volatile semiconductor memory device
  • FIG. 7 is a block diagram showing part of a non-volatile semiconductor memory device according to an embodiment
  • FIG. 8 is a block diagram showing part of the memory array of FIG. 7 , showing the memory array of a NAND-type non-volatile semiconductor memory device;
  • FIG. 9 is a circuit diagram showing the page buffer of FIG. 7 ;
  • FIGS. 10 and 11 are a flowchart and a data flow diagram, respectively, showing a first page programming in a programming method for the non-volatile semiconductor memory device according to an embodiment
  • FIG. 12 is a view showing variation in the threshold voltage of a memory cell after the first page programming has been performed in the programming method for the non-volatile semiconductor memory device according to an embodiment
  • FIGS. 13 a and 13 b are flowcharts showing a second page programming in the programming method for the non-volatile semiconductor memory device according to an embodiment
  • FIGS. 14 a and 14 b are data flow diagrams based on the flowcharts of FIGS. 13 a and 13 b;
  • FIG. 15 is a view showing variation in the threshold voltage of a memory cell after the second page programming has been performed in the programming method for the non-volatile semiconductor memory device according to an embodiment
  • FIGS. 16 a and 16 b are flowcharts showing a third page programming in the programming method for the non-volatile semiconductor memory device according to an embodiment
  • FIGS. 17 a and 17 b are data flow diagrams based on the flowcharts of FIGS. 16 a and 16 b;
  • FIG. 18 is a view showing variation in the threshold voltages of first and second memory cells after the third page programming has been performed in the programming method for the non-volatile semiconductor memory device according to an embodiment
  • FIG. 19 is a flowchart showing a first page reading step in the reading method for the non-volatile semiconductor memory device according to an embodiment.
  • FIGS. 20 a and 20 b are data flow diagrams based on the flowchart of FIG. 19 ;
  • FIG. 21 is a flowchart showing a second page reading in the reading method for the non-volatile semiconductor memory device according to an embodiment.
  • FIGS. 22 a and 22 b are data flow diagrams based on the flowchart of FIG. 21 ;
  • FIGS. 23 a and 23 b are flowcharts showing a third page reading in the reading method for the non-volatile semiconductor memory device according to an embodiment
  • FIGS. 24 a and 24 b are data flow diagrams based on the flowcharts of FIGS. 23 a and 23 b;
  • FIG. 25 is a diagram showing a page decoding method performed by a non-volatile semiconductor device according to an embodiment
  • FIG. 26 is a flowchart showing an embodiment of a programming operation performed by a non-volatile semiconductor memory device
  • FIG. 27 is a flowchart showing an embodiment of a read operation performed by a non-volatile semiconductor memory device.
  • FIG. 28 is a diagram showing part of the memory array of FIG. 7 according to another embodiment.
  • FIG. 29 is a diagram showing part of the memory array of FIG. 7 according to another embodiment, which shows the memory array of a NOR-type non-volatile semiconductor memory device.
  • FIG. 30 is a diagram showing part of the memory array of FIG. 7 according to another embodiment, which shows the memory array of an OR-type non-volatile semiconductor memory device.
  • 3-level memory cells are included.
  • a 3-level memory cell (MC) has three threshold voltage groups.
  • the threshold voltage groups of the memory cells MCs may be classified based on a first reference voltage VR 1 and a second reference voltage VR 2 .
  • a threshold voltage group having threshold voltages lower than the first reference voltage VR 1 may be designated as a “first threshold voltage group G 1 ”
  • a threshold voltage group having threshold voltages between the first reference voltage VR 1 and the second reference voltage VR 2 may be designated as a “second threshold voltage group G 2 .”
  • a threshold voltage group having threshold voltages higher than the second reference voltage VR 2 may be designated as a “third threshold voltage group G 3 .”
  • the first reference voltage VR 1 and the second reference voltage VR 2 may be set to different levels in a verify read operation of verifying whether programming has succeeded, and in a normal read operation of reading stored data, respectively.
  • each of the first reference voltage VR 1 and the second reference voltage VR 2 does not vary in the verify read operation and in the normal read operation.
  • Such reference voltages may vary as described above.
  • FIG. 7 is a block diagram showing part of a non-volatile semiconductor memory device according to an embodiment.
  • a memory array 100 a page buffer 200 , and a row decoder 300 are shown.
  • FIG. 8 is a block diagram showing part of the memory array 100 of FIG. 7 , showing the memory array of a NAND-type non-volatile semiconductor memory device.
  • the memory array 100 includes memory cells MC arranged in a matrix structure of rows and columns.
  • the memory array 100 includes a first cell string ST 1 and a second cell string ST 2 .
  • the first cell string ST 1 is coupled to a first bitline
  • the second cell string ST 1 is coupled to a second bitline.
  • the first cell string ST 1 includes a plurality of the first memory cells MC 1 s
  • the second cell string ST 1 includes a plurality of the second memory cells MC 2 s .
  • the first and the second memory cells MC 1 and MC 2 may be electrically programmable and erasable, and retain data even if power is not supplied.
  • One of the first memory cells MC 1 s and one of the second memory cells MC 2 s may form a pair.
  • first to third bit data forming a single group may be programmed. Further, storage states according to the threshold voltage of the pair of memory cells MC 1 and MC 2 may be read as the first to third bit data.
  • first to third bit data may be referred to by reference characters “BIT 1 to BIT 3 .”
  • the first and second memory cells MC 1 and MC 2 are located in the first cell string ST 1 and the second cell string ST 2 , respectively.
  • the page buffer 200 is coupled to the memory array through the first and the second bitlines BL 1 and BL 2 .
  • the page buffer 200 is driven to map the first to third bit data BIT 1 to BIT 3 , forming a group, to the threshold voltage groups of the pair of first and second memory cells MC 1 and MC 2 .
  • FIG. 9 is a circuit diagram showing the page buffer 200 of FIG. 7 in detail.
  • the page buffer 200 includes a switch SW, a first latch block LTBK 1 and a second latch block LTBK 2 .
  • the switch may be controlled to connect the first bitline BL 1 to second bitline BL 2 , in response to a switch control signal SWC.
  • the first latch block LTBK 1 can store first latch data DLT 1 . Further, the first latch block LTBK 1 can transfer/receive data to/from the memory array 100 , via the first bitline BL 1 .
  • the first buffer block LTBK 1 includes a sensing node NSEN, a first latch unit 210 , a first flop unit 220 and an inverting flop unit 230 .
  • the sensing node NSEN is connected to the first bitline BL 1 in response to a first bitline connection signal. Then, the data on the sensing node NSEN can be provided through a bitline blocking element 240 .
  • the first latch unit 210 latches and stores the first latch data DLT 1 .
  • the first latch unit 210 maps the first latch data DLT 1 to the first bitline BL 1 in response to a first bitline selection signal BLSLT 1 .
  • the first flop unit 220 may change the first latch data DLT 1 to a logic H state depending on the voltage level of the sensing node NSEN or the second latch data DLT 2 of the second buffer block LTBK 2 .
  • a logic L state and a logic H state may be designated as a “first logic state” and a “second logic state,” respectively.
  • the first flop unit 220 includes, in detail, a transmission unit 221 and a flop circuit 223 .
  • the transmission unit 221 is enabled in response to a transmission control signal TR.
  • the transmission unit 221 flops the first latch data DLT 1 from a logic L state to a logic H state depending on the second latch data DLT 2 of the second buffer block LTBK 2 .
  • the flop circuit 223 is enabled in response to a first latch control signal LCH 1 .
  • the flop circuit 223 performs a control operation so that the first latch data DLT 1 , latched in the first latch unit 210 , is set to a logic H state depending on the voltage level of the sensing node NSEN.
  • the inverting flop unit 230 may change the first latch data DLT 1 , latched in the first latch unit 210 , to a logic L state depending on the voltage level of the sensing node NSEN and the second latch data DLT 2 of the second buffer block LTBK 2 .
  • the inverting flop unit 230 performs a control operation so that the first latch data DLT 1 may change depending on the voltage level of the sensing node NSEN. For example, when the logic state of the second latch data DLT 2 , latched in the second latch block LTBK 2 , is logic L, the inverting flop unit 230 does not change the first latch data DLT 1 to a logic L state.
  • the first buffer block LTBK 1 further includes a first input/output unit 250 .
  • the first input/output unit 250 may load the first latch data DLT 1 of the first latch unit 210 or may provide the first latch data DLT 1 to an internal data line IDL.
  • a sensing precharge block 201 precharges the sensing node NSEN with a power voltage VDD in response to a sensing precharge signal /PRE.
  • the second latch block LTBK 2 can store second latch data DLT 2 . Further, the second latch block LTBK 2 can transfer/receive data to/from the memory array 100 through the second bitline BL 2 .
  • the second buffer block LTBK 2 includes a second latch unit 260 and a second flop unit 270 .
  • the second latch unit 260 latches and stores the second latch data DLT 2 . Further, the second latch unit 260 can transfer/receive the second latch data DLT 2 to the second bitline BL 2 in response to a second bitline selection signal BLSLT 2 .
  • the second flop unit 270 may change the second latch data DLT 2 to a logic H state depending on the voltage level of the sensing node NSEN.
  • the second flop unit 270 is enabled in response to a second latch control signal LCH 2 .
  • the second flop unit 270 performs a control operation so that the second latch data DLT 2 , latched in the second latch unit 260 , changes to a logic H state depending on the voltage level of the sensing node NSEN.
  • the row decoder 300 is coupled to the memory array 100 to control the voltage level of a selected word line WL.
  • the row decoder 300 activates a selected word line WL according to row addresses XADD.
  • the row decoder 300 provides a string selection signal SSL and a ground selection signal GSL.
  • the data input/output circuit 700 outputs data, latched in the page buffer 200 , to an external system, and loads data input from the external system on the page buffer 200 .
  • the non-volatile semiconductor memory device of FIG. 7 also includes a page identification circuit 500 and a control signal generation circuit 600 .
  • the page identification circuit 500 receives the row address XADD, and provides page information PGIF to the control signal generation circuit 600 .
  • the page information PGIF includes information indicating which page among first to third pages corresponds to the received row address XADD.
  • the control signal generation circuit 600 determines a programming operation, a read operation, etc. in response to an operation command CMD and the page information PGIF, and provides control signals based on the determined operation to the page buffer 200 , the row decoder 300 and the data I/O circuit 400 .
  • a data value on the internal data line IDL is assumed to be equal to that of each of first to third bit data BIT 1 to BIT 3 , which are provided outside of the page buffer at the time of performing a program or read operation. That is, it is assumed that, when each bit data value is “1,” the logic level of the internal data line IDL is logic H, while when each bit data value is “0.” the logic level of the internal data line IDL is logic L.
  • a 3-level code conversion circuit is not required between a page buffer and a data I/O line.
  • restrictions to layout are significantly reduced.
  • the programming of a pair of memory cells is performed in the sequence of first to third page programming steps that respectively use first to third bit data BIT 1 to BIT 3 .
  • FIGS. 10 and 11 are a flowchart and a data flow diagram, respectively, showing a first page programming in and embodiment of a programming method for the non-volatile semiconductor memory device.
  • the threshold voltage of the first memory cell MC 1 is programmed to the second threshold voltage group G 2 depending on the first bit data BIT 1 .
  • the first latch data DLT 1 is reset to a logic H state.
  • the first bit data BIT 1 is loaded as the first latch data DLT 1 through an internal data line IDL (refer to A 1 of FIG. 11 ). That is, when the first bit data BIT 1 is “0,” the first latch data DLT 1 is latched as a logic L state. In contrast, when the first bit data BIT 1 is “1,” the first latch data DLT 1 is maintained at a logic H state.
  • the programming of the first memory cell MC 1 is performed using the first latch data DLT 1 (refer to A 2 of FIG. 11 ). That is, if the first bit data BIT 1 is “0,” the threshold voltage of the first memory cell MC 1 increases, while if the first bit data BIT 1 is “1,” the threshold voltage of the first memory cell MC 1 is maintained at its previous state.
  • the threshold voltage of the first memory cell MC 1 is reflected on the sensing node NSEN, based on the first reference voltage VR 1 (refer to A 3 of FIG. 11 ). That is, whether the threshold voltage of the first memory cell MC 1 is higher than the first reference voltage VR 1 is reflected on the sensing node NSEN. For example, if the threshold voltage of the first memory cell MC 1 is higher than the first reference voltage VR 1 , the voltage level of the sensing node NSEN is adjusted to the supply voltage VDD. In contrast, if the threshold voltage of the first memory cell MC 1 is lower than the first reference voltage VR 1 , the voltage level of the sensing node NSEN is adjusted to the ground voltage VSS.
  • the first latch control signal LCH 1 is generated as an H pulse.
  • the first latch data DLT 1 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to A 4 of FIG. 11 ). In other words, if the voltage level of the sensing node NSEN is the supply voltage VDD, the first latch data DLT 1 is set to a logic H state. In contrast, if the voltage level of the sensing node NSEN is adjusted to the ground voltage VSS, the first latch data DLT 1 is maintained at its previous data state.
  • the fact that the first latch data DLT 1 is in a logic L state after S 1150 has been performed means that, although the programming of the first memory cell MC 1 is performed, the threshold voltage of the first memory cell MC 1 was not adjusted to the target of the first or second threshold voltage group G 1 or G 2 according to the first data bit BIT 1 .
  • a first data line control signal DIO 1 is generated as an H pulse, so that the logic state of the first latch data DLT 1 is read out (refer to A 5 of FIG. 11 ).
  • whether programming has succeeded is verified.
  • the logic H state of data read at S 1160 indicates that programming has succeeded.
  • the logic L state of the data read at S 1160 indicates that programming has failed.
  • FIG. 12 is a view showing variation in the threshold voltages of the first and second memory cells MC 1 and MC 2 after the first page programming has been performed in the programming method for the non-volatile semiconductor memory device according to an embodiment.
  • the threshold voltage of the first memory cell MC 1 is adjusted to the second threshold voltage group G 2 , and the threshold voltage of the second memory cell MC 2 is maintained at the first threshold voltage group G 1 .
  • FIGS. 13 a and 13 b are flowcharts showing a second page programming in the programming method for the non-volatile semiconductor memory device according to an embodiment. Further, FIGS. 14 a and 14 b are data flow diagrams based on the flowcharts of FIGS. 13 a and 13 b .
  • the threshold voltage of the first memory cell MC 1 or the second memory cell MC 2 is programmed to the third threshold voltage group G 3 depending on the second bit data BIT 2 , and the threshold voltage of the first memory cell MC 1 .
  • the first and second latch data DLT 1 and DLT 2 are reset to a logic H state.
  • a data loading step of controlling the first and second latch data DLT 1 and DLT 2 using the second bit data BIT 2 through the internal data line IDL is performed (refer to B 1 of FIG. 14 a ). That is, when the second bit data BIT 2 is “0,” the first and second latch data DLT 1 and DLT 2 are latched as a logic L state. In contrast, when the second bit data BIT 2 is “1,” the first and second latch data DLT 1 and DLT 2 are maintained at a logic H state.
  • the data of the first memory cell MC 1 is reflected on the sensing node NSEN, based on the first reference voltage VR 1 (refer to B 2 of FIG. 14 a ).
  • the second latch data DLT 2 is controlled using the voltage level of the sensing node NSEN obtained at S 1215 (refer to B 3 of FIG. 14 a ). Consequently, if the first bit data BIT 1 is “0,” the sensing node NSEN is a logic H state and the second latch data DLT 2 changes to a logic H state. In contrast, if the first bit data BIT 1 is “1,” the sensing node NSEN is a logic L state and the second latch data DLT 2 is maintained at its current state.
  • the transmission control signal TR is activated to a logic H state. Therefore, at S 1225 , the first latch data DLT 1 is selectively set to a logic H state in response to the second latch data DLT 2 (refer to B 4 and B 4 ′ of FIG. 14 a ). That is, if the second latch data DLT 2 is currently the first latch data DLT 1 is maintained at its previous state. In contrast, if the second latch data DLT 2 is “0,” the first latch data DLT 1 changes to a logic H state.
  • the first and second latch data DLT 1 and DLT 2 are logic H regardless of the value of the first bit data BIT 1 .
  • the first latch data DLT 1 is logic L and the second latch data DLT 2 is logic H.
  • the first latch data DLT 1 is logic H
  • the second latch data DLT 2 is logic L.
  • the threshold voltage of the first or second memory cell MC 1 or MC 2 is adjusted to the third threshold voltage group G 3 .
  • the threshold voltage of the first memory cell MC 1 is adjusted to the third threshold voltage group G 3 .
  • the threshold voltage of the second memory cell MC 2 is adjusted to the third threshold voltage group G 3 .
  • the threshold voltage of the first memory cell MC 1 is adjusted to the third threshold voltage group G 3 at the second page programming.
  • the threshold voltage of the second memory cell MC 2 is adjusted to the third threshold voltage group G 3 at the second page programming in response to the second bit data BIT 2 .
  • the threshold voltage of the first memory cell MC 1 is reflected on the sensing node NSEN, based on the second reference voltage VR 2 (refer to B 6 of FIG. 14 b ). That is, whether the threshold voltage of the first memory cell MC 1 is higher than the second reference voltage VR 2 is reflected on the sensing node NSEN.
  • the first latch control signal LCH 1 is generated as an H pulse.
  • the first latch data DLT 1 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to B 7 of FIG. 14 b ).
  • the threshold voltage of the second memory cell MC 2 is reflected on the sensing node NSEN, based on the second reference voltage VR 2 (refer to B 8 of FIG. 14 b ). That is, whether the threshold voltage of the second memory cell MC 2 is higher than the second reference voltage VR 2 is reflected on the sensing node NSEN.
  • the second latch control signal LCH 2 is generated as an H pulse.
  • the second latch data DLT 2 selectively flops from a logic L state to a logic H state depending on the voltage level of the sensing node NSEN (refer to B 9 of FIG. 14 b ).
  • a first data line control signal DIO 1 and a second data line control signal DIO 2 are simultaneously or sequentially generated as H pulses, and the logic states of the first and second latch data DLT 1 and DLT 2 are read out (refer to B 10 of FIG. 14 b ).
  • whether programming has succeeded is verified.
  • a circuit capable of verifying that programming has succeeded if the threshold voltage of any one of the first and second memory cells MC 1 and MC 2 is adjusted to the third threshold voltage group G 3 , may be used as a program verify circuit for verifying whether programming has succeeded at S 1260 . Further, it is also apparent to those skilled in the art that such a program verify circuit may be implemented in various forms.
  • S 1230 and onward are repeated. At this time, at S 1230 , the voltage level of a selected word line or bit line gradually increases.
  • FIG. 15 is a view showing variation in the threshold voltages of the first and second memory cells MC 1 and MC 2 after the second page programming step has been performed in the programming method for the non-volatile semiconductor memory device according to an embodiment.
  • both the first and second bit data BIT 1 and BIT 2 are “1” (CASE 21 )
  • the threshold voltages of the first and second memory cells MC 1 and MC 2 are maintained at an erase state, that is, at the first threshold voltage group G 1 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the first threshold voltage group G 1 , and the threshold voltage of the second memory cell MC 2 is adjusted to the third threshold voltage group G 3 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the second threshold voltage group G 2
  • the threshold voltage of the second memory cell MC 2 is maintained at the first threshold voltage group G 1 .
  • the threshold voltage of the first memory cell MC 1 is adjusted to the third threshold voltage group G 3 , and the threshold voltage of the second memory cell MC 2 is maintained at the first threshold voltage group G 1 .
  • FIGS. 16 a and 16 b are flowcharts showing a third page programming in the programming method for the non-volatile semiconductor memory device according to an embodiment.
  • FIGS. 17 a and 17 b are data flow diagrams based on the flowcharts of FIGS. 16 a and 16 b .
  • the threshold voltage of the first or second memory cell MC 1 or MC 2 is programmed to the second threshold voltage group G 2 depending on the third bit data BIT 3 .
  • first and second latch data DLT 1 and DLT 2 are reset to a logic H state.
  • the first and second latch data DLT 1 and DLT 2 are loaded with the third bit data BIT 3 through the internal data line IDL, (refer to C 1 of FIG. 17 a ). That is, when the third bit data BIT 3 is “0,” the first and second latch data DLT 1 and DLT 2 are latched as a logic L state. In contrast, when the third bit data BIT 3 is “1,” the first and second latch data DLT 1 and DLT 2 are maintained at a logic H state.
  • the second latch data DLT 2 is controlled using the data programmed in the second memory cell MC 2 at the second page programming.
  • the data of the second memory cell MC 2 is reflected on the sensing node NSEN, based on the second reference voltage VR 2 (refer to C 2 of FIG. 17 a ).
  • the second latch data DLT 2 is selectively changed using the voltage level of the sensing node NSEN obtained at step S 1315 (refer to C 3 of FIG. 17 a ). Consequently, when the first bit data BIT 1 is “1”, and the second bit data BIT 2 is “0,” the second latch data DLT 2 flops to a logic H state. In contrast, in the remaining cases except for the case where the first bit data BIT 1 is “1,” and the second bit data BIT 2 is “0,” the second latch data DLT 2 is maintained at its previous state.
  • the transmission control signal TR is activated to a logic H state. Therefore, at S 1325 , the first latch data DLT 1 is selectively changed using the second latch data DLT 2 (refer to C 4 and C 4 ′ of FIG. 17 a ). That is, when the first bit data BIT 1 is “1” and the second bit data BIT 2 is “0,” the first latch data DLT 1 is maintained at its previous state.
  • the first latch data DLT 1 and the second latch data DLT 2 are logic H regardless of the values of the first and second bit data BIT 1 and BIT 2 .
  • the first latch data DLT 1 is logic H
  • the second latch data DLT 2 is logic L.
  • the first latch data DLT 1 is logic L
  • the second latch data DLT 2 is logic H.
  • first bit data BIT 1 is “0”
  • second bit data BIT 2 is “1”
  • third bit data BIT 3 is “0”
  • the first latch data DLT 1 is logic H
  • the second latch data DLT 2 is logic L.
  • the first latch data DLT 1 is logic H and the second latch data DLT 2 is logic L.
  • the threshold voltage of the first memory cell MC 1 or the second memory cell MC 2 is adjusted to the second threshold voltage group G 2 .
  • the threshold voltage of the first memory cell MC 1 is adjusted to the second threshold voltage group G 2 .
  • the threshold voltage of the second memory cell MC 2 is adjusted to the second threshold voltage group G 2 .
  • the threshold voltage of the second memory cell MC 2 when the threshold voltage of the second memory cell MC 2 has been adjusted to the third threshold voltage group G 3 as a result of the second page programming, the threshold voltage of the first memory cell MC 1 is adjusted to the second threshold voltage group G 2 at the third page programming in response to the third data bit BIT 3 .
  • the threshold voltage of the second memory cell MC 2 when the threshold voltage of the second memory cell MC 2 has been maintained at the first threshold voltage group G 1 as a result of the second page programming step, the threshold voltage of the second memory cell MC 2 is adjusted to the second threshold voltage group G 2 at the third page programming in response to the third data bit BIT 3 .
  • the threshold voltage of the first memory cell MC 1 is reflected on the sensing node NSEN, based on the first reference voltage VR 1 (refer to C 6 of FIG. 17 b ).
  • the first latch control signal LCH 1 is generated as an H pulse.
  • the first latch data DLT 1 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to C 7 of FIG. 17 b ).
  • the threshold voltage of the second memory cell MC 2 is reflected on the sensing node NSEN, based on the first reference voltage VR 1 (refer to C 8 of FIG. 17 b ).
  • the second latch control signal LCH 2 is generated as an H pulse.
  • the second latch data DLT 2 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to C 9 of FIG. 17 b ).
  • the first data line control signal DIO 1 and the second data line control signal D 102 are simultaneously or sequentially generated as H pulses, so that the logic states of the first and second latch data DLT 1 and DLT 2 are read out (refer to B 10 of FIG. 17 b ).
  • step S 1360 whether programming has succeeded is verified.
  • FIG. 18 is a view showing variation in the threshold voltages of first and second memory cells MC 1 and MC 2 after the third page programming step has been performed in the programming method for the non-volatile semiconductor memory device according to an embodiment.
  • the threshold voltages of the first and second memory cells MC 1 and MC 2 are maintained at an erase state, that is, at the first threshold voltage group G 1 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the first threshold voltage group G 1 , and the threshold voltage of the second memory cell MC 2 is adjusted to the second threshold voltage group G 2 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the first threshold voltage group G 1
  • the threshold voltage of the second memory cell MC 2 is maintained at the third threshold voltage group G 3 .
  • the threshold voltage of the first memory cell MC 1 is adjusted to the second threshold voltage group G 2 , and the threshold voltage of the second memory cell MC 2 is maintained at the third threshold voltage group G 3 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the second threshold voltage group G 2
  • the threshold voltage of the second memory cell MC 2 is maintained at the first threshold voltage group G 1 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the second threshold voltage group G 2
  • the threshold voltage of the second memory cell MC 2 is adjusted to the second threshold voltage group G 2 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the third threshold voltage group G 3
  • the threshold voltage of the second memory cell MC 2 is maintained at the first threshold voltage group G 1 .
  • the threshold voltage of the first memory cell MC 1 is maintained at the third threshold voltage group G 3 , and the threshold voltage of the second memory cell MC 2 is adjusted to the second threshold voltage group G 2 .
  • the threshold voltages of the first and second memory cells MC 1 and MC 2 may be simultaneously controlled depending on the three sequentially provided bit data BIT 1 , BIT 2 and BIT 3 . Further, whether programming has succeeded can be verified through only one or two verify read operations for each bit data value.
  • the overall operating speed is very high.
  • FIG. 19 is a flowchart showing a first page reading in the reading method for the non-volatile semiconductor memory device according to an embodiment.
  • FIGS. 20 a and 20 b are data flow diagrams based on the flowchart of FIG. 19 .
  • the first memory cell MC 1 of a first threshold voltage group G 1 and the second memory cell MC 2 of a third threshold voltage group G 3 are verified, so that the first bit data BIT 1 is read.
  • first and second latch data DLT 1 and DLT 2 are set to a logic L state (refer to D 1 of FIG. 20 a ).
  • a data fetching controlling the second latch data DLT 2 is performed, using data depending on the threshold voltage of the first memory cell MC 1 which is verified based on a first reference voltage VR 1 .
  • the threshold voltage of the first memory cell MC 1 is reflected on the sensing node NSEN, based on the first reference voltage VR 1 (refer to D 2 of FIG. 20 a ).
  • a second latch control signal LCH 2 is generated as an H pulse.
  • the second latch data DLT 2 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to D 3 of FIG. 20 a ).
  • a transmission control signal TR is activated to a logic H state. Therefore, at S 1440 , the first latch data DLT 1 , is selectively controlled by the second latch data DLT 2 at S 1430 , is performed (refer to D 4 and D 4 ′ of FIG. 20 a ).
  • the logic state of the first latch data DLT 1 after step S 1440 has been performed is described. That is, when the threshold voltage of the first memory cell MC 1 belongs to the first threshold voltage group G 1 (CASE 31 , CASE 32 and CASE 33 of FIG. 20 ), the first latch data DLT 1 is adjusted to a logic H state from a logic L state. In contrast, when the threshold voltage of the first memory cell MC 1 belongs to the second or third threshold voltage group G 2 or G 3 (CASE 34 to CASE 38 of FIG. 18 ), the first latch data DLT 1 is maintained at a logic L state.
  • the first latch data DLT 1 is selectively changed using data depending on the threshold voltage of the second memory cell MC 2 which is verified based on a second reference voltage VR 2 .
  • the threshold voltage of the second memory cell MC 2 is reflected on the sensing node NSEN, based on the second reference voltage VR 2 (refer to D 5 of FIG. 20 b ).
  • a first latch control signal LCH 1 is generated as an H pulse.
  • the first latch data DLT 1 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to D 6 of FIG. 20 b ).
  • the first latch data DLT 1 is adjusted to a logic H state from a logic L state. In contrast, in the remaining cases, the first latch data DLT 1 is maintained at its previous state.
  • output data having a logic H state indicates that the first bit data BIT 1 is “1” while output data having a logic L state indicates that the first bit data BIT 1 is “0.”
  • the first bit data BIT 1 can be read through a single read operation.
  • FIG. 21 is a flowchart showing a second page reading in the reading method for the non-volatile semiconductor memory device according to an embodiment.
  • FIGS. 22 a and 22 b are data flow diagrams based on the flowchart of FIG. 21 .
  • the first or second memory cell MC 1 or MC 2 of the third threshold voltage group G 3 is verified, so that the second bit data BIT 2 is read.
  • the first and second latch data DLT 1 and DLT 2 are set to a logic L state is performed (refer to E 1 of FIG. 22 a ).
  • the second latch data DLT 2 is controlled, using data depending on the threshold voltage of the second memory cell MC 2 , verified based on the second reference voltage VR 2 .
  • the threshold voltage of the second memory cell MC 2 is reflected on the sensing node NSEN, based on the second reference voltage VR 2 (refer to E 2 of FIG. 22 a ).
  • the second latch control signal LCH 2 is generated as an H pulse.
  • the second latch data DLT 2 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to E 3 of FIG. 22 a ).
  • the logic state of the second latch data DLT 2 after S 1530 has been performed is described below. That is, when the threshold voltage of the second memory cell MC 2 belongs to the third threshold voltage group G 3 (CASE 33 and CASE 34 of FIG. 18 ), the second latch data DLT 2 is adjusted to a logic H state from a logic L state. In contrast, in the remaining cases (CASE 31 , CASE 32 , and CASE 35 to CASE 38 of FIG. 18 ), the second latch data DLT 2 is maintained at a logic L state.
  • the second latch data DLT 2 is controlled, using data depending on the threshold voltage of the first memory cell MC 1 which is verified based on the second reference voltage VR 2 .
  • the threshold voltage of the first memory cell MC 1 is reflected on the sensing node NSEN, based on the second reference voltage VR 2 (refer to E 4 of FIG. 22 b ).
  • the second latch control signal LCH 2 is generated as an H pulse.
  • the second latch data DLT 2 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to E 5 of FIG. 22 b ).
  • the logic state of the second latch data DLT 2 after S 1550 has been performed is described below. That is, when the threshold voltage of the first memory cell MC 1 belongs to the third threshold voltage group G 3 (CASE 37 and CASE 38 of FIG. 18 ), the second latch data DLT 2 is adjusted to a logic H state. In contrast, in the remaining cases (CASE 31 to CASE 36 of FIG. 18 ), the second latch data DLT 2 is maintained at its previous logic state.
  • the transmission control signal TR is activated to a logic H state. Therefore, at S 1560 , the first latch data DLT 1 , set at step S 1510 is controlled, using the second latch data DLT 2 at S 1530 and S 1550 , (refer to E 6 and E 6 ′ of FIG. 22 b ).
  • the logic state of the first latch data DLT 1 after S 1560 has been performed is described below. That is, when the threshold voltage of the first memory cell MC 1 or the second memory cell MC 2 belongs to the third threshold voltage group G 3 (CASE 33 , CASE 34 , CASE 37 and CASE 38 of FIG. 18 ), the first latch data DLT 1 is adjusted to a logic H state from a logic L state. In contrast, in the remaining cases (CASE 31 , CASE 32 , CASE 35 and CASE 36 of FIG. 18 ), the first latch data DLT 1 is maintained at a logic L state.
  • the first data line control signal D 100 is generated as an H pulse, reading out the logic state of the first latch data DLT 1 , and verifying the second bit data BIT 2 , (refer to E 7 of FIG. 22 b ).
  • output data having a logic H state indicates that the second bit data BIT 2 is “1,” and output data having a logic L state indicates that the second bit data BIT 2 is “0.”
  • the value of the second bit data BIT 2 can be read through a single read operation.
  • FIGS. 23 a and 23 b are flowcharts showing a third page reading in the reading method for the non-volatile semiconductor memory device according to an embodiment.
  • FIGS. 24 a and 24 b are data flow diagrams based on the flowcharts of FIGS. 23 a and 23 b .
  • the third page reading step the second memory cell MC 2 of the first threshold voltage group G 1 or the third threshold voltage group G 3 is verified, and the first memory cell MC 1 of the second threshold voltage group G 2 is excluded, so that the third bit data B 113 is read.
  • step S 1610 a setting the first and second latch data DLT 1 and DLT 2 are set to a logic L state is performed (refer to F 1 of FIG. 24 a ).
  • the second latch data DLT 2 is controlled, using data depending on the threshold voltage of the second memory cell MC 2 which is verified based on the first reference voltage VR 1 .
  • the threshold voltage of the second memory cell MC 2 is reflected on the sensing node NSEN, based on the first reference voltage VR 1 (refer to F 2 of FIG. 24 a ).
  • the second latch control signal LCH 2 is generated as an H pulse.
  • the second latch data DLT 2 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to F 3 of FIG. 24 a ).
  • the transmission control signal TR is activated to a logic H state. Therefore, at S 1640 , the first latch data DLT 1 , set at step S 1610 is controlled, using the second latch data DLT 2 obtained at S 1630 (refer to F 4 and F 4 ′ of FIG. 24 a ).
  • the logic state of the first latch data DLT 1 after S 1640 has been performed is described below. That is, when the threshold voltage of the second memory cell MC 2 belongs to the first threshold voltage group G 1 (CASE 31 , CASE 35 , and CASE 37 of FIG. 18 ), the first latch data DLT 1 is adjusted to a logic H state from a logic L state. In contrast, when the threshold voltage of the first memory cell MC 1 belongs to the second or third threshold voltage group G 2 or G 3 (CASE 32 , CASE 33 , CASE 34 , CASE 36 and CASE 38 of FIG. 18 ), the first latch data DLT 1 is maintained at a logic L state.
  • the first latch data DLT 1 is selectively changed using data depending on the threshold voltage of the second memory cell MC 2 which is verified based on the second reference voltage VR 2 .
  • the threshold voltage of the second memory cell MC 2 is reflected on the sensing node NSEN, based on the second reference voltage VR 2 (refer to F 5 of FIG. 24 b ).
  • the first latch control signal LCH 1 is generated as an H pulse.
  • the first latch data DLT 1 selectively changes to a logic H state depending on the voltage level of the sensing node NSEN (refer to F 6 of FIG. 24 b ).
  • the threshold voltage of the second memory cell MC 2 belongs to the third threshold voltage group G 3 (CASE 33 and CASE 34 of FIG. 18 )
  • the first latch data DLT 1 is adjusted to a logic H state from a logic L state.
  • the first latch data DLT 1 is maintained at its previous logic state.
  • the threshold voltage of the second memory cell MC 2 belongs to the first threshold voltage group G 1 or the third threshold voltage group G 3 (CASE 31 , CASE 35 , CASE 37 , CASE 33 and CASE 34 of FIG. 18 )
  • the first latch data DLT 1 is adjusted to a logic H state from a logic L state.
  • the remaining cases CASE 32 , CASE 36 and CASE 38 of FIG. 18
  • the first latch data DLT 1 is maintained at a logic L state.
  • the first latch data DLT 1 is selectively changed using data depending on the threshold voltage of the first memory cell MC 1 which is verified based on the first reference voltage VR 1 , is performed.
  • the inverting flop of the first latch data DLT 1 is enabled in response to the second latch data DLT 2 flopped at S 1630 .
  • the threshold voltage of the first memory cell MC 1 is reflected on the sensing node NSEN, based on the first reference voltage VR 1 (refer to F 7 of FIG. 24 b ).
  • an inverting latch signal IVLCH is generated as an H pulse.
  • the first latch data DLT 1 selectively changes to a logic L state depending on the voltage level of the sensing node NSEN and the second latch data DLT 2 (refer to F 8 and F 8 ′ of FIG. 24 b ).
  • the first latch data DLT 1 selectively inversely flops from a logic H state to a logic L state depending on the voltage level of the sensing node NSEN. At this time, the inverting flop of the first latch data DLT 1 can be performed only when the second latch data DLT 2 is a logic H state.
  • the inverting flop of the first latch data DLT 1 from a logic H state to a logic L state occurs only when the threshold voltage of the first memory cell MC 1 belongs to the second threshold voltage group G 2 and the threshold voltage of the second memory cell MC 2 belongs to the third threshold voltage group G 3 (CASE 34 of FIG. 18 ).
  • the logic state of the first latch data DLT 1 after step S 1680 has been performed is described below.
  • the logic state of the first latch data DLT 1 is logic H.
  • the logic state of the first latch data DLT 1 is logic L.
  • the first data line control signal DIO 1 is generated as an H pulse, reading out the logic state of the first latch data DLT 1 , and verifying the third bit data BIT 3 , (refer to F 9 of FIG. 24 b ).
  • the third bit data BIT 3 can be read through a single read operation.
  • each of the first to third bit data BIT 1 to BIT 3 can be read without reading the other two bits. Therefore, the overall operating speed is very high.
  • FIG. 25 is a diagram showing a page decoding method performed by a non-volatile semiconductor memory device according to an embodiment.
  • each of a first string ST 1 and a second string ST 2 includes 22 memory cells.
  • 20 memory cells are memory cells MC 1 b or MC 2 b , programmable to three levels, and the remaining two memory cells are memory cells MC 1 a or MC 2 a , programmable to two levels.
  • the memory cells MC 1 b or MC 2 b programmable to three levels are designated as ‘3-level memory cells’ and the memory cells MC 1 a or MC 2 a programmable to two levels are designated as ‘2-level memory cells.’
  • the two 3-level memory cells MC 1 b and MC 2 b , forming a pair are arranged in the first string ST 1 and the second string ST 2 , respectively, as shown in FIG. 25 .
  • an advantage can be obtained in a data read operation, using two 3-level memory cells MC 1 b and MC 2 b , forming a pair, arranged in the same string.
  • Page addresses are assigned to the memory cells of the first string ST 1 and the second string ST 2 .
  • the term ‘page addresses’ means a series of numbers for specifying each page. Furthermore, during a single page interval, 1 bit of data can be input or output to or from a memory cell in a specified column.
  • 60 pages are assigned to the first and second strings ST 1 and ST 2 , each using 20 pairs of 3-level memory cells MC 1 b and MC 2 b , in such a way that 30 pages are assigned to each string.
  • 4 pages are assigned to the first and second strings ST 1 and ST 2 , each using two 2-level memory cells MC 1 a or MC 2 a , in such a way that two pages are assigned to each string.
  • 64 pages are assigned to a total of 44 memory cells.
  • page addresses assigned to respective pairs 3-level memory cells MC 1 b and MC 2 b have a sequential relationship, as shown in FIG. 25 .
  • reliability can be improved.
  • Each of the strings ST 1 and ST 2 of FIG. 25 is coupled to a common source line CSL through a ground selection transistor TR 1 g and TR 2 g , respectively.
  • the strings ST 1 and ST 2 are coupled to first and second bit lines BL 1 and BL 2 , respectively, through respective string selection transistors TR 1 s and TR 2 s .
  • the 2-level memory cells MC 1 a and the 3-level memory cells MC 1 b are arranged between the string selection transistor TR 1 s and the ground selection transistor TR 1 g .
  • the 2-level memory cells MC 2 a and the 3-level memory cells MC 2 b are arranged between the string selection transistor TR 2 s and the ground selection transistor TR 2 g.
  • the 2-level memory cells MC 1 a and MC 2 a are arranged to be adjacent respective ground selection transistors TR 1 g and TR 2 g , and adjacent respective string selection transistors TR 1 s and TR 2 s . That is, the 2-level memory cells MC 1 a and MC 2 a , supplied with a lower voltage than that of the 3-level memory cells MC 1 b and MC 2 b during operation, are arranged to be adjacent to the ground selection transistors TR 1 g and TR 2 g and the string selection transistors TR 1 s and TR 2 s .
  • the decrease of reliability caused by the leakage current of the ground selection transistors TR 1 g and TR 2 g and the string selection transistors TR 1 s and TR 2 s is minimized.
  • the non-volatile semiconductor memory device determines the type of page to be operated depending on the row address XADD, and performs a programming or read operation based on the determination of the type of page. For example, if the row address XADD indicates that PAGE 63 is to be selected, the type of the page is a 2-level memory cell. Similarly, if the row address XADD indicates that PAGE 62 is to be selected, the type of the page is a 3-level memory cell. Accordingly, the appropriate programming or read operations for the type of page will be used.
  • FIG. 26 is a flowchart showing an embodiment of a programming operation performed by a non-volatile semiconductor memory device.
  • an operation command CMD for commanding a programming operation is input.
  • a row address XADD and data to be programmed are input.
  • whether the input row address XADD is a 3-level address corresponding to a page having 3-level memory cells is determined. If it is determined that the input row address XADD is not a 3-level address, a typical 2-level programming operation is performed at S 2140 . If it is determined that the input row address XADD is a 3-level address, a programming operation for a corresponding page is performed at steps S 2160 , S 2170 , or S 2180 .
  • FIG. 27 is a flowchart showing an embodiment of a read operation performed by a non-volatile semiconductor memory device.
  • an operation command CMD for commanding a read operation is input.
  • a row address XADD is input.
  • whether the input row address XADD is a 3-level address corresponding to a page having 3-level memory cells is determined. If it is determined that the input row address XADD is not a 3-level address, a typical 2-level read operation is performed at S 2240 . If it is determined that the input row address XADD is a 3-level address, a read operation for a corresponding page is performed at S 2160 , S 2170 or S 2180 .
  • the pair of memory cells may be two memory cells from one string.
  • FIG. 29 and FIG. 30 it is apparent to those skilled in the art that, even though the 3-level non-volatile semiconductor memory device of the present invention is implemented with a NAND-type memory device, the structure of a data control circuit may be suitably modified so that the technical spirit of the invention may be realized in other types of memory devices, such as a NOR and an OR type memory device.

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US20080165580A1 (en) 2008-07-10
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US20100271873A1 (en) 2010-10-28
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