US7075137B2 - Semiconductor memory having charge trapping memory cells - Google Patents

Semiconductor memory having charge trapping memory cells Download PDF

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Publication number
US7075137B2
US7075137B2 US10/890,803 US89080304A US7075137B2 US 7075137 B2 US7075137 B2 US 7075137B2 US 89080304 A US89080304 A US 89080304A US 7075137 B2 US7075137 B2 US 7075137B2
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memory
interconnects
bit lines
source
relevant
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US20050045935A1 (en
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Josef Willer
Christoph Ludwig
Joachim Deppe
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Polaris Innovations Ltd
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Infineon Technologies AG
Qimonda Flash GmbH
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Assigned to QIMONDA AG reassignment QIMONDA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INFINEON TECHNOLOGIES AG, INFINEON TECHNOLOGIES FLASH GMBH & CO. KG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • resent invention relates generally to a memories and more particularly to a semiconductor memory having charge trapping memory cells.
  • a memory cell has a memory transistor, which is provided with a gate electrode at a top side of a semiconductor body or a semiconductor layer.
  • the gate electrode is arranged between a source region and a drain region, which are formed in the semiconductor material.
  • the gate electrode is isolated from the semiconductor material by a dielectric material.
  • a layer sequence comprising a storage layer provided for trapping charge carriers at source and drain between boundary layers is present at least between the source region and the gate electrode and between the drain region and the gate electrode.
  • the material of the boundary layers has a higher energy band gap than the material of the storage layer, so that the charge carriers trapped in the storage layer between the boundary layers remain localized there.
  • a nitride is preferably taken into consideration as material for the storage layer.
  • An oxide is principally suitable as the surrounding material.
  • the memory cell in this example is silicon nitride with an energy band gap of about 5 eV
  • the surrounding boundary layers are silicon oxide with an energy band gap of about 9 eV.
  • the storage layer may be a different material with a smaller energy band gap than that of the boundary layers, the difference between the energy band gaps being intended to be as large as possible for good electrical confinement of the charge carriers.
  • silicon oxide In conjunction with silicon oxide, it is less possible to use e.g., tantalum oxide, hafnium silicate, titanium oxide (in the case of stoichiometric composition TiO 2 ), zirconium oxide (in the case of stoichiometric composition ZrO 2 ), aluminum oxide (in the case of stoichiometric composition Al 2 O 3 ) or intrinsically conducting (undoped) silicon as material of the storage layer.
  • Silicon nitride has a relative permittivity of about 7.9.
  • the use of an alternative material with a higher relative permittivity permits a reduction of the oxide-equivalent overall thickness of the layer stack provided for storage and is therefore advantageous.
  • the present invention specifies a semiconductor memory having charge trapping memory cells in a virtual ground architecture, which is divided into slices.
  • the periodically arranged series of memory transistors T between two successive relevant bit lines are interrupted at predetermined distances. It is the case then that either only insulation regions are present instead of the transistors, or the transistors present are not used as memory cells of the semiconductor memory.
  • an insulation is present between two successive bit lines in the semiconductor body or substrate.
  • the insulation may, in particular, insulate the entire region between the adjoining STI isolations.
  • the sequence of interconnects can be interrupted below the relevant bit line.
  • insulating regions are present below the relevant bit line, which insulating regions are preferably formed by virtue of the fact that the dielectric material which is provided for mutually insulating the interconnects is also introduced into the insulating regions.
  • the bit line contacts may be omitted in the case of the relevant bit line. If the relevant bit line contacts are absent and a sufficient electrical insulation of the bit line is thereby effected, the interconnects may, if appropriate, be present below the relevant bit line.
  • a division of the semiconductor memory may also be performed in circuitry terms.
  • the structure of the memory cell array can then be strictly periodic; the boundaries between the slices result only on account of the driving of the bit lines. This is done in this case such that a series of memory transistors are wired up as dummy memory cells, referred to as dummy mode memory cells hereinafter, between the two relevant bit lines.
  • FIG. 1 shows an arrangement scheme of the STI isolations and word lines
  • FIG. 2 shows an arrangement scheme of the word lines, bit lines and interconnects and of the subdivision into slices for a first exemplary embodiment
  • FIG. 3 shows an arrangement scheme of the word lines, bit lines and interconnects and of the subdivision into slices for a second exemplary embodiment
  • FIG. 4 shows an arrangement scheme of the word lines, bit lines and interconnects and of the subdivision into slices for a third exemplary embodiment.
  • German patent application file ref. 10258194.0 describes a semiconductor memory having charge trapping memory cells in which the channel regions in each case run transversely with respect to the relevant word line and the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter. Electrically conductive interconnects are present in interspaces between the word lines and in a manner electrically insulated from the latter, and are connected to the bit lines in sections.
  • said interconnects electrically conductively connect, on one side of the word line, in each case a source/drain region of an even-numbered memory transistor to a source/drain region of the subsequent odd-numbered memory transistor in said numbering and, on the opposite side of this word line, in each case a source/drain region of an odd-numbered memory transistor to a source/drain region of the subsequent even-numbered memory transistor in said numbering.
  • the word lines can be contact-connected between the bit lines with word line straps which reduce the electrical bulk resistance.
  • FIG. 1 shows a plan view of a scheme revealing the positions of the STI (shallow trench isolation) isolations 1 , word lines 2 with lateral spacers 3 and the regions that are to be electrically conductively connected to one another.
  • the STI isolations 1 represent a multiplicity of isolation trenches which are arranged parallel at a distance from one another and are preferably filled with an oxide of the semiconductor material. However, a different dielectric may also be present in the isolation trenches.
  • the STI isolations are arranged parallel at a distance from one another. Channel regions of the memory transistors T that run parallel to the isolation trenches below each word line 2 are in each case present between said STI isolations.
  • the word lines 2 therefore run over the channel regions arranged transversely with respect to the longitudinal direction of the word line.
  • the source/drain regions of the memory transistors T are in each case present in a manner laterally adjoining the word lines.
  • the source/drain regions are electrically conductively connected to one another in the regions that are in each case identified in hatched fashion in FIG. 1 , a short piece of the relevant isolation trench being bridged in each case.
  • FIG. 2 illustrates a plan view of this arrangement including the bit lines 4 applied above the word lines.
  • the regions depicted in hatched fashion in FIG. 1 are covered with electrically conductive material, designated as interconnects hereinafter, and are in each case designated by the same lower-case letters in FIG. 2 .
  • the interconnects 6 are contact-connected by the bit lines 4 .
  • the bit line contacts 5 are depicted by broken lines as concealed contours in FIG. 2 and identified by a cross. Furthermore, the bit line contacts 5 are in each case designated by that upper-case letter which corresponds to the lower-case letter of the relevant interconnect 6 .
  • bit lines 4 are in each case electrically contact-connected at interconnects 6 which are arranged successively in the direction of the bit lines in each case in next but one interspaces between the word lines 2 .
  • the interconnects 6 in each case bridge an STI isolation 1 and connect a respective source/drain region to a subsequent source/drain region in the relevant interspace between the word line webs. They are electrically insulated from one another and therefore formed in sections and isolated from one another by dielectric material.
  • Semiconductor memories are subdivided into sections, so-called slices, which generally comprise 33 or 34 successive bit lines in the case of the memory architecture described here.
  • Memory areas which typically comprise 33 ⁇ 256 or 33 ⁇ 512 memory cells are formed in this way.
  • the slices have to be electrically isolated from one another and are provided for joint erasure of the memory cells present therein.
  • FIG. 1 illustrates a sectional plan view of an arrangement scheme of the STI isolations and word lines in the case of a first exemplary embodiment, in which a wider STI isolation 7 is present in the sequence of STI isolations 1 arranged parallel to one another.
  • the bit lines 4 may be arranged at uniform distances on the top side of this structure.
  • the relevant bit lines 41 , 42 then serve for driving the memory transistors in slice A (bit line 41 ) and the memory transistors in slice B (bit line 42 ). There are no transistors present between said bit lines 41 , 42 .
  • the wider STI isolation 7 forms a boundary between the slices A, B.
  • the active regions respectively adjoining the wider STI isolation 7 may be made somewhat wider than the rest of the active regions.
  • the active regions may also all have the same width if proximity effects that possibly occur during production, are suitably compensated for by the configuration of the mask used for patterning the STI isolations.
  • assist lines in the mask.
  • the mask has openings which are wider at the boundaries of the slices, in accordance with the wider STI isolations provided there, than above the rest of the STI regions.
  • narrow portions of the mask are provided in each case, so-called assist lines, which are narrow enough in order, during the subsequent lithography, not to effect shielding in the region of the wider STI isolations, but provide for an exposure of the adjoining regions in the envisaged grid.
  • the exemplary embodiment described has the advantage that the division of the semiconductor memory into slices which are electrically insulated from one another can be carried out with a comparatively low outlay without significantly impairing the strict periodicity of the arrangement of the active regions. Consequently, the distribution of the threshold voltages of the memory transistors is essentially identical in comparison with the memory that is not subdivided into slices.
  • the interconnects 6 are omitted below a relevant bit line 40 .
  • Only insulated regions 60 are present instead of the interconnects.
  • the insulated regions 60 may preferably be formed by virtue of the fact that the dielectric material which is introduced into the interspaces between the word lines 2 for the purpose of electrically insulating the interconnects from one another is also introduced below the relevant bit line 40 .
  • This bit line 40 should preferably be connected to ground.
  • the terminal contacts of the relevant bit line 40 are preferably omitted. If this suffices for an electrical insulation, the interconnects may possibly be present below said relevant bit line 40 and the terminal contacts of the bit line on the interconnects may possibly be omitted.
  • the exemplary embodiment in which the relevant interconnects are omitted is preferred.
  • This exemplary embodiment has the advantage that the periodicity of the active regions provided with the transistor structures is not interrupted.
  • the distribution of the threshold voltages of the memory transistors is narrowest in the case of this exemplary embodiment.
  • the structure of the semiconductor memory is unchanged relative to the structure described in the German patent application noted above.
  • a division of the semiconductor memory into slices that are electrically isolated from one another is effected exclusively by the wiring-up. Apart from the edge, the memory cell arrangement is periodic in the case of this exemplary embodiment.
  • a series of memory transistors which are not as such used for storing information are situated between two relevant bit lines 41 , 42 on the boundary between slice A and slice B. These memory transistors instead form dummy transistors or dummy mode memory cells 8 .
  • the charge trapping memory cells it is possible to store bits at both channel ends through suitable polarity of the voltages present on the bit lines.
  • the memory locations 9 are illustrated by the broken lines at the two ends of the transistor structures adjoining the source/drain regions.
  • Programming is effected by trapping hot charge carriers from the channel in the storage layer between the gate electrode, which is part of the respective word line, and the semiconductor material of the channel.
  • a bit is in each case programmed in the memory locations 9 of the dummy mode memory cells adjoining the slice to be erased, in order to prevent a so-called over-erase.
  • Those memory locations of the dummy mode memory cells 8 are in each case programmed here whose respectively adjacent source/drain region is electrically conductively connected via an interconnect 6 to a source/drain region in the slice to be erased.
  • the memory locations 91 are thus programmed prior to the erasure since these memory locations are adjacent to a source/drain region which is connected via the interconnect i depicted to a further source/drain region within slice A.
  • the memory locations 92 are programmed prior to the erasure of slice B since these memory locations are adjacent to a source/drain region which is connected via the interconnect f depicted to a further source/drain region within slice B.
  • the bits written in the dummy mode memory cells 8 are concomitantly erased during the subsequent erase operation. It is advantageous if the memory locations of the dummy mode memory cells 8 are reprogrammed directly after the erase operation, in order to minimize leakage currents that possibly occur and to avoid problems when reading the memory transistors arranged at the edge in slice A or slice B.
  • the programming is preferably performed such that the threshold voltage increases greatly and the leakage currents through the transistor become very small.
  • the advantages of this exemplary embodiment are a small space consumption without interruption of the periodicity of the active regions, the interconnects and the bit line contacts and a very narrow fluctuation in the distribution of the threshold voltages of the memory transistors.

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
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US10/890,803 2003-07-15 2004-07-14 Semiconductor memory having charge trapping memory cells Expired - Fee Related US7075137B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10332095A DE10332095B3 (de) 2003-07-15 2003-07-15 Halbleiterspeicher mit Charge-trapping-Speicherzellen
DE10332095.4 2003-07-15

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US20050045935A1 US20050045935A1 (en) 2005-03-03
US7075137B2 true US7075137B2 (en) 2006-07-11

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EP (1) EP1498953A3 (de)
JP (1) JP4311505B2 (de)
DE (1) DE10332095B3 (de)
TW (1) TWI248195B (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070018278A1 (en) * 2005-07-25 2007-01-25 Michael Kund Semiconductor memory device
KR100733055B1 (ko) 2006-07-10 2007-06-28 삼성전자주식회사 전하 트랩형 비휘발성 메모리 장치 및 그 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311049A (en) 1991-10-17 1994-05-10 Rohm Co., Ltd. Non-volatile semiconductor memory with outer drain diffusion layer
US5583808A (en) 1994-09-16 1996-12-10 National Semiconductor Corporation EPROM array segmented for high performance and method for controlling same
US5825688A (en) 1994-07-26 1998-10-20 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor storage apparatus
US6713315B2 (en) * 2002-03-19 2004-03-30 Macronix International Co., Ltd. Mask read-only memory and fabrication thereof
DE10258194A1 (de) 2002-12-12 2004-07-15 Infineon Technologies Ag Halbleiterspeicher mit Charge-trapping-Speicherzellen und Herstellungsverfahren

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466624A (en) * 1994-09-30 1995-11-14 Intel Corporation Isolation between diffusion lines in a memory array
US6518618B1 (en) * 1999-12-03 2003-02-11 Intel Corporation Integrated memory cell and method of fabrication
DE10058948A1 (de) * 2000-11-28 2002-06-06 Infineon Technologies Ag Halbleiterschaltungsanordnung sowie dazugehöriges Herstellungsverfahren
US6531350B2 (en) * 2001-02-22 2003-03-11 Halo, Inc. Twin MONOS cell fabrication method and array organization
US6569735B2 (en) * 2001-03-20 2003-05-27 Macronix International Co., Ltd. Manufacturing method for isolation on non-volatile memory
JP4565767B2 (ja) * 2001-04-11 2010-10-20 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311049A (en) 1991-10-17 1994-05-10 Rohm Co., Ltd. Non-volatile semiconductor memory with outer drain diffusion layer
US5825688A (en) 1994-07-26 1998-10-20 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor storage apparatus
US5583808A (en) 1994-09-16 1996-12-10 National Semiconductor Corporation EPROM array segmented for high performance and method for controlling same
US6713315B2 (en) * 2002-03-19 2004-03-30 Macronix International Co., Ltd. Mask read-only memory and fabrication thereof
DE10258194A1 (de) 2002-12-12 2004-07-15 Infineon Technologies Ag Halbleiterspeicher mit Charge-trapping-Speicherzellen und Herstellungsverfahren

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TWI248195B (en) 2006-01-21
DE10332095B3 (de) 2005-01-20
JP2005039278A (ja) 2005-02-10
EP1498953A2 (de) 2005-01-19
JP4311505B2 (ja) 2009-08-12
EP1498953A3 (de) 2007-10-17
TW200509373A (en) 2005-03-01
US20050045935A1 (en) 2005-03-03

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