US7002502B2 - Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter - Google Patents

Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter Download PDF

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US7002502B2
US7002502B2 US10/498,765 US49876504A US7002502B2 US 7002502 B2 US7002502 B2 US 7002502B2 US 49876504 A US49876504 A US 49876504A US 7002502 B2 US7002502 B2 US 7002502B2
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bit
matrix
analog
digital converter
columns
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US20050146455A1 (en
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Peter Cornelis Simeon Scholtens
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NXP BV
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Koninklijke Philips Electronics NV
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
    • H03M7/165—Conversion to or from thermometric code

Definitions

  • the invention relates to an analog-to-digital converter for converting an analog input signal into a digital binary output signal, comprising a reference unit for generating a measuring signal based on a comparison of the input signal with a reference voltage, a first logic circuit connected to the reference unit for generating an intermediate signal based on the measuring signal, a second logic circuit connected to the first logic circuit for generating the digital binary output signal based on the intermediate signal, wherein the measuring signal comprises a bit word from a first set of bit words and the intermediate signal comprises a bit word from a second set of bit words, each bit word representing a unique value, and two bit words from the second set, which belong to two consecutive unique values, respectively, differing by no more than one bit, and wherein the bit words from the second set can be arranged in rows in a matrix, the order of the rows corresponding to the unique values represented by the bit words, while in operation each bit of the bit word of the measuring signal is applied to only one input port of the first logic circuit.
  • the invention further relates to a method of generating a code comprising a set of bit words, the method comprising at least the following steps:
  • each bit word containing n bits, where n is an integer greater than one and where each bit word represents a unique value
  • bit words arranged into a set of nodes, each node representing one bit word.
  • the reference unit In the known analog-to-digital converter, the reference unit generates a measuring signal such as, for example, a thermometer signal which comprises a bit word from said first set.
  • This first set is a measuring signal code. It holds for the bit words from the first set that a first part of the bit word consists of a sequence of zeros and that a second part consists of a sequence of ones.
  • the first logic circuit Based on the measuring signal the first logic circuit can generate an intermediate signal which consists of a bit word from the second set.
  • This second set of bit words is an intermediate code known by the name of Gray code, and the intermediate signal based on this is the Gray signal. It holds for the Gray code that the bit words belonging to successive unique values differ from one another by only one bit.
  • the Gray signal is finally converted into the digital binary output signal by the second logic circuit.
  • a disadvantage of the known analog-to-digital converter is that the first logic circuit has a relatively large logic depth (the logic depth being related to the maximum number of series-arranged processing elements in the circuit). In this respect it particularly holds that the logic depth for generating the least significant bit of the Gray code is considerably larger than the logic depth for generating the most significant bit of the Gray code. A consequence of this is that the most significant bit arrives at an output of the first logic circuit earlier than the least significant bit. In this way the conversion from the measuring signal code to the Gray code is limited by the waiting time for the least significant bit. This represents a limitation of the processing speed of the known analog-to-digital converter.
  • the analog-to-digital converter according to the invention is for this purpose characterized in that the respective numbers of bit changes in the respective columns of said matrix are substantially equal.
  • an intermediate code hereinafter to be referred to as S code
  • S signal The intermediate signal based on the S code will be referred to as S signal hereinafter.
  • S codes are possible for the analog-to-digital converter according to the invention. These codes can be generated by the method according to the invention, as will be discussed in more detail below.
  • the logic depth of the first logic circuit of the analog-to-digital converter according to the invention is smaller than the logic depth of the first logic circuit of the known analog-to-digital converter. The result of this is that the intermediate signal in the analog-to-digital converter according to the invention can be delivered at the outputs more rapidly than is the case with the known analog-to-digital converter. Furthermore, it holds that the logic depth of the second logic circuit (for converting the S signal into the binary output signal) of the analog-to-digital converter according to the invention is not larger than the logic depth of the second logic circuit (for converting the Gray signal into the binary output signal) for the known analog-to-digital converter. This means that the speed gain of the first logic circuit according to the invention results in a faster analog-to-digital converter. As a result, the analog-to-digital converter according to the invention can sample input signals with a higher frequency than the known analog-to-digital converter.
  • the first logic circuit will comprise a number of sub-circuits, each sub-circuit generating one bit of the bit word of the intermediate signal. Since the respective numbers of bit variations in the respective columns of the matrix are at least substantially equal, the sub-circuits will at least substantially have the same logic depth.
  • a preferred embodiment of the analog-to-digital converter according to the invention is characterized in that the digital binary output signal contains n bits, where n>1 and where the number of bit changes in each column of said matrix is at least substantially equal to 2 n n .
  • the logic depth of the first logic circuit in this preferred embodiment is approximately equal to n - ln ⁇ ( n ) ln ⁇ ( 2 ) . In this respect it is observed that the logic depth of a first logic circuit for converting the measuring signal into the Gray signal is n ⁇ 1.
  • the consecutive rows of the selected matrix contain consecutive bit words of the S code.
  • the S code thus found may be used for realizing an analog-to-digital converter according to the invention.
  • the number of bit variations is then at least substantially evenly spread over the columns of the matrix.
  • the associated sub-circuits will all have substantially the same logic depth for the generation of the bits.
  • a computer is utilized to traverse all the nodes via said connections made and to select at least one matrix whose respective numbers of bit changes in the respective columns of the matrix are at least substantially equal.
  • FIG. 1 is a diagram of an analog-to-digital converter according to the invention
  • FIG. 2 shows a table having a column with a Thermometer code, a column with a Gray code, a column with an S code, a column with a binary code, and a column with unique values, the S code column comprising a four-column matrix;
  • FIG. 3 is a diagram of a first logic circuit of an analog-to-digital converter according to the state of the art
  • FIG. 4 is a diagram of a first logic circuit of an analog-to-digital converter according to the invention.
  • FIG. 5 is a diagram for illustrating a method according to the invention for generating an S code
  • FIG. 6 is a further diagrammatic illustration of the method illustrated in FIG. 5 .
  • FIG. 1 shows an analog-to-digital converter 2 for converting an analog input signal 4 into a digital binary output signal 6 .
  • the analog-to-digital converter 2 comprises a reference unit 8 for generating a measuring signal 10 based on a comparison of the input signal 4 with a reference voltage 12 .
  • the measuring signal is a bit word from a first set of bit words. This first set is also referred to as a measuring signal code.
  • a highly suitable type of measuring signal is a so-termed thermometer signal.
  • the analog-to-digital converter 2 comprises a first logic circuit 14 which is connected to the reference unit 8 for generating an intermediate signal 16 based on the measuring signal 10 .
  • the intermediate signal 16 is a bit word from a second set of bit words. This second set of bit words is called the intermediate code.
  • Each bit word from the intermediate code represents a unique value, with two bit words belonging to successive unique values differing by only a single bit.
  • the intermediate code mentioned above may be an S code, as will be further explained hereinafter.
  • the analog-to-digital converter 2 further comprises a second logic circuit 18 which is connected to the first logic circuit 14 for generating the digital binary output signal 6 based on the intermediate signal 16 .
  • the binary output signal 6 comprises a bit word from a third set of bit words. This third set is often a binary code.
  • the Table in FIG. 2 comprises a matrix and gives a survey of a possible relationship between the aforesaid codes.
  • the Table shows a possible relationship between a measuring signal code, Gray code, and a binary code for a state of the art analog-to-digital converter.
  • the table further shows a possible relationship between the measuring signal code, S code, and the binary code for an analog-to-digital converter 2 according to the invention.
  • the intermediate code (S code) consists of four bits. Alternatively it is possible for the intermediate code to have more than four bits so as to achieve a certain redundancy.
  • the first main column “Measuring Signal Code” of the Table shows the bit words of the measuring signal code. Each bit word of the measuring signal code is built up from the bits T 15 to T i .
  • the second main column “Gray Code” of the Table shows the Gray code.
  • the Gray code comprises bit words comprising 4 bits G 1 to G 4 each.
  • the Gray code is frequently used as an intermediate code in known analog-to-digital converters.
  • the third main column “S Code” of the Table shows an S code which may be used as an intermediate code in an analog-to-digital converter according to the invention.
  • the fourth main column “Binary Code” in the Table shows the binary code. This binary code is used for reproducing the digital binary output signal 6 .
  • the fifth main column in the Table (“Unique Values”) shows by what path (via rows of the table) a unique value is coupled to each bit word of each code.
  • the analog input signal 4 is compared with the reference voltage 12 .
  • the reference unit 8 comprises a number of comparators (not shown in the drawing) in a manner known per se, each comparator having a first and a second input terminal. Each of the first input terminals is connected to the analog input signal 4 . A unique voltage which is derived from said reference voltage is supplied to each of the second input terminals. Since the unique voltage is different for each comparator, it is possible to measure the analog input signal 4 with the various comparators and to generate a digital measuring signal 10 based on the comparisons. In this process, each comparator drives one bit of the measuring signal code in principle. With an increasing analog input signal 4 , the measuring signal 10 will contain an increasing number of ones.
  • the successive bit words of the measuring signal 10 in the Table of FIG. 2 show that the bit words of the measuring signal 4 can be compressed further. This is effected by a transformation from the thermometer signal 10 to a 4-bit intermediate signal.
  • the 4-bit intermediate signal is an S signal (according to the state of the art, for example, a Gray signal).
  • the transformation is performed by the first logic circuit 14 .
  • FIG. 3 shows on the left hand side by what paths the 15 bits T 1 to T 15 of the bit words of the measuring signal (see also the table in FIG. 2 ) are applied to the inputs of the first logic circuit.
  • the first logic circuit comprises digital AND gates 20 . 1 to 20 . 11 known per se, each gate having two inputs and one output.
  • Each of the AND gates 20 . 1 to 20 . 7 further has one input to which an inverter (negation element) is connected.
  • the inverters are schematically shown in circles.
  • the AND gates 20 . 2 to 20 . 8 and 20 . 11 have an inverter at the output.
  • FIG. 3 together with the Table of FIG. 2 show that the bits G 1 to G 4 of the Gray code are delivered at the outputs of the first logic circuit 14 A.
  • G 1 is then the most significant bit of the Gray code and
  • the first logic circuit 14 A comprises four sub-circuits, each sub-circuit generating a bit of the Gray code.
  • This first sub-circuit for generating G 1 has a logic depth 0. This logic depth is determined by the maximum number of ports or processing elements connected in series.
  • the second sub-circuit for generating G 2 has a logic depth 1
  • the third sub-circuit for generating G 3 has a logic depth 2
  • the fourth sub-circuit for generating G 4 has a logic depth 3.
  • the first logic circuit 14 B comprises digital AND gates 22 . 1 to 22 . 12 known per se, each gate having two inputs and one output.
  • Each of the AND gates 22 . 1 to 22 . 8 further has one input to which an inverter (negation element) is connected.
  • each AND gate includes an inverter at the output.
  • the inverters are schematically shown in circles.
  • the structure of the first logic circuit 14 B is such that this circuit comprises four respective sub-circuits for generating the four respective bits of the S signal.
  • the logic depths of the various sub-circuits are equal in this example.
  • the reason for the equal distribution of the logic depths over the sub-circuits can be traced back in the Table of FIG. 2 .
  • the column under “S code” in the table forms a matrix consisting of four columns and sixteen rows.
  • the number of bit changes per column is approximately equal to 2 n /n.
  • the bits of the intermediate signal are delivered substantially simultaneously at the outputs of the first logic circuit 14 B.
  • a further consequence is the small logic depth of the first logic circuit 14 B, so that the intermediate signal 16 is available at the outputs of the first logic circuit 14 B.
  • the analog-to-digital converter according to the invention has a high data processing rate and can thus sample input signals at a high frequency.
  • each bit of the bit word of the measuring signal is applied to one and only one input port of the first logic circuits.
  • This measure prevents situations that may lead to unnecessary erroneous conversions.
  • An example of such a situation is when a bit is applied to two different ports and when, as a consequence of the changing of the bit value of the bit, different bit words are applied to the ports.
  • FIGS. 5 and 6 illustrate a method of generating an S code.
  • An S code may be used, for example, in an analog-to-digital converter according to the invention.
  • every node of the diagram is connected to four adjacent nodes (boxes), so that the binary representations of the associated bit words differ by only 1 bit (see also the Table in FIG. 2 ).
  • FIG. 5 shows, for example, that the node in which the unique 0 value occurs is connected to the nodes in which the unique values 4, 8, 1 and 2 occur (the diagram is cyclically repeated, see the dotted lines).
  • FIG. 6 An example of a possible way of passing through the nodes is given in FIG. 6 .
  • a matrix is made for each route through the nodes, the bit words of the consecutive nodes being accommodated in successive rows in the matrix. Subsequently, the matrix in which the respective numbers of bit changes in the respective columns are at least substantially equal can be selected from the matrices obtained. In this way an S code according to the invention is found.
  • a computer may be used to traverse all the nodes by every possible path via said connections provided and to select at least one matrix whose respective numbers of bit variations in the respective columns are at least substantially equal.
  • the invention was described above with reference to a number of embodiments in which the intermediate code comprises four bits. However, the invention may be applied in a comparable manner to intermediate codes comprising bit words of more than four bits.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Emergency Protection Circuit Devices (AREA)
US10/498,765 2001-12-20 2002-12-12 Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter Expired - Lifetime US7002502B2 (en)

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EP01205046 2001-12-20
EP01205046.4 2001-12-20
PCT/IB2002/005406 WO2003055076A2 (en) 2001-12-20 2002-12-12 Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter

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JP (1) JP4027895B2 (de)
CN (1) CN100490328C (de)
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DE (1) DE60216146T2 (de)
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US20050264586A1 (en) * 2004-05-25 2005-12-01 Tae-Sung Kim Display device

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US7411756B2 (en) * 2004-02-06 2008-08-12 Agere Systems, Inc. Method and apparatus for write head demagnetization
JP4347865B2 (ja) * 2006-06-22 2009-10-21 ジーイー・メディカル・システムズ・グローバル・テクノロジー・カンパニー・エルエルシー 磁気共鳴イメージング装置及びａ／ｄ変換装置
JP4842989B2 (ja) * 2008-03-28 2011-12-21 株式会社アドバンテスト プライオリティエンコーダならびにそれを利用した時間デジタル変換器、試験装置
JP2010103913A (ja) * 2008-10-27 2010-05-06 Toshiba Corp Ａ／ｄ変換器、及びそれを備えた固体撮像装置
CN101915869A (zh) * 2010-08-13 2010-12-15 天津大学 减小激励信号幅值波动引入测量误差的方法及实施装置
CN105207675B (zh) * 2015-10-21 2018-10-02 昆腾微电子股份有限公司 用于数模转换器的编码、译码装置及方法

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US4733220A (en) * 1985-10-04 1988-03-22 Tektronix, Inc. Thermometer-to-adjacent bindary encoder
US5329279A (en) * 1991-09-20 1994-07-12 U.S. Philips Corporation Method of transcoding data from a thermometric code, decoder and converter applying this method
US5525985A (en) * 1990-12-28 1996-06-11 Eaton Corporation Sure chip
US6268819B1 (en) * 1999-06-29 2001-07-31 Texas Instruments Corporated Bit interpolation in a resistor string data converter
US6542104B1 (en) * 2001-10-22 2003-04-01 Santel Networks, Inc. Method and apparatus for low power thermometer to binary coder
US6774830B2 (en) * 2000-09-11 2004-08-10 Broadcom Corporation Methods and systems for digital dither
US6906656B2 (en) * 2002-10-22 2005-06-14 Samsung Electronics Co., Ltd. Flash type analog to digital converting method and circuit

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US4733220A (en) * 1985-10-04 1988-03-22 Tektronix, Inc. Thermometer-to-adjacent bindary encoder
US5525985A (en) * 1990-12-28 1996-06-11 Eaton Corporation Sure chip
US5329279A (en) * 1991-09-20 1994-07-12 U.S. Philips Corporation Method of transcoding data from a thermometric code, decoder and converter applying this method
US6268819B1 (en) * 1999-06-29 2001-07-31 Texas Instruments Corporated Bit interpolation in a resistor string data converter
US6774830B2 (en) * 2000-09-11 2004-08-10 Broadcom Corporation Methods and systems for digital dither
US6542104B1 (en) * 2001-10-22 2003-04-01 Santel Networks, Inc. Method and apparatus for low power thermometer to binary coder
US6906656B2 (en) * 2002-10-22 2005-06-14 Samsung Electronics Co., Ltd. Flash type analog to digital converting method and circuit

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Publication number Priority date Publication date Assignee Title
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AU2002366892A1 (en) 2003-07-09
AU2002366892A8 (en) 2003-07-09
ATE345595T1 (de) 2006-12-15
JP4027895B2 (ja) 2007-12-26
CN1605157A (zh) 2005-04-06
DE60216146D1 (de) 2006-12-28
WO2003055076A3 (en) 2003-12-24
EP1461866B1 (de) 2006-11-15
US20050146455A1 (en) 2005-07-07
EP1461866A2 (de) 2004-09-29
DE60216146T2 (de) 2007-10-04
WO2003055076A2 (en) 2003-07-03
JP2005513905A (ja) 2005-05-12
CN100490328C (zh) 2009-05-20

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