US6944780B1 - Adaptive voltage scaling clock generator for use in a digital processing component and method of operating the same - Google Patents

Adaptive voltage scaling clock generator for use in a digital processing component and method of operating the same Download PDF

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US6944780B1
US6944780B1 US10/053,227 US5322702A US6944780B1 US 6944780 B1 US6944780 B1 US 6944780B1 US 5322702 A US5322702 A US 5322702A US 6944780 B1 US6944780 B1 US 6944780B1
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Prior art keywords
clock signal
clock
signal
processing component
control circuitry
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Bruno Kranzen
Dragan Maksimovic
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National Semiconductor Corp
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National Semiconductor Corp
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Assigned to NATIONAL SEMICONDUCTOR CORPORATION reassignment NATIONAL SEMICONDUCTOR CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KRANZEN, BRUNO, MAKSIMOVIC, DRAGAN
Priority to CNB038062046A priority patent/CN100511098C/zh
Priority to AU2003209296A priority patent/AU2003209296A1/en
Priority to PCT/US2003/001647 priority patent/WO2003062972A2/en
Priority to JP2003562769A priority patent/JP2006502466A/ja
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention is generally directed to low power integrated circuits and, more specifically, to systems for adjusting a power supply level of a digital processing component and methods of operating the same.
  • ASIC application specific integrated circuit
  • CPU central processing unit
  • DSP digital signal processor
  • VDD is set to a high level, such as +3.3 volts or +2.4 volts. If a CPU or DSP can operate a relatively slow clock frequency, such as 50 MHz, VDD may be set to a low level, such as +1.2 volts.
  • a DSP or CPU may operate in only two modes: a+3.3 volt high power mode and a+1.2 volt low power mode, for example.
  • the +1.2 volt VDD level used at 50 MHz may not be sufficient to operate at 100 MHz.
  • the DSP or CPU will be required to operate at VDD of +3.3 volts.
  • the CPU or DSP may consume far more power that is necessary to operate at 100 MHz.
  • clock generator circuits that selectively apply a clock signal to a large scale digital integrated circuit when the power supply is at a sufficient level to meet the clock speed and are further capable of disabling the clock signal whenever the clock speed is changed until such time as the power supply, VDD, is adjusted to an optimum level suitable for the new clock speed.
  • an adaptive voltage scaling (AVS) clock generator that is capable of generating a system clock signal, CLK, at a desired clock frequency, as specified by a digital processing component associated therewith.
  • An important aspect of an AVS clock generator in accordance with the principles of the present invention is that it ensures proper operation of the digital processing component, which is capable of operating at different clock frequencies.
  • the AVS clock generator when associated with power supply adjustment circuitry in accord with a related embodiment of this invention, further ensures optimum utilization of a power supply.
  • the power supply voltage, VDD is finely adjusted to an optimum level to ensure that the rise times and propagation delays of the digital processing component are closely matched to the clock speed at which the digital processing component operates.
  • clock control circuitry for selectively applying a clock signal to a digital processing component, wherein the clock signal is capable of being changed to a plurality of operating frequencies.
  • the clock control circuitry operable to (i) receive a command to change a first operating frequency to a second operating frequency, (ii) disable the applied clock signal in response to the command, (iii) generate a test clock signal having the second operating frequency, (iv) apply the test clock signal to a power supply adjustment circuit, and (v) sense a status signal from the power supply adjustment circuit indicating that a power supply level of the digital processing component has been adjusted to an optimum value suitable for the second operating frequency.
  • the clock control circuitry is further operable in response to the status signal to set the applied clock signal to the second operating frequency. In a further related embodiment, the clock control circuitry is further operable to enable the applied clock signal.
  • the clock control circuitry comprises clock divider circuitry and a controller.
  • the controller is operable to disable the applied clock signal in response to the received command and enable the applied clock signal in response to the status signal.
  • the clock divider circuitry is operable to generate the test clock signal having the second operating frequency.
  • the clock control circuitry is further operable to set the applied clock signal to the second operating frequency as a function of the test clock signal and the status signal.
  • a digital circuit that includes a digital processing component having dynamic adaptive voltage scaling.
  • the digital circuit further includes an adjustable clock source, an adjustable power supply, power supply adjustment circuitry, and clock control circuitry for selectively applying a clock signal to the digital processing component.
  • the digital processing component is capable of operating at different clock frequencies.
  • the adjustable power supply is capable of supplying power supply voltage, VDD, to the digital processing component.
  • the power supply adjustment circuitry is capable of adjusting VDD.
  • the clock control circuitry is operable to (i) receive a command to change a first operating frequency to a second operating frequency, (ii) in response to the command, disable the applied clock signal, (iii) generate a test clock signal having the second operating frequency, (iv) apply the test clock signal to the power supply adjustment circuit, and (v) sense a status signal from the power supply adjustment circuit indicating that a power supply level of the digital processing component has been adjusted to an optimum value suitable for the second operating frequency.
  • the digital circuit further comprises N delay cells coupled in series, wherein each of the N delay cells has a delay D determined by a value of VDD, such that a clock edge applied to an input of a first delay cell ripples sequentially through the N delay cells.
  • the power supply adjustment circuitry is operable to (i) monitor outputs of at least a K delay cell and a K+1 delay cell, (ii) determine that the clock edge has reached an output of the K delay cell and has not reached an output of the K+1 delay cell, and (iii) generate a control signal capable of adjusting VDD.
  • the power supply adjustment circuitry determines that the clock edge has reached the K delay cell output and has not reached the K+1 delay cell output when a next sequential clock edge is applied to the first delay cell input. A total delay from the first delay cell input to the K delay cell output is greater than a maximum delay of the digital processing component.
  • FIG. 1 illustrates a block diagram of digital processing system according to one exemplary embodiment of the present invention
  • FIG. 2 illustrates the adaptive voltage scaling (AVS) slack time detector of FIG. 1 in greater detail according to an exemplary embodiment of the present invention
  • FIG. 3 illustrates a timing diagram illustrating the operation of the adaptive voltage scaling (AVS) slack time detector according to the exemplary embodiment illustrated in FIG. 2 ;
  • AVS adaptive voltage scaling
  • FIG. 4A illustrates an exemplary delay cell according to a first exemplary embodiment of the present invention
  • FIG. 4B illustrates an exemplary delay cell according to a second exemplary embodiment of the present invention
  • FIG. 5 illustrates an adaptive voltage scaling (AVS) slack time detector according to an alternate exemplary embodiment of the present invention
  • FIG. 6 depicts a flow diagram which illustrates an exemplary method of operating of the adaptive voltage scaling (AVS) slack time detector in the digital processing system of FIG. 1 according to an exemplary embodiment of the present invention
  • FIG. 7 is a block diagram of the AVS clock generator in FIG. 1 according to a first exemplary embodiment of the present invention.
  • FIG. 8 is a block diagram of the AVS clock generator in FIG. 1 according to a second exemplary embodiment of the present invention.
  • FIG. 9 is a flow diagram illustrating the operation of the AVS clock generator in FIG. 1 according to the principles of the present invention.
  • FIGS. 1 through 9 discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged digital processing system.
  • FIG. 1 illustrates a block diagram of digital processing system 100 according to one exemplary embodiment of the present invention.
  • Digital processing system 100 comprises crystal oscillator 105 , phase-locked loop (PLL) frequency synthesizer 110 , adaptive voltage scaling (AVS) clock generator 115 , a digital processing component, labeled DSP/CPU is system 120 , adaptive voltage scaling (AVS) slack-time detector 125 , and adaptive voltage scaling (AVS) power supply 130 .
  • PLL phase-locked loop
  • AVS adaptive voltage scaling
  • Exemplary crystal oscillator 105 generates an output reference frequency signal in which the reference frequency of the output is determined by the mechanical properties of a piezoelectric crystal.
  • Exemplary PLL frequency synthesizer 110 is coupled to the output of crystal oscillator 105 and generates CLKEXT signal, which has an operating frequency that is a multiple of the reference frequency provided by crystal oscillator 105 .
  • the CLKEXT signal may represent a set of clock frequencies.
  • Exemplary AVS clock generator 115 is coupled to the output of PLL frequency synthesizer 110 , digital processing component 120 and AVS slack-time detector 125 and respectively receives as inputs CLKEXT signal, a FREQUENCY CONTROL signal and a STEADY signal.
  • the FREQUENCY CONTROL signal sets the desired operating clock frequency, f clk , which is typically some fraction of the CLKEXT signal. For example, if the CLKEXT signal is 1.6 Ghz, AVS clock generator 115 may divide the CLKEXT signal by four to produce a 400 MHz clock as the CLK signal supplied to DSP/CPU system 120 .
  • the STEADY signal indicates to AVS clock generator 115 that the power supply voltage, VDD, has been adjusted to a sufficient level to match the desired clock speed of the CLK signal.
  • VDD power supply voltage
  • the CLK signal is applied to DSP/CPU system 120 .
  • the desired operating frequency is higher than the current operating frequency
  • DSP/CPU system 120 may be any digital processing component designed for performing mathematical computations and may suitably be programable, meaning that digital processing component 120 may be used for manipulating different types of information, including sound, images, video, and the like.
  • DSP/CPU system 120 has varying operating frequencies and is coupled to the output of AVS clock generator 115 and AVS power supply 130 .
  • DSP/CPU system 120 generates the FREQUENCY CONTROL signal, as well as to communicate input/output (I/O) data with an associated processing system (not shown (e.g., mobile communication unit, computing system, and the like).
  • I/O input/output
  • Exemplary AVS slack-time detector 125 is a critical path slack-time discriminator in accordance with the principles of the present invention.
  • AVS slack-time detector 125 comprises N delay cells and power supply adjustment circuitry (shown with reference to FIG. 2 ), and operable to control AVS power supply 130 to adjust VDD.
  • the N delay cells are coupled in series, each of which has a delay (D) determined by a value of VDD, such that a clock edge applied to an input of a first delay cell ripples sequentially through the N delay cells.
  • the power supply adjustment circuitry which is associated with the N delay cells, is capable of adjusting VDD and is operable to (i) monitor outputs of at least a K delay cell and a K+1 delay cell, (ii) determine that the clock edge has reached an output of the K delay cell and has not reached an output of the K+1 delay cell, and (iii) generate a control signal capable of adjusting VDD in response thereto.
  • FIG. 2 illustrates AVS slack time detector 125 in greater detail according to an exemplary embodiment of the present invention.
  • AVS slack time detector 125 comprises N sequential delay cells 201 , including exemplary delay cells 201 A, 201 B, 201 C, and 201 D, inverter 205 , status register 210 , decoder 215 , and digital filter 220 .
  • Status register 210 further comprises edge-triggered flip-flop (FF) 211 and edge-triggered flip-flop (FF) 212 .
  • Decoder 215 comprises inverter 216 .
  • a rising edge on the REGCLK clock signal will ripple sequentially through each of the delay cells in the chain of N sequential delay cells 201 .
  • the N delay cells 201 are identical components and are made from the same process as the gates in DSP/CPU system 120 .
  • each of the delay cells in the chain of N delay cells has a variable propagation delay, D, between its input (I) and its output (O) that is substantially equal to the variable propagation delay, D, of all of the other N delay cells 201 .
  • the propagation delays are said to be variable because the level of the power supply, VDD, affects the propagation delay, D.
  • VDD the propagation delay, D, of each of the N delay cells 201 decreases.
  • the propagation delay, D, of each of the N delay cells 201 increases.
  • the combined propagation delay from the input of the first delay cell (i.e., delay cell 201 A) to the output of the K delay cell (i.e., delay cell 201 C) is K ⁇ D (i.e., K times D).
  • Exemplary delay cells 201 A, 201 B, 201 C, and 201 D are sequentially labeled by their respective delay periods D1, D2, D(K), and D(K+1).
  • the combined propagation delay, K ⁇ D, from the input of the first delay cell to the output of the K delay cell is designed to model the longest propagation delay through DSP/CPU system 120 , including a safety margin of M propagation delays, scaled by an appropriate factor in case all.
  • the value of K may be set to 8, so that the output of the K delay cell represents eight propagation delays (8D) and the safety margin, M, is two propagation delays.
  • the value of K may be set to 7, so that the output of the K delay cell represents seven propagation delays (7D) and the safety margin, M, is one propagation delay.
  • the value of K may be set to 9, so that the output of the K delay cell represents nine propagation delays (9D) and the safety margin, M, is three propagation delays.
  • the delay cells 201 are fabricated from the same process as the gates in DSP/CPU system 120 , the combined delay, K ⁇ D, at the output of the K delay cell (i.e. delay cell 201 C) changes proportionally, thereby tracking the longest propagation delay through DSP/CPU system 120 .
  • AVS slack time detector 125 The purpose of AVS slack time detector 125 is to control the level of VDD so that a rising edge on the REGCLK clock signal received at the input of delay cell 201 A propagates to the output of the K delay cell (i.e., delay cell 201 C), but not to the output of the K+1 delay cell, by the time a falling edge on the REGCLK clock signal is received. If the rising edge propagates to the output of the K+1 delay cell (i.e., delay cell 201 D) or beyond, then VDD is too large for the current clock speed of the REGCLK clock signal and power is being wasted.
  • VDD is too low for the current clock speed of the REGCLK clock signal and an error may occur due to the longest propagation delay through DSP/CPU system 120 .
  • FIG. 3 is a timing diagram illustrating the operation of AVS slack time detector 125 according to the exemplary embodiment illustrated in FIG. 2 .
  • One illustrative clock pulse is shown.
  • the REGCLK clock signal is low (Logic 0).
  • Inverter 205 inverts the REGCLK clock signal to produce the REGCLK* clock signal, which is applied to the reset (R) inputs of each of the N delay cells 201 .
  • the REGCLK* clock signal is high (Logic 1), which forces the output (O) of each delay cell 201 to Logic 0.
  • the REGCLK clock signal goes to Logic 1 (i.e., rising edge of clock pulse)
  • the REGCLK* clock signal goes to Logic 0, thereby removing the reset (R) signal from all of the delay cells 201 .
  • D1 the output of delay cell 201 A, referred to as Tap 1
  • D2 the output of delay cell 201 B, referred to as Tap 2
  • D(K) the output of delay cell 201 C, referred to as Tap K, goes to Logic 1 (as shown by dotted line).
  • the output of delay cell 201 D After the K+1 propagation delay, D(K+1), the output of delay cell 201 D, referred to as Tap K+1, would normally go to Logic 1.
  • the falling edge of the REGCLK clock signal occurs before the K+1 propagation delay completes.
  • the falling edge of the REGCLK clock signal causes the REGCLK* clock signal to go to Logic 1 (i.e., rising edge), thereby applying a reset (R) signal to all of the N delay cells 201 and resetting the outputs (O) of all delay cells 201 back to Logic 0.
  • Flip-flop (FF) 211 in status register 210 monitors the output of delay cell 201 C (i.e., Tap K) and flip-flop (FF) 212 in status register 210 monitors the output of delay cell 201 D (i.e., Tap K+1).
  • the rising edge of the REGCLK* clock signal causes FF 211 and FF 212 to read the values of the outputs of delay cells 201 C and 201 D before the outputs are reset.
  • the status of the outputs of delay cells 201 C and 201 D referred to as STATUS(A,B), are read on every falling edge of the REGCLK clock signal (i.e., the rising edge of the REGCLK* clock signal).
  • the rising edge of the REGCLK clock signal propagates only as far as the output of the K delay cell (i.e., delay cell 201 C).
  • the value of A which corresponds to the K delay cell output is, represents the raw signal, STEADY IN.
  • the STEADY IN signal may fluctuate between 0 and 1 until the value of VDD is adjusted to a stable level.
  • Digital filter 220 receives STEADY IN and determines when STEADY IN has become stable at Logic 1 before setting the STEADY signal at its output to Logic 1, thereby enabling AVS clock generator 115 .
  • FIG. 4A illustrates exemplary delay cell 201 according to a first exemplary embodiment of the present invention.
  • Delay cell 201 comprises inverter 401 and NOR gate 402 .
  • the reset signal (R) is Logic 1
  • the output (O) of NOR gate 402 is forced to Logic 0 and the input (I) is irrelevant.
  • the reset signal (R) is Logic 0, the input I can pass through to the output (O) of NOR gate 402 .
  • NOR gate 401 a rising edge appears at the output (O) of delay cells 201 after a total delay equal to the combined propagation delays of inverter 401 and NOR gate 402 .
  • FIG. 4B illustrates exemplary delay cell 201 according to a second exemplary embodiment of the present invention.
  • Delay cell 201 comprises NOR gate 402 and an odd number of sequential inverters 401 , including exemplary inverters 401 A and 401 B, and NOR gate 402 .
  • the reset signal (R) is Logic 1
  • the output (O) of NOR gate 402 is forced to Logic 0 and the input (I) is irrelevant.
  • the reset signal (R) is Logic 0, the input I can pass through to the output (O) of NOR gate 402 .
  • a rising edge at the input (I) of delay cell 201 is sequentially inverted an odd number of times by inverters 401 A through 401 B, and is then inverted one last time by NOR gate 401 .
  • an even number of inversions occur and a rising edge appears at the output (O) of delay cells 201 after a total delay equal to the combined propagation delays of NOR gate 402 and all of the inverters 401 A through 401 B.
  • the total delay of delay cell 201 may be manipulated by varying the number of inverters 401 in delay cell 201 .
  • other types of gates that perform an inverting function may be used in place of simple inverters 401 .
  • any type of gate that receives an input I and generates an inverted output, I* may be used.
  • FIG. 5 illustrates AVS slack time detector 125 in greater detail according to an alternate exemplary embodiment of the present invention.
  • the first embodiment of AVS slack time detector 125 illustrated in FIG. 2 produced two control signals, namely UP and DOWN, which could be used to adjust the level of VDD in relatively coarse incremental steps or relatively coarse decremental steps.
  • AVS slack time detector 125 produces a plurality of control signals that may be used to increment or decrement the level of VDD by relatively small amounts and relatively large amounts.
  • AVS slack time detector 125 in FIG. 5 is identical in most respects to AVS slack time detector 125 illustrated in FIG. 2 . The principal difference is in the number of delay cell 201 outputs that are monitored.
  • AVS slack time detector 125 in FIG. 2 only monitored two delay cell 201 outputs (i.e., K and K+1).
  • AVS slack time detector 125 in FIG. 5 monitors the outputs of more than the two delay cells 201 .
  • status register 210 monitors the outputs of Tap R through Tap R+P, which represent a total of P+1 delay cell 201 outputs.
  • the longest propagation delay through DSP/CPU system 120 is less than or equal to 6D (i.e., six propagation delays). If the safety margin, M, is one propagation delay and P equals 3, then Tap R is the output of the 7 th delay cell, Tap R+1 is the output of the 8 th delay cell, Tap R+2 is the output of the 9 th delay cell, and Tap R+3 is the output of the 10 th delay cell. These four delay cell outputs represent the outputs of the K ⁇ 1 delay cell, the K delay cell, the K+1 delay cell, and the K+2 delay cell, respectively.
  • AVS slack time detector 125 is to control the level of VDD so that a rising edge on the REGCLK clock signal received at the input of delay cell 201 A propagates to the output of the K delay cell (Tap R+1), but not to the output of the K+1 delay cell (Tap R+2), by the time a falling edge on the REGCLK clock signal is received.
  • the value of STATUS(K ⁇ 1,K,K+1,K+2) 1100.
  • decoder 215 in FIG. 5 may generate a plurality of VDD control signals having different incremental step sizes or decremental step sizes according to the value of STATUS(K ⁇ 1,K,K+1,K+2).
  • decoder 215 may generate a LARGE UP control signal that increments VDD by a relatively large amount (e.g., +0.1 volt step size). This corrects VDD more rapidly for large errors. If STATUS(K ⁇ 1,K,K+1,K+2) is 1000, then decoder 215 may generate a SMALL UP control signal that increments VDD by a relatively small amount (e.g., +0.01 volt step size). This increases VDD by small amounts for small errors without causing an overshoot.
  • a relatively large amount e.g., +0.1 volt step size
  • decoder 215 may generate a LARGE DOWN control signal that decrements VDD by a relatively large amount (e.g., ⁇ 0.1 volt step size). This corrects VDD more rapidly for large errors. If STATUS(K ⁇ 1,K,K+1,K+2) is 1110, then decoder 215 may generate a SMALL DOWN control signal that decrements VDD by a relatively small amount (e.g., ⁇ 0.01 volt step size). This decreases VDD by small amounts for small errors without causing an undershoot.
  • a relatively large amount e.g., ⁇ 0.1 volt step size
  • decoder 215 may generate LARGE DOWN, MEDIUM DOWN or SMALL DOWN control signals, respectively.
  • AVS slack time detector 125 was described in terms of two trigger events, namely a first occurring rising edge of the REGCLK clock signal and the subsequent falling edge of the REGCLK clock signal, that are used to monitor the slack time and control the level of VDD.
  • this is by way of illustration only and should not be construed so as to limit the scope of the present invention.
  • AVS slack time detector 125 may be easily reconfigured so that a first occurring falling edge of the REGCLK clock signal and a subsequent rising edge of the REGCLK clock signal may be used as trigger events to monitor the slack time and control the level of VDD.
  • FIG. 6 depicts flow diagram 600 , which illustrates the operation of AVS slack time detector 125 in digital processing system 100 according to an exemplary embodiment of the present invention.
  • DSP/CPU system 120 sets the value of the FREQUENCY CONTROL signal to establish a new nominal clock operating speed (e.g., 50 MHz) (process step 605 ).
  • AVS slack time detector 125 monitors the REGCLK signal and determines the amount of slack time, if any.
  • the slack time is the time difference between the longest propagation delay in DSP/CPU system 120 and the pulse width of the REGCLK clock signal (process step 610 ).
  • the longest propagation delay in DSP/CPU system 120 is represented by the total delay, K ⁇ D, at the output of the K delay cell 201 and the pulse width of the REGCLK clock signal is the length of time between a rising clock edge and the next falling clock edge of the REGCLK clock signal.
  • the pulse width of the REGCLK clock signal is the length of time between a falling clock edge and the next rising clock edge of the REGCLK clock signal.
  • FIG. 7 is a block diagram of AVS clock generator 115 according to a first exemplary embodiment of the present invention.
  • AVS clock generator 115 provides clock control circuitry that comprises clock divider circuit 705 (labeled “DIVIDE BY N”), clock divider circuit 710 (labeled DIVIDE BY N 2 ”), and control block 715 .
  • AVS clock generator 115 is operable to selectively apply a clock signal to digital processing component 120 .
  • the clock signal is capable of being changed to a plurality of operating frequencies.
  • Exemplary clock divider circuit 705 receives as inputs the CLKEXT signal from crystal oscillator 105 and the FREQUENCY CONTROL signal, N, from DSP/CPU system 120 .
  • Exemplary clock divider circuit 710 receives as inputs the CLKEXT signal from crystal oscillator 105 and a second FREQUENCY CONTROL signal, N 2 , from control block 715 .
  • Exemplary control block 715 receives as inputs the STEADY signal from AVS slack time detector 125 and the FREQUENCY CONTROL signal, N, from DSP/CPU system 120 .
  • control block 715 In response to receiving the FREQUENCY CONTROL signal, control block 715 halts the CLK signal applied to DSP/CPU system 120 .
  • Clock divider circuit 705 sets REGCLK signal to the new clock speed by dividing the CLKEXT signal by the FREQUENCY CONTROL signal.
  • Control block 715 then monitors the STEADY signal while the level of AVS power supply 130 is adjusted to an optimum value for the new clock speed by AVS slack time detector 125 .
  • control block 715 In response to receiving an enabled STEADY signal from AVS slack time detector 125 , control block 715 enables clock divider circuit 710 which thereby generates a new CLK signal by dividing the CLKEXT signal by the second FREQUENCY CONTROL signal value, N, and applies the new CLK signal to DSP/CPU system 120 .
  • the second FREQUENCY CONTROL signal, N 2 In steady-state, the second FREQUENCY CONTROL signal, N 2 , is equal to the FREQUENCY CONTROL signal, N, or is scaled by a constant.
  • FIG. 8 is a block diagram of AVS clock generator 115 according to a second exemplary embodiment of the present invention.
  • AVS clock generator 115 again provides clock control circuitry for selectively applying a clock signal to DSP/CPU system 120 and comprises clock divider circuit 805 (labeled “DIVIDE BY N”), AND gate 810 , and control block 815 .
  • Clock divider circuit 705 receives as inputs the CLKEXT signal from crystal oscillator 105 and the FREQUENCY CONTROL signal, N, from DSP/CPU system 120 .
  • AND gate 810 receives as inputs the REGCLK signal from clock divider circuit 705 and an ENABLE signal from control block 815 .
  • Exemplary control block 815 receives as inputs the STEADY signal from AVS slack time detector 125 and the FREQUENCY CONTROL signal, N, from DSP/CPU system 120 .
  • control block 715 halts the CLK signal applied to DSP/CPU system 120 by setting the ENABLE signal to Logic 0.
  • Clock divider circuit 705 sets REGCLK signal to the new clock speed by dividing the CLKEXT signal by the FREQUENCY CONTROL signal.
  • Control block 715 then monitors the STEADY signal while the level of VDD power supply 130 is adjusted to an optimum value(s) for the new clock speed by AVS slack time detector 125 .
  • control block 715 sets the ENABLE signal to Logic 1, in order to enable AND gate 810 and apply the new CLK signal (REGCLK) to DSP/CPU system 120 .
  • FIG. 9 depicts flow diagram 900 , which illustrates the operation of AVS clock generator 115 according to the principles of the present invention.
  • AVS clock generator 115 receives a new FREQUENCY CONTROL value, N, from DSP/CPU system 120 (process step 905 ).
  • AVS clock generator 115 halts the CLK signal applied to DSP/CPU system 120 (process step 910 ).
  • AVS clock generator 115 sets REGCLK signal to the new clock speed and monitors STEADY signal while the level of the VDD power supply (or optionally other operational parameters of digital processing system 100 ) is adjusted to an optimum value(s) for the new clock speed (process step 915 ).
  • AVS clock generator 115 sets the CLK signal to the new clock speed and re-applies the CLK signal to DSP/CPU system 120 (process step 920 ).
  • an advantageous embodiment of the present invention is directed to clock control circuitry for selectively applying a clock signal to a digital processing component wherein the clock signal is capable of being changed to a plurality of operating frequencies.
  • the clock control circuitry is operable to (i) receive a command to change a first operating frequency to a second operating frequency, (ii) in response to the command, disable the applied clock signal, (iii) generate a test clock signal having the second operating frequency, (iv) apply the test clock signal to a power supply adjustment circuit, and (v) sense a status signal from the power supply adjustment circuit.
  • the status signal indicates that a power supply level of the digital processing component has been adjusted to an optimum value suitable for the second operating frequency.

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US10/053,227 US6944780B1 (en) 2002-01-19 2002-01-19 Adaptive voltage scaling clock generator for use in a digital processing component and method of operating the same
CNB038062046A CN100511098C (zh) 2002-01-19 2003-01-17 一种用于大规模数字集成电路中的自适应电压定标时钟发生器及其工作方法
AU2003209296A AU2003209296A1 (en) 2002-01-19 2003-01-17 Adaptive voltage scaling clock generator for use in a large-scaledigital ntegrated circuit and method of operating the same
PCT/US2003/001647 WO2003062972A2 (en) 2002-01-19 2003-01-17 Adaptive voltage scaling clock generator for use in a large-scaledigital ntegrated circuit and method of operating the same
JP2003562769A JP2006502466A (ja) 2002-01-19 2003-01-17 デジタル処理コンポーネント内で使用する適応電圧スケーリングクロック発生器およびその操作方法
JP2009235368A JP4825291B2 (ja) 2002-01-19 2009-10-09 デジタル処理コンポーネント内で使用する適応電圧スケーリングクロック発生器およびその操作方法

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US9093846B2 (en) 2009-12-04 2015-07-28 National Semiconductor Corporation Methodology for controlling a switching regulator based on hardware performance monitoring
US8004329B1 (en) 2010-03-19 2011-08-23 National Semiconductor Corporation Hardware performance monitor (HPM) with variable resolution for adaptive voltage scaling (AVS) systems
US8572426B2 (en) 2010-05-27 2013-10-29 National Semiconductor Corporation Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) systems
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AU2003209296A1 (en) 2003-09-02
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WO2003062972A3 (en) 2004-02-26
CN100511098C (zh) 2009-07-08
JP4825291B2 (ja) 2011-11-30
WO2003062972A2 (en) 2003-07-31
CN1643480A (zh) 2005-07-20

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