US6933753B2 - Sensor signal output circuit - Google Patents

Sensor signal output circuit Download PDF

Info

Publication number
US6933753B2
US6933753B2 US10/490,729 US49072904A US6933753B2 US 6933753 B2 US6933753 B2 US 6933753B2 US 49072904 A US49072904 A US 49072904A US 6933753 B2 US6933753 B2 US 6933753B2
Authority
US
United States
Prior art keywords
transistor
gate
differential amplifier
limiter
sensor signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/490,729
Other languages
English (en)
Other versions
US20040239375A1 (en
Inventor
Keisuke Kuroda
Takeshi Uemura
Toshiyuki Nozoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KURODA, KEISUKE, NOZOE, TOSHIYUKI, UEMURA, TAKESHI
Publication of US20040239375A1 publication Critical patent/US20040239375A1/en
Application granted granted Critical
Publication of US6933753B2 publication Critical patent/US6933753B2/en
Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PANASONIC CORPORATION
Assigned to CPPIB CREDIT INVESTMENTS, INC. reassignment CPPIB CREDIT INVESTMENTS, INC. AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Assigned to CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. reassignment CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: CPPIB CREDIT INVESTMENTS INC.
Assigned to MOSAID TECHNOLOGIES INCORPORATED reassignment MOSAID TECHNOLOGIES INCORPORATED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: CONVERSANT INTELLECTUAL PROPERTY INC.
Anticipated expiration legal-status Critical
Assigned to MOSAID TECHNOLOGIES INCORPORATED reassignment MOSAID TECHNOLOGIES INCORPORATED CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME FROM CONVERSANT INTELLECTUAL PROPERTY INC. TO CONVERSANT INTELLECTUAL PROPERT MANAGEMENT INC. PREVIOUSLY RECORDED AT REEL: FRAME: . ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Assigned to MOSAID TECHNOLOGIES INCORPORATED reassignment MOSAID TECHNOLOGIES INCORPORATED CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED ON REEL 058794 FRAME 0701. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Assignors: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45566—Indexing scheme relating to differential amplifiers the IC comprising one or more dif stages in cascade with the dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45636—Indexing scheme relating to differential amplifiers the LC comprising clamping means, e.g. diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45664—Indexing scheme relating to differential amplifiers the LC comprising one or more cascaded inverter stages as output stage at one output of the dif amp circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror

Definitions

  • the present invention relates to a sensor signal output circuit used, for example, in a sensor which detects acceleration, angular velocity, pressure or the like.
  • a sensor for detecting acceleration, angular velocity, pressure or the like generally includes a transducing element for converting the amount of displacement of an object to be detected into an electric signal, and a circuit which electrically amplifies the weak electric signal output from the element for output.
  • the known sensor signal output circuit is illustrated by FIG. 7 .
  • first differential amplifier 26 is formed of transistors 1 , 2 having their respective sources connected to each other, and constant current source 20 connected between the sources of transistors 1 , 2 and first power supply terminal 33 .
  • the electric signal from the sensor is input to a gate of transistor 1 , and first reference voltage setting part 28 is provided at a gate of transistor 2 .
  • First load resistor 30 is an active load for first differential amplifier 26 .
  • This load resistor 30 is formed of diode-connected transistor 3 , and transistor 4 having its gate connected to a gate of transistor 3 .
  • the gate and a drain of transistor 3 are connected to a drain of transistor 1 , while a source of this transistor 3 is connected to second power supply terminal 34 .
  • Transistor 4 has a drain connected to a drain of transistor 2 , and a source connected to second power supply terminal 34 .
  • First transistor 5 for preamplification has a gate connected to the drain of transistor 2 , a source coupled to second power supply terminal 34 via first constant current source 21 , and a drain connected to first power supply terminal 33 .
  • the drain of transistor 2 provides an output of first differential amplifier 26 .
  • Second transistor 6 for output has a gate connected to the source of first transistor 5 , a source connected to second power supply terminal 34 and a drain coupled to first power supply terminal 33 via second constant current source 22 .
  • the drain of second transistor 6 is also connected to output terminal 32 .
  • the voltage input to the receiving circuit is equal to a potential of first power supply terminal 33 , with only this output circuit, a determination cannot be made as to whether this input voltage is a normal output of the sensor or a voltage resulting from the break in the wire or the short circuit to first power supply terminal 33 . Accordingly, another circuit has been required for detecting the short circuit.
  • a sensor signal output circuit includes:
  • a first differential amplifier including an input end connected to a first reference voltage setting part, and an other input end to which a signal is input;
  • a first transistor including a gate connected to an output end of the first differential amplifier, and a source connected to a first constant current source;
  • a second transistor including a gate connected to a point of connection between the first constant current source and the first transistor, and a drain connected to a second constant current source;
  • the limiter section including at least:
  • FIG. 1 is a diagram of a sensor signal output circuit in accordance with a first exemplary embodiment of the present invention.
  • FIG. 2 is a diagram of a sensor signal output circuit in accordance with a second exemplary embodiment of the present invention.
  • FIG. 3 is a diagram of a sensor signal output circuit in accordance with the second embodiment of the invention.
  • FIG. 4 is a diagram of a sensor signal output circuit in accordance with the second embodiment of the invention.
  • FIG. 5 is a diagram of a sensor signal output circuit in accordance with the second embodiment of the invention.
  • FIG. 6 is a diagram of a sensor signal output circuit in accordance with the second embodiment of the invention.
  • FIG. 7 is a diagram of a conventional sensor signal output circuit.
  • a sensor is used as means for inputting a signal to the sensor signal output circuit.
  • the first exemplary embodiment is described with reference to FIG. 1 .
  • first differential amplifier 26 is formed of transistors 1 , 2 having their respective sources connected to each other, and constant current source 20 connected between the common sources of transistors 1 , 2 and first power supply terminal 33 .
  • a signal from a sensor is input to a gate of transistor 1
  • first reference voltage setting part 28 provides a first reference voltage to a gate of transistor 2 .
  • First load resistor 30 is an active load for first differential amplifier 26 .
  • This load resistor 30 is formed of diode-connected transistor 3 , and transistor 4 having its gate connected to a gate of transistor 3 .
  • the gate and a drain of transistor 3 are connected to a drain of transistor 1 , while a source of this transistor 3 is connected to second power supply terminal 34 .
  • Transistor 4 has a drain connected to a drain of transistor 2 , and a source connected to second power supply terminal 34 .
  • First transistor 5 for preamplification has a gate connected to the drain of transistor 2 , a source coupled to second power supply terminal 34 via first constant current source 21 , and a drain connected to first power supply terminal 33 .
  • the drain of transistor 2 provides an output of first differential amplifier 26 .
  • Second transistor 6 for output has a gate connected to the source of first transistor 5 , a source connected to second power supply terminal 34 , and a drain connected to output terminal 32 and coupled to first power supply terminal 33 via second constant current source 22 .
  • Second differential amplifier 27 is formed of sixth and seventh transistors 8 , 9 having their respective sources connected to each other, and third constant current source 23 connected between the sources of sixth and seventh transistors 8 , 9 and first power supply terminal 33 .
  • a gate of sixth transistor 8 is coupled to second power supply terminal 34 via constant current source 24 and connected to a source of output monitoring transistor 12 .
  • Transistor 12 has a drain connected to first power supply terminal 33 , and a gate connected to output terminal 32 .
  • a gate of seventh transistor 9 is coupled to second power supply terminal 34 via constant current source 25 and connected to a source of fourth transistor 13 of second reference voltage setting part 38 .
  • Fourth transistor 13 has a drain connected to first power supply terminal 33 , and a gate connected to second reference voltage 29 , which is a limit voltage.
  • Second load resistor 31 is an active load for second differential amplifier 27 .
  • This second load resistor 31 is formed of diode-connected transistor 14 , and transistor 15 having its gate connected to a gate of transistor 14 .
  • the gate and a drain of transistor 14 are connected to a drain of sixth transistor 8 , while a source of this transistor 14 is connected to second power supply terminal 34 .
  • Transistor 15 has a drain connected to a drain of seventh transistor 9 , and a source connected to second power supply terminal 34 .
  • Output limiting third transistor 7 has a gate connected to the drain of seventh transistor 9 , a source connected to the source of first transistor 5 , the gate of second transistor 6 and first constant current source 21 , and a drain connected to first power supply terminal 33 .
  • the drain of seventh transistor 9 provides an output of second differential amplifier 27 .
  • a limiter section is formed of at least third transistor 7 , second differential amplifier 27 and second reference voltage setting part 38 .
  • the decrease in the output voltage results in a decrease in gate voltage of transistor 12 , and in synchronization with the gate voltage of transistor 12 , gate voltage of sixth transistor 8 decreases.
  • Second reference voltage 29 which is the limit voltage applied to the gate of fourth transistor 13 is applied as a gate voltage of seventh transistor 9 .
  • drain voltage of seventh transistor 9 or the output of second differential amplifier 27 and gate voltage of third transistor 7 decrease.
  • source voltage of transistor 7 and gate voltage of second transistor 6 decrease, whereby the drain voltage of second transistor 6 increases to second reference voltage 29 or the limit voltage.
  • first and third transistors 5 , 7 have their respective sources connected to each other and their respective drains connected to each other, thus having the common source voltage, so that third transistor 7 is turned on, while first transistor 5 is turned off. The output of first differential amplifier 26 is thus cut off, not affecting the output voltage.
  • third transistor 7 is turned off, and first transistor 5 is turned on because these transistors 5 , 7 have the common source voltage.
  • the output of second differential amplifier 27 is thus cut off, not affecting the output voltage.
  • the output voltage of output terminal 32 does not fall short of second reference voltage 29 , so that setting this second reference voltage 29 higher than a potential of first power supply terminal 33 eliminates the possibility that the output voltage will be equal to the potential of first power supply terminal 33 under normal conditions. This allows a receiving circuit to judge that a break in a wire or a short circuit to first power supply terminal 33 has occurred when the output voltage has become equal to the potential of first power supply terminal 33 .
  • the supplied limit voltage effected by the operation of the limiter section for the output voltage is accurate and stable with respect to temperature or the like and can be changed easily by changing second reference voltage 29 .
  • second reference voltage setting part 38 is formed of fourth transistor 13 having its gate connected to second reference voltage 29 , its drain connected to first power supply terminal 33 and its source connected to the input end of second differential amplifier 27 , thus advantageously facilitating setting of second reference voltage 29 .
  • second differential amplifier 27 has a simple structure, which has sixth and seventh transistors 8 , 9 having their respective sources connected to each other, and third constant current source 23 connected to the sources of these transistors 8 , 9 , thus having the advantage of being capable of performing an accurate comparison between the output voltage and second reference voltage 29 .
  • FIG. 2 is a diagram of a sensor signal output circuit in accordance with the present embodiment. Elements similar to those in the first embodiment have the same reference marks, and the descriptions of those elements are omitted.
  • the second embodiment differs from the first embodiment in that the present embodiment includes limiter disengagement part 35 and output saturation part 36 .
  • Limiter disengagement part 35 is formed of fifth transistor 16 connected in parallel to fourth transistor 13 .
  • Output saturation part 36 is formed of tenth transistor 17 provided between first reference voltage setting part 28 and first power supply terminal 33 . The operation of limiter disengagement part 35 and the operation of output saturation part 36 are controlled by abnormality detector 37 .
  • Abnormality detector 37 produces a control signal when, for example, a sensor experiences excessive or abnormal disturbance (such as vibration or an electromagnetic wave) during a period from when the sensor starts to when an output reaches a stable region.
  • excessive or abnormal disturbance such as vibration or an electromagnetic wave
  • abnormality detection signal is input from abnormality detector 37 to a gate of fifth transistor 16 when the output voltage is about to become lower than second reference voltage 29 or a limit voltage as a result of an increase in voltage input to a gate of transistor 1 , fifth transistor 16 forming limiter disengagement part 35 is turned on, thus establishing a short circuit between a source and a drain of fourth transistor 13 . Consequently, voltage between a gate and the source of fourth transistor 13 and second reference voltage 29 are eliminated. Gate voltage of seventh transistor 9 is thus adjusted to a level lower than level-adjusted voltage of sixth transistor 8 , decreasing by the voltage between the gate and source of transistor 13 and second reference voltage 29 .
  • Limiter disengagement part 35 can have another structure, which is as follows. As shown in FIG. 3 , eighth transistor 18 is provided. This transistor 18 has a source connected to common sources of sixth and seventh transistors 8 , 9 , a drain connected to second power supply terminal 34 and a gate connected to an output end of abnormality detector 37 .
  • Limiter disengagement part 35 can have still another structure such as shown in FIG. 4 .
  • ninth transistor 19 is provided.
  • This transistor 19 has a source connected to a gate of third transistor 7 , a drain connected to second power supply terminal 34 , and a gate connected to the output end of abnormality detector 37 .
  • first and third transistors 5 , 7 have common source voltage as in FIG. 2 , so that third transistor 7 is turned off, while first transistor 5 is turned on, whereby the output of second differential amplifier 27 is cut off, not affecting the output voltage. Consequently, the output voltage responsive to the input can be output even in a region lower than second reference voltage 29 , that is, even when the input voltage such as to cause the output voltage to fall short of second reference voltage 29 is input.
  • the sensor signal output circuit thus has the advantage of not making a misjudgment as a result of receiving the signal, which is output by the means for inputting the signal to the sensor signal output circuit when, for example, the system is not stable right after power-up or the like.
  • abnormality detector 37 provides the abnormality detection output to a gate of tenth transistor 17 of output saturation part 36 and the gate of fifth transistor 16 of limiter disengagement part 35 at the same time, a limiter section is disengaged in the manner described above, and tenth transistor 17 is turned on. Since a gate of transistor 2 is grounded to first power supply terminal 33 , the voltage input to the gate of transistor 1 always becomes higher than gate voltage of transistor 2 . For this reason, drain voltage of transistor 2 or an output of first differential amplifier 26 and base voltage of first transistor 5 , the gate of which is at the same potential as a drain of transistor 2 , increase, and the source voltage of transistor 5 also increases. Accordingly, drain voltage of second transistor 6 decreases, whereby the output voltage of output terminal 32 decreases to less than the gate voltage of transistor 2 , thus becoming equal to a potential of first power supply terminal 33 .
  • the output similar to a voltage resulting from a break in a wire or a short circuit to first power supply terminal 33 can be achieved when the abnormality is detected, so that the information about the detected abnormality can be transmitted to a receiving circuit via signal output terminal 32 without another terminal provided for abnormality detection.
  • the sensor signal output circuit is not provided with a level adjustment part.
  • the level adjustment part may be provided on an as needed basis.
  • diode-connected transistors 10 , 11 may be used as shown in FIG. 5 .
  • transistor 10 is interposed between sixth transistor 8 and transistor 12
  • transistor 11 is interposed between seventh transistor 9 and fourth transistor 13 .
  • bipolar transistors (not shown) instead of the transistors used in the embodiment affords the same advantage.
  • the source corresponds to an emitter
  • the drain corresponds to a collector
  • the gate corresponds to a base.
  • an upper limit can be set on the output voltage.
  • a limit voltage that is, a lower limit voltage has been set by second reference voltage setting part 38 in the sensor signal output circuit of the present invention
  • the upper limit voltage can be set in a similar manner. This provides an advantage that a short circuit to second power supply terminal 34 can be detected without a detection circuit. Even the use of bipolar transistors such as described above provides the same advantage.
  • limiter disengagement part 35 is provided to the limiter section, thus providing the same advantage.
  • limiter disengagement part 35 is formed of fifth transistor 16 in parallel with fourth transistor 13 of second reference voltage setting part 38 , and this fifth transistor 16 has its drain connected to the source of fourth transistor 13 , its source connected to first power supply terminal 33 , and its gate serving as an input end for the limiter disengagement signal, thus providing the same advantage.
  • limiter disengagement part 35 is formed of eighth transistor 18 having the source connected to the common sources of sixth and seventh transistors 8 , 9 of second differential amplifier 27 , the drain connected to second power supply terminal 34 , and the gate serving as an input end for the limiter disengagement signal, thus providing the same advantage.
  • limiter disengagement part 35 is formed of ninth transistor 19 having the source connected to the gate of third transistor 7 , the drain connected to second power supply terminal 34 , and the gate serving as an input end for the limiter disengagement signal, thus providing the same advantage.
  • the sensor signal output circuit of this invention is provided with abnormality detector 37 for operating limiter disengagement part 35 in abnormality, and output saturation part 36 for holding the output voltage at a voltage lower than second reference voltage 29 upon receipt of the abnormality detection signal output from abnormality detector 37 , thus providing the advantage that the abnormality other than the break in the wire or the short circuit to first power supply terminal 33 can be detected.
  • output saturation part 36 is formed of tenth transistor 17 having its drain connected to the input end (to which the first reference voltage is input) of first differential amplifier 26 , its source connected to the potential of first power supply terminal 33 , and its gate connected to abnormality detector 37 , thus providing the same advantage.
  • the senor is used as the means for inputting the signal to the sensor signal output circuit.
  • such means is not limited to the sensor.
  • the present invention has the advantage that the break in the wire or the short circuit to first power supply terminal 33 can be detected without the detection circuit.
  • the present invention relates to a sensor signal output circuit used, for example, in a sensor which detects acceleration, angular velocity, pressure or the like. This invention allows detection of a break in a wire or a short circuit to a power supply terminal without a detection circuit.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
US10/490,729 2002-08-07 2003-08-01 Sensor signal output circuit Expired - Lifetime US6933753B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002-229755 2002-08-07
JP2002229755A JP2004072462A (ja) 2002-08-07 2002-08-07 信号出力回路
PCT/JP2003/009791 WO2004015857A1 (ja) 2002-08-07 2003-08-01 センサ信号出力回路

Publications (2)

Publication Number Publication Date
US20040239375A1 US20040239375A1 (en) 2004-12-02
US6933753B2 true US6933753B2 (en) 2005-08-23

Family

ID=31711662

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/490,729 Expired - Lifetime US6933753B2 (en) 2002-08-07 2003-08-01 Sensor signal output circuit

Country Status (6)

Country Link
US (1) US6933753B2 (de)
EP (1) EP1455446B1 (de)
JP (1) JP2004072462A (de)
CN (1) CN100337398C (de)
DE (1) DE60316908T2 (de)
WO (1) WO2004015857A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10084374B1 (en) * 2017-03-23 2018-09-25 Kabushiki Kaisha Toshiba Semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100446417C (zh) * 2004-12-23 2008-12-24 中国科学院电子学研究所 基于双模式的集成isfet传感器信号差分读出电路
JP2010119083A (ja) * 2008-10-17 2010-05-27 Denso Corp 演算増幅器
CN112953414A (zh) * 2021-03-19 2021-06-11 中国兵器工业集团第二一四研究所苏州研发中心 一种像元级的放大器电路

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4401901A (en) * 1981-06-01 1983-08-30 Advanced Micro Devices, Inc. Comparator
US4625131A (en) * 1983-03-31 1986-11-25 U.S. Philips Corporation Attenuator circuit
JPS62112070A (ja) 1985-11-09 1987-05-23 Fujitsu Ten Ltd センサの断線検出装置
US4789799A (en) * 1983-04-05 1988-12-06 Tektronix, Inc. Limiting circuit
JPH03192907A (ja) 1989-12-22 1991-08-22 Yamaha Corp 増幅器
JPH08111616A (ja) 1994-10-07 1996-04-30 Olympus Optical Co Ltd 演算増幅回路
JPH102915A (ja) 1996-06-13 1998-01-06 Mitsubishi Electric Corp 半導体センサ
US6633191B2 (en) * 2001-02-05 2003-10-14 Vitesse Semiconductor Corporation Clock buffer with DC offset suppression

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525934A (en) * 1994-08-24 1996-06-11 National Semiconductor Corporation Output circuit with short circuit protection for a CMOS comparator
US6288604B1 (en) * 1998-02-03 2001-09-11 Broadcom Corporation CMOS amplifier providing automatic offset cancellation

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4401901A (en) * 1981-06-01 1983-08-30 Advanced Micro Devices, Inc. Comparator
US4625131A (en) * 1983-03-31 1986-11-25 U.S. Philips Corporation Attenuator circuit
US4789799A (en) * 1983-04-05 1988-12-06 Tektronix, Inc. Limiting circuit
JPS62112070A (ja) 1985-11-09 1987-05-23 Fujitsu Ten Ltd センサの断線検出装置
JPH03192907A (ja) 1989-12-22 1991-08-22 Yamaha Corp 増幅器
JPH08111616A (ja) 1994-10-07 1996-04-30 Olympus Optical Co Ltd 演算増幅回路
JPH102915A (ja) 1996-06-13 1998-01-06 Mitsubishi Electric Corp 半導体センサ
US6633191B2 (en) * 2001-02-05 2003-10-14 Vitesse Semiconductor Corporation Clock buffer with DC offset suppression

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
English translation of International Search Report for PCT/JP03/09791, dated Nov. 18, 2003.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10084374B1 (en) * 2017-03-23 2018-09-25 Kabushiki Kaisha Toshiba Semiconductor device
US20180278159A1 (en) * 2017-03-23 2018-09-27 Kabushiki Kaisha Toshiba Semiconductor device

Also Published As

Publication number Publication date
WO2004015857A1 (ja) 2004-02-19
DE60316908T2 (de) 2008-02-07
EP1455446A4 (de) 2006-07-05
JP2004072462A (ja) 2004-03-04
US20040239375A1 (en) 2004-12-02
DE60316908D1 (de) 2007-11-29
EP1455446A1 (de) 2004-09-08
EP1455446B1 (de) 2007-10-17
CN100337398C (zh) 2007-09-12
CN1572056A (zh) 2005-01-26

Similar Documents

Publication Publication Date Title
JP4296811B2 (ja) 物理量センサ装置
CA1287384C (en) Controlled-output amplifier and power detector therefor
JP2635277B2 (ja) センサユニット制御システム
US6933753B2 (en) Sensor signal output circuit
US5515008A (en) Output level automatic control apparatus
US4247949A (en) Signal strength detecting circuit
JP3135283B2 (ja) 絶対値検出用信号処理回路装置
US5942945A (en) Arrangement for protecting the output transistors in a power amplifier
US20020008580A1 (en) Automatic gain control circuit, and optical receiver using the same
JP2737481B2 (ja) 半導体加速度センサー
US6339702B1 (en) Output power detection circuit of transmitter
US5079506A (en) Checking circuit for checking the normal operation of a sensor
JP3991981B2 (ja) 信号出力回路
JP3991980B2 (ja) 信号出力回路
JPH08223013A (ja) 電力用トランジスタの過電流保護装置
JPH0649033Y2 (ja) 遠隔制御信号処理回路
JP3991982B2 (ja) 信号出力回路
US20240235503A9 (en) Physical quantity outputting circuit
KR0151414B1 (ko) 영상처리 시스템의 자동이득 조절회로
JPH04295222A (ja) 安定化電源回路
US5555442A (en) Error detecting device for a radio blind zone system
KR100190852B1 (ko) 수신신호레벨검출기의히스테리시스회로_
US20030174011A1 (en) Method of stabilization of operating conditions in electronic devices
JP2946819B2 (ja) プログラム電源装置
JPH046257Y2 (de)

Legal Events

Date Code Title Description
AS Assignment

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KURODA, KEISUKE;UEMURA, TAKESHI;NOZOE, TOSHIYUKI;REEL/FRAME:015656/0370

Effective date: 20040317

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: PANASONIC CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;REEL/FRAME:045607/0661

Effective date: 20081001

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PANASONIC CORPORATION;REEL/FRAME:045773/0387

Effective date: 20180423

AS Assignment

Owner name: CPPIB CREDIT INVESTMENTS, INC., CANADA

Free format text: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:046900/0136

Effective date: 20180731

AS Assignment

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CPPIB CREDIT INVESTMENTS INC.;REEL/FRAME:054344/0143

Effective date: 20201028

AS Assignment

Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA

Free format text: CHANGE OF NAME;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY INC.;REEL/FRAME:058794/0701

Effective date: 20210401

AS Assignment

Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME FROM CONVERSANT INTELLECTUAL PROPERTY INC. TO CONVERSANT INTELLECTUAL PROPERT MANAGEMENT INC. PREVIOUSLY RECORDED AT REEL: FRAME: . ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:064689/0057

Effective date: 20210401

AS Assignment

Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED ON REEL 058794 FRAME 0701. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:064584/0672

Effective date: 20210401