US6621171B2 - Semiconductor device having a wire laid between pads - Google Patents

Semiconductor device having a wire laid between pads Download PDF

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Publication number
US6621171B2
US6621171B2 US10/171,599 US17159902A US6621171B2 US 6621171 B2 US6621171 B2 US 6621171B2 US 17159902 A US17159902 A US 17159902A US 6621171 B2 US6621171 B2 US 6621171B2
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US
United States
Prior art keywords
circuit
semiconductor device
wiring area
semiconductor region
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US10/171,599
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English (en)
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US20030132532A1 (en
Inventor
Toshiyuki Matsubara
Hideo Matsui
Hiroki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
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Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MATSUBARA, TOSHIYUKI, MATSUI, HIDEO, TAKAHASHI, HIROKI
Publication of US20030132532A1 publication Critical patent/US20030132532A1/en
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Publication of US6621171B2 publication Critical patent/US6621171B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a technique for layout of a circuit in a semiconductor device.
  • FIG. 10 shows a layout of a conventional semiconductor device 200 A.
  • a block 201 is surrounded by a wiring area 202 and includes a RAM (random access memory) 201 a , a ROM (read only memory) 201 b , a CPU (central processing unit) 201 c and a peripheral circuit 201 d .
  • a plurality of bonding pads 202 a are arranged in the wiring area 202 , to be connected to the foregoing components in the block 201 by wires not shown.
  • FIG. 11 shows a layout of another conventional semiconductor device 200 B having a greater storage capacity than that of the semiconductor device 200 A.
  • the semiconductor device 200 B differs from the semiconductor device 200 A in that the RAM 201 a and-the ROM 201 b of the device 200 A are replaced with a RAM 201 d and a ROM 201 e , respectively.
  • the RAM 201 d and the ROM 201 e are respectively greater than the RAM 201 a and the ROM 201 b in storage capacity and thus in occupying area in the layout.
  • a RAM or ROM having a greater storage capacity occupies a greater area.
  • the semiconductor device 200 B in which the area of the block 201 is increased while keeping the rectangular shape thereof is newly designed.
  • the semiconductor device 200 B would unavoidably include an unused area in the block 201 which is larger than an unused area in the block 201 of the semiconductor device 200 A by an area 500 as shown in FIG. 11 .
  • the increase of the area of the block 201 itself results in an increase of the area of the wiring area 202 surrounding the block 201 .
  • a semiconductor device includes a first semiconductor region, a second semiconductor region, a wiring area and at least one wire.
  • first semiconductor region at least one first circuit is placed.
  • second semiconductor region at least one second circuit connected to the at least one first circuit is placed.
  • the wiring area includes a plurality of pads connected to the at least one first circuit and surrounds the first semiconductor region.
  • the at least one wire is laid across said wiring area at a single position between two adjacent ones of the plurality of pads per portion of the wiring area which is sandwiched between the first and second semiconductor regions. The at least one wire connects the at least one first circuit and the at least one second circuit to each other.
  • the at least one wire is electrically broken while no request for access to the second circuit from the first circuit is present.
  • FIG. 1 illustrates a layout of a semiconductor device according to a first preferred embodiment of the present invention.
  • FIG. 2 illustrates a layout of a semiconductor device according to a second preferred embodiment of the present invention.
  • FIG. 3 illustrates a layout of a semiconductor device according to a third preferred embodiment of the present invention.
  • FIG. 4 illustrates a layout of a semiconductor device according to a fourth preferred embodiment of the present invention.
  • FIG. 5 illustrates a layout of a semiconductor device according to a fifth preferred embodiment of the present invention.
  • FIG. 6 illustrates a part of a structure of a semiconductor device according to a sixth preferred embodiment of the present invention.
  • FIG. 7 is a flow chart illustrating an outline of operations according to the sixth preferred embodiment of the present invention.
  • FIG. 8 illustrates a part of a structure of a semiconductor device according to a seventh preferred embodiment of the present invention.
  • FIG. 9 illustrates a modification of the present invention.
  • FIGS. 10 and 11 illustrate layouts of conventional semiconductor devices.
  • FIG. 1 shows a layout of a semiconductor device 100 A according to a first preferred embodiment of the present invention.
  • a block 101 as a first semiconductor region, the RAM 201 a , the ROM 201 b , the CPU 201 c and the peripheral circuit 201 d are placed in the same manner as in the block 201 of the conventional device.
  • the block 101 has a substantially quadrangled shape such as a substantially rectangular shape, for example.
  • a ROM 301 , a RAM 302 and an A/D converter 303 which are to be connected with the CPU 201 c are placed.
  • a wiring area 102 surrounding the block 101 is provided, which includes a plurality of pads 102 a arranged therein.
  • the plurality of pads 102 a are connected with circuits placed in the block 101 (which will be hereinafter referred to as “first circuits”) such as the CPU 201 and the peripheral circuit 201 d , for example, via wires not shown.
  • the pads 102 a are further connected with any element or circuit not shown which is provided outside the semiconductor device 100 A.
  • the pads 102 a function as relaying points for electrically connecting the circuits placed in the block 101 to the outside of the semiconductor device 100 A.
  • the layout of the semiconductor device 100 A is such that the wiring area 102 is surrounded by the extension block 103 as the second semiconductor region and is completely sandwiched between the block 101 and the extension block 103 . Further, plural wires 104 are laid across the wiring area 102 only at a single position therein between two adjacent ones out of the pads 102 a , to connect the CPU 201 c and each of the ROM 301 , the RAM 302 and the A/D converter 303 .
  • the foregoing layout of the semiconductor device 100 A eliminates a need for significantly changing a layout of the block 101 in further providing the ROM 301 , the RAM 302 and the A/D converter 303 in addition to the RAM 201 a , the ROM 201 b , the CPU 201 c and the peripheral circuit 201 d , positions of which have already been determined in the block 101 .
  • it is possible to lower an increase of the area of the block 101 or the wiring area 102 surrounding the block 101 which areas would considerably increase by the conventional practices, in increasing the storage capacity of the semiconductor device 100 A.
  • the manner of laying the wires 104 which are laid across the wiring area 102 only at a single position therein is effective in lowering the increase of the area of the block 101 .
  • the manner of the laying the wires 104 allows for suppression of characteristics variation of the block 101 even if the extension block 103 is modified in many ways.
  • each of the block 101 and the extension block 103 may include only a single circuit. Further, not the plural wires 104 but a single wire 104 may be alternatively laid.
  • FIG. 2 shows a layout of a semiconductor device 100 B according to a second preferred embodiment of the present invention.
  • the first circuits including the RAM 201 a , the ROM 201 b and the CPU 201 c , and circuits placed in the extension block 103 (which will be hereinafter referred to as “second circuits”) such as the peripheral circuit 201 d , the ROM 301 , the RAM 302 and the A/D converter 303 (see FIG. 1) are not shown for purposes of simplification.
  • the layout of the semiconductor device 100 B is such that only three sides of the block 101 having a substantially rectangular shape face the extension block 103 with the wiring area 102 interposed therebetween. In other words, a portion of the wiring area 102 is sandwiched between the block 101 and the extension block 103 such that the sandwiched portion is substantially U-shaped. Further, the wires 104 are laid across the wiring area 102 only at the single position 204 which is located within the portion of the wiring area 102 sandwiched between the block 101 and the extension block 103 .
  • each pad out of the pads 102 a located in a portion of the wiring area 102 which is not sandwiched between the block 101 and the extension block 103 is denoted by a reference numeral 102 b, in distinction from the other pads 102 a located in the sandwiched portion of the wiring area 102 .
  • the pad 102 b is configured so as to have a function of receiving an external input signal such as an analog input, for example. By having the pad 102 b receive an external input signal, the length of a wire extending from the outside of the device to the circuit placed in the block 101 is reduced as compared with a structure where an external input signal is received by the pads 102 a.
  • the position 204 can be determined anywhere in the wiring area 102 , provided that the position 204 is located in a single space between two adjacent ones of the pads 102 a within the portion of the wiring area 102 sandwiched between the block 101 and the extension block 103 .
  • the position 204 can be determined within a portion of the wiring area 102 which portion extends along a longitudinal direction of the drawing.
  • FIG. 3 illustrates a layout of a semiconductor device 100 C according to a third preferred embodiment of the present invention.
  • the first and second circuits are not shown for purposes of simplification in FIG. 3 as well.
  • the layout of the semiconductor device 100 C is such that only one side of the block 101 having a substantially rectangular shape faces the extension block 103 with the wiring area 102 interposed therebetween.
  • a portion of the wiring area 102 is sandwiched between the block 101 and the extension block 103 such that the sandwiched portion is substantially I-shaped.
  • the wires 104 are laid across the wiring area 102 only at the single position 204 which is located between two adjacent ones of the pads 102 a within the portion of the wiring area 102 sandwiched between the block 101 and the extension block 103 .
  • extension block 103 By placing the extension block 103 on only one side of the block 101 , it is possible to reduce a load applied within the extension block 103 such as a wire capacitance, for example.
  • each of the pads 102 a located in a portion of the wiring area 102 not sandwiched between the block 101 and the extension block 103 may be configured so as to have a function of receiving an external input signal such as an analog input, for example, as described in the second preferred embodiment, of course.
  • FIG. 4 shows a layout of a semiconductor device 100 D according to a fourth preferred embodiment of the present invention.
  • the first and second circuits are not shown for purposes of simplification in FIG. 4 as well.
  • the layout of the semiconductor device 100 D is such that only two adjacent sides of the block 101 having a substantially rectangular shape face the extension block 103 with the wiring area 102 interposed therebetween. A portion of the wiring area 102 is sandwiched between the block 101 and the extension block 103 such that the sandwiched portion is substantially L-shaped. Further, the wires 104 are laid across the wiring area 102 only at the single position 204 which is located between two adjacent ones of the pads 102 a within the portion of the wiring area 102 sandwiched between the block 101 and the extension block 103 .
  • the fourth preferred embodiment makes it easier to shape the entire semiconductor device 100 D like a square, which provides for increased productivity.
  • each of the pads 102 a located in a portion of the wiring area 102 not sandwiched between the block 101 and the extension block 103 may be configured so as to have a function of receiving an external input signal, as described in the second preferred embodiment, of course.
  • FIG. 5 shows a layout of a semiconductor device 100 E according to a fifth preferred embodiment of the present invention.
  • the first and second circuits except RAMs 302 a and 302 b each of which is one of the second circuits are not shown for purposes of simplification.
  • the RAMs 302 a and 302 b are placed in extension blocks 103 a and 103 b , respectively.
  • the RAMs 302 a and 302 b are connected to the circuits not shown which are placed in the block 101 by wires 104 a and 104 b , respectively.
  • the layout of the semiconductor device 100 E is such that only two sides of the block 101 having a substantially rectangular shape face the block 103 a and 103 b , respectively, with the wiring area 102 interposed therebetween. A portion of the wiring area 102 is sandwiched between the block 101 and the extension block 103 a such that the sandwiched portion is substantially I-shaped, while another portion of the wiring area 102 is sandwiched between the block 101 and the extension block 103 b such that the sandwiched portion is substantially I-shaped. These portions of the wiring area 102 face each other.
  • a single position 204 a between two adjacent ones of the pads 102 a within the portion of the wiring area 102 sandwiched between the block 101 and the extension block 103 a is specified, while another single position 204 b between two adjacent ones of the pads 102 a within the portion of the wiring area sandwiched between the block 101 and the extension block 103 b is specified.
  • the wires 104 a and 104 b are laid across the wiring area 102 only at positions 204 a and 204 b , respectively.
  • the wires 104 described in the first to fourth preferred embodiments and the wires 104 a and 104 b described in the fifth preferred embodiment contain a common feature in that the wires are laid across the wiring area 102 only at a single position per portion of the wiring area 102 sandwiched between the block 101 and the extension block 103 (or 103 a , 103 b ).
  • the fifth preferred embodiment facilitates equalization of the respective characteristics regarding access to the RAM 302 a and 302 b from the circuits placed in the block 101 .
  • each of the pads 102 a located in a portion of the wiring area 102 not sandwiched between the block 101 and the extension block 103 a , 103 b may be configured so as to have a function of receiving an external input signal, as described in the second preferred embodiment, of course.
  • Sixth and seventh preferred embodiments of the present invention will propose techniques for electrically breaking the wires 104 while no request for access from the first circuits to the second circuits is present.
  • the techniques proposed in the sixth and seventh preferred embodiments avoid a situation in which although access to the second circuits is unnecessary, a wire capacitance is unwantedly applied to the first circuits. This improves an operation speed of the first circuits of the semiconductor device.
  • FIG. 6 illustrates a portion of a structure of a semiconductor device according to the sixth preferred embodiment of the present invention.
  • the block 101 , the wiring area 102 and the extension block 103 shown therein are identical to those described in the first preferred embodiment.
  • the sixth preferred embodiment is also applicable to any of the second to fifth preferred embodiments without any difficulty.
  • the peripheral circuit 201 d includes an access permitting register 210 for permitting access to the extension block 103 .
  • the access permitting register 210 is configured so as to allow a “permit command” which is a command for permitting access to be written thereinto from the CPU 201 c .
  • the RAM 302 is provided in the extension block 103 , and is connected with the CPU 201 c via the wire 104 .
  • the block 101 further includes a switch 211 placed at some midpoint in the wire 104 .
  • the switch 211 operates to electrically connect the CPU 201 c and the RAM 302 with each other while the permit command is being written into the access permitting register 210 .
  • the switch 211 operates to break the electrical connection between the CPU 201 c and the RAM 302 which is established by the wire 104 while the permit command is not being written into the access permitting register 210 .
  • FIG. 7 is a flow chart illustrating an outline of operations according to the sixth preferred embodiment of the present invention.
  • a request for access to the extension block 103 is made in a step S 11 .
  • Such request is made when instruction executed by the CPU 201 c requires access to an address assigned to the RAM 302 , for example.
  • the electrical connection between the CPU 201 c and the RAM 302 established by the wire 104 is still being broken by the switch 211 .
  • the permit command is written by the CPU 201 c into the access permitting register 210 in a step S 12 .
  • This writing operation turns the switch 211 ON in a step S 13 , so that access to the extension block 103 is carried out. For example, access to an address assigned to the RAM 302 from the CPU 201 c is carried out.
  • the permit command in the access permitting register 210 is deleted by, for example, the CPU 201 c .
  • the switch 211 breaks the electrical connection between the CPU 201 c and the RAM 302 which is established by the wire 104 .
  • FIG. 8 shows a portion of a structure of a semiconductor device according to the seventh preferred embodiment of the present invention.
  • the block 101 , the wiring area 102 and the extension block 103 are identical to those described in the first preferred embodiment.
  • the seventh preferred embodiment is also applicable to any of the second to fifth preferred embodiments without any difficulty.
  • the RAM 302 placed in the extension block 103 and the CPU 201 c placed in the block 101 are connected with each other via the wire 104 .
  • the block 101 further includes a gate 213 and a logic circuit 212 each placed at some midpoint in the wire 104 .
  • An address assigned to a destination of access which is required by instruction executed by the CPU 201 c , is supplied to the logic circuit 212 . If the supplied address corresponds to an address assigned to one of the second circuits, for example, the RAM 302 , the gate 213 is opened, so that the RAM 302 and the CPU 201 c are electrically connected with each other via the wire 104 . Otherwise, if the supplied address does not have a predetermined number assigned to any of the second circuits, the gate 213 is closed, so that the electrical connection between the CPU 201 c and the RAM 302 established by the wire 104 is broken.
  • the logic circuit 212 is exemplified by a NAND circuit, and the gate 213 is exemplified by an inverter which permits or forbids electrical connection based on a negative logic.
  • the logic circuit 212 is provided with an address AD from the CPU 201 c , and outputs a signal AE which is an active low signal.
  • the gate 213 inverts the output from the CPU 201 c and provides the inverted output to the RAM 302 .
  • FIG. 8 illustrates an instance where an address necessary for access to the RAM 302 is formed of bits each being “1”.
  • the signal AE enters an active state.
  • the logic circuit 212 may alternatively be configured so as to allow the signal AE to enter an active state when the address AD has another predetermined number.
  • the gate 213 may alternatively be an transmission gate, not an inverter.
  • the second circuits placed in the extension block 103 may include a D/A converter, a timer, a serial input/output interface, a clock generating circuit and any other peripheral circuit, singly or in combination, in addition to a RAM, a ROM and an A/D converter.
  • FIG. 9 shows a plurality of wires 104 a , 104 b and 104 c which are laid across portions of the wiring area 102 between the block 101 and the extension block 103 (or 103 a , 103 b ).
  • the wires 104 a , 104 b and 104 c are laid across the wiring area 102 not at a single position between two adjacent ones of the pads 102 a , but at plural positions each between two adjacent ones of the pads 102 a .
  • Such layout provides for reduction of wire capacitance of the extension block 103 (or 103 a , 103 b ).

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
US10/171,599 2002-01-15 2002-06-17 Semiconductor device having a wire laid between pads Expired - Fee Related US6621171B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002-005920 2002-01-15
JP2002005920A JP2003209178A (ja) 2002-01-15 2002-01-15 半導体装置

Publications (2)

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US20030132532A1 US20030132532A1 (en) 2003-07-17
US6621171B2 true US6621171B2 (en) 2003-09-16

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US (1) US6621171B2 (enrdf_load_stackoverflow)
JP (1) JP2003209178A (enrdf_load_stackoverflow)
KR (1) KR100463945B1 (enrdf_load_stackoverflow)
DE (1) DE10236877A1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030057454A1 (en) * 2001-09-21 2003-03-27 Mitsubishi Electric System Lsi Design Corporation Semiconductor device comprising memories on the inside and outside of bonding pad

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6166403A (en) * 1997-11-12 2000-12-26 Lsi Logic Corporation Integrated circuit having embedded memory with electromagnetic shield
JP2000077609A (ja) * 1998-08-28 2000-03-14 Hitachi Ltd 半導体集積回路装置
KR100688476B1 (ko) * 2000-05-31 2007-03-08 삼성전자주식회사 칩 면적을 줄이기 위한 레이아웃 구조를 갖는 고속 메모리장치

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030057454A1 (en) * 2001-09-21 2003-03-27 Mitsubishi Electric System Lsi Design Corporation Semiconductor device comprising memories on the inside and outside of bonding pad
US6998655B2 (en) * 2001-09-21 2006-02-14 Mitsubishi Electric System Lsi Design Corporation Semiconductor device comprising memories on the inside and outside of bonding pad

Also Published As

Publication number Publication date
DE10236877A1 (de) 2003-07-24
KR100463945B1 (ko) 2004-12-30
JP2003209178A (ja) 2003-07-25
US20030132532A1 (en) 2003-07-17
KR20030062209A (ko) 2003-07-23

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