US6465318B1 - Bipolar transistor and method for producing same - Google Patents

Bipolar transistor and method for producing same Download PDF

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Publication number
US6465318B1
US6465318B1 US09/787,571 US78757101A US6465318B1 US 6465318 B1 US6465318 B1 US 6465318B1 US 78757101 A US78757101 A US 78757101A US 6465318 B1 US6465318 B1 US 6465318B1
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layer
zone
deposition
transistor
buffer layer
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Expired - Fee Related
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US09/787,571
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English (en)
Inventor
Karl-Ernst Ehwald
Bernd Tillack
Bernd Heinemann
Dieter Knoll
Dirk Wolansky
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Institut fuer Halbleiterphysik GmbH
IHP GmbH
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Institut fuer Halbleiterphysik GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

Definitions

  • the invention relates to a bi-polar transistor and a procedure for its manufacture.
  • double polysilicon technologies are used in modem procedures to manufacture vertical bi-polar transistors.
  • Such technologies make it possible to arrange the base contact and parts of the highly conductive polysilicon connection between the contact and the inner base through insulated zones.
  • these design advantages as compared with the “simple polysilicon technologies” are associated with such disadvantages as additional process complexity and increased contact resistance.
  • These disadvantages arise in connection with the required etching of the polysilicon in the active zone of the transistor, and the diffusion of the doping agents from the highly doped polysilicon layer into the monocrystal base zone.
  • In-situ doping is used during the deposition in order to achieve smaller sizes of the base, i.e., smaller thickness of the base layer and smaller base layer resistance.
  • An additional variance in achieving a certain resistance of the base layer and a current gain and, therefore, optimal high-speed properties is provided by the deposition of heterogeneous layers.
  • the concept of the double polysilicon technology with an etching-stop layer is also applied in the case of an epitaxially deposited base layer using the so-called selective epitaxy.
  • the deposition conditions are such that the epitaxial growth occurs only on uncovered semiconductor surface. If differential epitaxy is used, during which the silicon material is deposited both on the semiconductor and the insulator zones, an inner base and the connection to a base contact (base zone) located on the insulator zone can be produced at the same time. This generally eliminates the need of an additional polysilicon layer.
  • the resulting quasi double polysilicon arrangement allows to simplify the process.
  • the thickness of the epitaxy layer in the active transistor zone cannot be set independently from the thickness of the silicon layer in the base zone or on the insulator zones. Due to the insufficient nucleation of the SiO 2 layer usually used as insulator, the polycrystal layer is usually thinner than the epitaxially grown layer. As for the epitaxy layer thickness, two different requirements exist. Within the emitter zone, a sufficiently thin layer should be present between the highly doped emitter and the base. A thicker layer is beneficial in the outer base zone to allow low resistance of the base.
  • the patent documentation U.S. Pat. No. 5,137,840A describes differential epitaxy process in a UHVCVD system at a pressure between 1 ⁇ 10 ⁇ 4 and 1 ⁇ 10 ⁇ 2 Torr and a constant deposition temperature of 500-800° C. for the buffer layer.
  • the task of this invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance.
  • This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone.
  • the greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer.
  • this invention also includes the possible use of an amorphous silicon layer.
  • the use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition.
  • the deposition at a very low temperature allows a higher deposition rate for the polycrystal or amorphous layer as compared with the epitaxial layer. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.
  • a simple polysilicon bi-polar transistor with an epitaxially made base allows a reduction of the outer base resistance without having to accept a deterioration of the emitter properties. Due to a continuous deposition of the inner and outer zones no surface problems occur with the base.
  • FIG. 1 A schematic illustration of a bi-polar transistor
  • FIG. 2 A schematic illustration of a bi-polar transistor according to FIG. 1 during the manufacture.
  • FIG. 1 schematically shows a bi-polar transistor 10 according to this invention.
  • a collector zone of conductivity type II is made on semiconductor substrate zone 11 of conductivity type I. If the emitter and collector are e.g. n-conductive, the base is of a p-type or vice versa.
  • Another version is implanted retrogressive domains.
  • a field insulation zone 14 separates the bi-polar transistor from other components not shown in FIG. 1, and also separates the collector zone from the active transistor zone.
  • Other suitable insulation techniques are also known such as spaced mesa arrangements.
  • a shaft implant 20 can be applied in order to reduce the resistance between the contact layer 21 made of highly doped polysilicon and the buried layer 12 .
  • the epitaxy layer structured outside the active transistor zone is covered with a dielectric 18 .
  • a thick polycrystal layer 19 is applied on the insulator zone.
  • an amorphous layer can be used instead of the polycrystal layer 19 .
  • the particular values of the thickness, doping agent content as well as the material composition of the base are to be selected depending on the desired functions of the bi-polar transistor and are not subject to any special requirements from the point of this invention.
  • the base layer is made of silicon with a doping of 2 ⁇ 10 18 cm ⁇ 3 , and is 40 nm thick.
  • other material compositions and doping profiles can be used, too.
  • the application of a thin cover layer 17 over the base layer is possible but not essential for the present invention.
  • the doping of the emitter in a monocrystal silicon is performed by out-diffusion of the doping agent 22 from the highly doped polysilicon contact layer 21 .
  • the thickness of the deposited cover layer can be typically 50 nm.
  • polycrystal layers 19 arise over the insulation zone 14 .
  • the thickness of the deposited polycrystal layer is greater than the thickness of the monocrystal layer.
  • the doping in the base zone is additionally increased by implantation 23 .
  • the insulation layer 24 separates the emitter, base, and collector contact. Metal contacts for emitter 25 , base 26 and collector 27 complete the design of the transistor.
  • FIG. 2 shows the basic structure of the procedure according to this invention.
  • a highly doped n-layer 12 is applied on a p-doped silicon substrate 11 after a photolithographic structuring and layer 12 is subsequently cured.
  • a slightly doped n-layer 13 is deposited by epitaxy.
  • Usual process steps define the active zone and produce insulation zones 14 (e.g. LOCOS) in the remaining zones.
  • the buffer layer 15 is deposited by means of differential epitaxy at a very low temperature.
  • a typical example of the deposition temperature is 550° C. At this temperature, the nucleus formation on the insulator zone is improved and the idle time is reduced.
  • the deposition rate of the polycrystal layer is greater than the deposition rate of the epitaxial layer.
  • the base layer 16 and the cover layer 17 are deposited.
  • the polycrystal layer 19 on the insulator is thicker than the monocrystal layer in the active transistor zone.
  • the deposited silicon or polysilicon layers are removed in the area of the future transistor and base zones by means of a plasma etching procedure using an etching stop on the insulation zone.
  • a dielectric 18 preferably an oxide, is subsequently applied.
  • the collector zone is now exposed and shaft implant 20 is introduced.
  • an oxide layer is etched, preferably in a wet chemical process, in the collector zone and in the emitter zone. The process continues with the deposition of an amorphous silicon layer. This layer can be doped in-situ by implantation during or after the deposition.
  • the emitter and collector zones are covered by means of a lithographic procedure.
  • the amorphous silicon is removed by plasma etching with a stop on the SiO 2 layer.
  • the emitter and collector contact zones are protected by the existing masking.
  • annealing is performed to cure the implantation damage and to form the poly-emitter. The process is completed by opening contact apertures for the emitter, base and collector and a standard metallization for the transistor contacts.
  • FIG. 2 shows the basic structure of the procedure according to this invention.
  • a highly doped n-layer 12 is applied on a p-doped silicon substrate 11 after a photolithographic structuring and layer 12 is subsequently cured.
  • a slightly doped n-layer 13 is deposited by epitaxy.
  • Usual process steps define the active zone and produce insulation zones 14 (e.g. LOCOS) in the remaining zones.
  • the buffer layer 15 is deposited by differential epitaxy in two steps. In the first step, a very low temperature is used. A typical value for the temperature used is 550° C. At this temperature, the nucleus formation on the insulator zone is improved and the idle time is reduced.
  • the deposition rate of the polycrystal layer is greater than the deposition rate of the epitaxial layer.
  • the growth of the buffer layer continues at the same temperature or also at an increased temperature (a typical temperature is 650° C.).
  • the base layer 16 and the cover layer 17 are deposited.
  • the polycrystal layer 19 on the insulator is thicker than the monocrystal layer in the active transistor zone.
  • the deposited silicon or polysilicon layers are removed in the area of the future transistor and base zones by means of a plasma etching procedure using an etching stop on the insulation zone.
  • a dielectric 18 preferably an oxide, is subsequently applied.
  • the collector zone is now exposed and shaft implant 20 is introduced.
  • an oxide layer is etched, preferably in a wet chemical process, in the collector zone and in the emitter zone. The process continues with the deposition of an amorphous silicon layer. This layer can be doped in-situ by implantation during or after the deposition.
  • the emitter and collector zones are covered by means of a lithographic procedure.
  • the amorphous silicon is removed by plasma etching with a stop on the SiO 2 layer.
  • annealing is performed to cure the implantation damage and to form the poly-emitter.
  • the process is completed by opening contact apertures for the emitter, base and collector and a standard metallization for the transistor contacts.
  • the present invention has explained, by means of concrete examples, a bi-polar transistor and a procedure for its manufacture.
  • the present invention is not restricted to the details of the description in the example designs, since alterations and changes are also claimed within this patent, since especially modifications of this process such as hetero-epitaxy or the integration in a bi-polar CMOS (BiCMOS) technology is also possible.
  • BiCMOS bi-polar CMOS
US09/787,571 1998-09-21 1999-09-20 Bipolar transistor and method for producing same Expired - Fee Related US6465318B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19845793 1998-09-21
DE19845793A DE19845793A1 (de) 1998-09-21 1998-09-21 Bipolartransistor und Verfahren zu seiner Herstellung
PCT/DE1999/003072 WO2000017933A1 (fr) 1998-09-21 1999-09-20 Transistor bipolaire et son procede de fabrication

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Country Status (6)

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US (1) US6465318B1 (fr)
EP (1) EP1118124B1 (fr)
JP (1) JP2002525873A (fr)
AT (1) ATE490559T1 (fr)
DE (2) DE19845793A1 (fr)
WO (1) WO2000017933A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100019326A1 (en) * 2006-12-08 2010-01-28 Dieter Knoll Complementary bipolar semiconductor device
US8786051B2 (en) 2012-02-21 2014-07-22 International Business Machines Corporation Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10160511A1 (de) * 2001-11-30 2003-06-12 Ihp Gmbh Bipolarer Transistor

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100019326A1 (en) * 2006-12-08 2010-01-28 Dieter Knoll Complementary bipolar semiconductor device
US8035167B2 (en) 2006-12-08 2011-10-11 IHP-GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut fur Innovativ Mikroelektronik Complementary bipolar semiconductor device
US8786051B2 (en) 2012-02-21 2014-07-22 International Business Machines Corporation Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance

Also Published As

Publication number Publication date
EP1118124A1 (fr) 2001-07-25
EP1118124B1 (fr) 2010-12-01
DE59915224D1 (de) 2011-01-13
WO2000017933A1 (fr) 2000-03-30
ATE490559T1 (de) 2010-12-15
DE19845793A1 (de) 2000-03-23
JP2002525873A (ja) 2002-08-13

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