US6452521B1 - Mapping a delta-sigma converter range to a sensor range - Google Patents

Mapping a delta-sigma converter range to a sensor range Download PDF

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Publication number
US6452521B1
US6452521B1 US09/808,516 US80851601A US6452521B1 US 6452521 B1 US6452521 B1 US 6452521B1 US 80851601 A US80851601 A US 80851601A US 6452521 B1 US6452521 B1 US 6452521B1
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circuit
sensor
charge
integrator
charge packet
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US09/808,516
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Feng Wang
Michael J. Gaboury
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Rosemount Inc
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Rosemount Inc
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Assigned to ROSEMOUNT INC. reassignment ROSEMOUNT INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GABOURY, MICHAEL J., WANG, FENG
Priority to DE10211374.2A priority patent/DE10211374B4/de
Priority to JP2002070247A priority patent/JP3917441B2/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/478—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication

Definitions

  • This invention relates to analog-to-digital converters used in industrial process control transmitters, and particularly to mapping an analog input range of a delta-sigma converter to the output range of an analog sensor.
  • A/D converters that convert the analog output of a sensor to a digital output.
  • A/D converters generate a combination of duty cycle, timing, frequency or pulse counts that digitally represent the output of the sensor.
  • One known type of A/D converter is a delta-sigma circuit, also known as sigma-delta, ⁇ , and ⁇ circuits.
  • Delta-sigma converters are balanced A/D converter circuits that are distinguished from other balanced A/D circuits by the provision of a balancing current to an integrator. The polarity of the balancing current is controlled by a clocked controller.
  • the delta-sigma circuit is capable of producing high accuracy, high resolution analog-to-digital conversions over its analog input range.
  • Delta-sigma circuits are often employed in industrial process control transmitters to convert an analog signal from the sensor to a digital signal so that information concerning the process variable can be transmitted to a central station remotely located from the transmitter.
  • a sensor such as a strain gauge
  • a strain gauge operates to provide an output having a range between 0 volts and some maximum sensor voltage (+Vmax), whereas the delta-sigma converter provides an output that ranges between a negative maximum voltage and a positive maximum voltage.
  • Vmax some maximum sensor voltage
  • the delta-sigma converter provides an output that ranges between a negative maximum voltage and a positive maximum voltage.
  • a method and circuit are needed that allow an analog sensor with a low level or offset analog output to be coupled directly to a delta-sigma converter having a higher level input range, to utilize substantially the full range of the delta-sigma converter without the inaccuracies of analog amplifying and offsetting circuits.
  • a delta-sigma converter includes a mapping circuit coupled to the integrator circuit to map the analog input range of the integrator to the analog output range of the sensor.
  • an integrator circuit has an analog input range and provides an integrator output to a controller to generate a digital output.
  • the digital output is in a digital output range representing the analog input range.
  • a sensor input circuit includes a sensor having an analog sensor output range.
  • the mapping circuit is coupled to the integrator circuit and is responsive to control signals from the controller to map the analog input range to the analog sensor range.
  • the integrator circuit has at least two differentially arranged inputs.
  • the sensor input circuit includes a pair of charge packet generators each coupled to a sensor capacitor to supply charges of opposite polarity to the integrator circuit inputs.
  • the mapping input circuit includes a pair of charge packet generators each having a mapping capacitor and arranged to alter the charge supplied by the sensor first charge packet generators to adjust the scale of the integrator analog input range to the analog output range of the sensors.
  • a reference circuit provides a reference charge for the integrator inputs.
  • FIG. 1 is a block diagram of an industrial process control transmitter employing a delta-sigma converter according to the present invention.
  • FIG. 2 is a circuit diagram of a portion of a delta-sigma converter described in the aforementioned Gaboury application.
  • FIG. 3 is a timing diagram of the operation of the switches in a delta-sigma converter.
  • FIG. 4 is a block diagram of the sensor and delta-sigma converter according to the present invention.
  • FIG. 5 is a circuit diagram of a portion of the sensor and delta-sigma converter shown in FIG. 4 .
  • FIG. 1 is a block diagram of a process variable transmitter 20 arranged to monitor one or more process variables 22 and generate one or more outputs 26 representing the sensed process variable.
  • Transmitter outputs 26 are configured for transmission over long distances via a communications bus 28 .
  • Transmitter 20 includes a sensor 24 configured to monitor process variables 22 associated with fluids, such as slurries, liquids, vapors and gasses in industrial processing plants, such as chemical, pulp, petroleum, gas, pharmaceutical, food and other fluid processing plants.
  • Process variables of such fluids that are monitored include pressure, strain, temperature, flow, level, pH, conductivity, turbidity, density, concentration, chemical composition and other properties of the fluids.
  • Communication bus 28 may be a 4-20 ma current loop that powers the transmitter, or a FieldBus connection, a HART protocol communication or a fiber optic connection to a controller, a control system or a read-out (not shown).
  • a fieldBus connection a HART protocol communication or a fiber optic connection to a controller, a control system or a read-out (not shown).
  • power In transmitters powered by a two-wire communication loop 28 , power must be maintained at a low level. to provide safety in explosive atmospheres. Circuits that conserve energy, such as delta-sigma circuits, are especially desirable when such low power is employed.
  • Transmitter 20 includes an analog-to-digital converter (A/D) converter circuit 30 of the type known as a delta-sigma circuit.
  • A/D analog-to-digital converter
  • delta-sigma circuits means circuits that generate an alternating polarity balancing current to an integrator under the control of a clocked controller.
  • delta-sigma A/D circuit 30 includes a delta-sigma modulator 48 having an integrator input 36 coupled to receive an analog signal V DC from sensor 24 representative of the monitored process variable.
  • Clock 34 generates a clock output. at frequency f S to controller 32 .
  • Controller 32 is coupled to modulator 48 to generate a converted digital output 38 that digitally represents the analog signal V DC .
  • output 38 of controller 32 generates two pulse counts N 1 and N 2 such that the quantity N 1 (N 1 +N 2 ) represents the sensed process variable.
  • the output 38 of delta-sigma A/D converter circuit 30 is coupled to digital processor 46 that processes the digital signal and conditions the processed signal for transmission at output 26 in a formatting compatible to communication bus 28 .
  • offset circuit 40 and reference 52 may be coupled to modulator 48 to offset noise frequency from the baseband of signals from sensor 24 . Such an offset circuit and reference are fully described in the aforementioned Gaboury application.
  • FIG. 2 illustrates a portion of a delta-sigma modulator 48 described in the aforementioned Gaboury application.
  • Modulator 48 comprises an integrator 80 and charge packet generators 82 .
  • delta-sigma modulator 48 may include a plurality of modulator stages, each including an integrator 80 and one or more charge packet generators 82 .
  • Each charge packet circuit 82 is coupled to differential inputs 84 of modular differential amplifier 86 to derive a differential output 88 .
  • the input and output of amplifier 86 are complimentary type signals.
  • charge packet generators 90 and 91 charge and discharge sensor capacitors 94 and 96 of sensor 24 .
  • Sensor capacitors 94 and 96 are each responsive to the process variable to store an electrical charge during a first phase ⁇ 1 representative of the process variable at respective locations in the process plant.
  • Sensor capacitors may, for example, be differential capacitors arranged to measure the difference in the process variable between two locations in the plant.
  • Switches 98 and 102 operate to charge sensor capacitor 94 positively and to charge sensor capacitor 96 negatively during a first phase ⁇ 1 .
  • Switches 100 and 104 operate to transfer the charge on capacitors 94 and 96 to respective inputs to amplifier 86 of integrator stage 80 during a second phase ⁇ 2 .
  • phase ⁇ 1 and ⁇ 2 are mutually exclusive portions of a charge cycle 60 .
  • each phase ⁇ 1 and ⁇ 2 ends before the next phase begins.
  • Charge packet generator 92 includes reference capacitor 120 coupled through switch 124 to a positive reference voltage V RP of reference voltage source 132 and through switch 126 to a negative reference voltage V RN Of source 132 .
  • charge packet generator 93 includes reference capacitor 122 coupled through switch 128 to positive reference voltage V RP and through switch 130 to negative reference voltage V RN .
  • Switches 124 and 128 . are operated to conduction during one phase of each cycle and switches 126 and 130 are operated to conduction during the other phase of each cycle; which pair of switches operates depends or the positive or negative value of the previous output y at output 88 during the previous cycle.
  • Controller 32 includes switch controller 56 that is operated by the output 88 of amplifier 86 to provide control signals ⁇ 1 , ⁇ 2 , y ⁇ 1 , y ⁇ 2 , ⁇ overscore (y) ⁇ 1 , ⁇ overscore (y) ⁇ 2 . Consequently, during the first phase ⁇ 1 the charge transferred to integrator 80 is
  • the total charge transferred is a balanced charge representing the difference of Q ⁇ 1 and Q ⁇ 2 ,
  • input circuit 50 is coupled to sensor 24 , consisting of capacitors 90 and 92 , to provide input to integrator 80 .
  • Reference circuit 52 consisting of charge packet generators 92 and 93 and their accompanying reference capacitors 120 and 122 , is coupled to integrator 80 .
  • a mapping circuit 58 maps the input to integrator 80 to the full range of integrator 80 .
  • the output 88 of integrator 80 is supplied to delta-sigma controller 32 , which includes switch control 56 to supply control signals ⁇ 1 , ⁇ 2 , y ⁇ 1 , y ⁇ 2 , ⁇ overscore (y) ⁇ 1 , ⁇ overscore (y) ⁇ 2 to input circuit 50 , reference circuit 52 , mapping circuit 58 and integrator 80 .
  • FIG. 5 illustrates the delta-sigma converter of FIG. 4 in greater detail.
  • mapping circuit 58 includes mapping capacitors 134 and 136 and associated charge packet generators 138 and 139 .
  • Charge packet generator 138 includes switches 140 and 142 coupling mapping capacitor 134 to the negative reference voltage V RN and positive reference voltage V RP , respectively, of reference voltage source 132 .
  • charge packet generator 139 includes switches 144 and 146 coupling mapping capacitor 136 to voltage V RN and to voltage V RP , respectively. Switches 142 and 146 are operated to conduction during phase ⁇ 1 , and switches 140 and 144 are operated to conduction during phase ⁇ 2 of each cycle.
  • mapping capacitors 134 and 136 are charged oppositely of respective capacitors 94 and 96 , respectively, to thereby subtract from the charge on respective capacitors 94 and 96 . Consequently, the charge transferred to integrator 80 is
  • the values of the capacitances of the reference capacitors 120 . and 122 and of the mapping capacitors 134 and 136 and the voltage values of voltage sources 118 and 132 are selected such that the charges transferred to differential amplifier 86 by each of the reference capacitors 120 and 122 and the mapping capacitors 134 and 135 is one-half of the charge transferred by each of the sensor capacitors 94 and 96 . Conveniently, this is accomplished by establishing voltage source 118 equal to voltage source 132 and setting the capacitance of capacitors reference capacitors 120 and 122 and mapping capacitors 134 and 136 equal to about one-half the nominal capacitance of each of sensor capacitors 94 and 96 .
  • each reference and mapping capacitor provides a capacitance of one-half the expected capacitance of each sensor capacitor.
  • C MAP and C REF both equal to C IN /2
  • the midpoint of the charge packet generator range is set to 0 volts for the integrator stage of the delta-sigma converter and places the range of the sensor extends over the full range of the converter between ⁇ (V RP ⁇ V RN ) and +(V RP ⁇ V RN ).
  • mapping circuit 58 adjusts the flow of charge from input circuit 50 to integrator circuit 80 to scale the analog input range of the integrator to the analog output range of sensor 40 .
  • charge packet generators 138 and 139 supply charges that are opposite in polarity and one-half of the value of the charges supplied by the sensor charge packet generators 90 and 91 to translate the analog input range of integrator 80 for the sensor. Consequently, the present invention utilizes the full range of the delta-sigma converter without the use or inaccuracies of analog amplifying and offsetting circuits.
US09/808,516 2001-03-14 2001-03-14 Mapping a delta-sigma converter range to a sensor range Expired - Lifetime US6452521B1 (en)

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Application Number Priority Date Filing Date Title
US09/808,516 US6452521B1 (en) 2001-03-14 2001-03-14 Mapping a delta-sigma converter range to a sensor range
DE10211374.2A DE10211374B4 (de) 2001-03-14 2002-03-14 Abbildung eines Delta-Sigma-Wandlerbereichs auf einen Sensorbereich
JP2002070247A JP3917441B2 (ja) 2001-03-14 2002-03-14 センサレンジに対するデルタ・シグマ変換器レンジのマッピング方法

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