US6240106B1 - Retiming arrangement for SDH data transmission system - Google Patents

Retiming arrangement for SDH data transmission system Download PDF

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Publication number
US6240106B1
US6240106B1 US08/945,898 US94589897A US6240106B1 US 6240106 B1 US6240106 B1 US 6240106B1 US 94589897 A US94589897 A US 94589897A US 6240106 B1 US6240106 B1 US 6240106B1
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data
signal
store
phase
clock signal
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Iain J Slater
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GPT Ltd
Ericsson AB
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Marconi Communications Ltd
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Assigned to ERICSSON AB reassignment ERICSSON AB ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: M(DGP1) LTD
Assigned to M(DGP1) LTD reassignment M(DGP1) LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MARCONI UK INTELLECTUAL PROPERTY LTD.
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Definitions

  • the present invention relates to a retiming arrangement for use in an SDH (Synchronous Digital Hierarchy) data transmission system.
  • SDH Serial Digital Hierarchy
  • the invention is concerned with the provision of an arrangement by which third parties wishing to use an SDH link which is controlled by another operator may carry their own timing and other information across that network.
  • Third party timing is defined when the timing to be carried in a primary rate signal originates from a source which is not synchronous with the source used to time the SDH network. Third party timing is therefore plesiochronous to the bearer clock.
  • SDH Synchronous Transport Modules
  • VC virtual containers
  • TU tributary units
  • Many of these TU's are multiplexed together into a single STM-N.
  • the STM-N is demultiplexed and demapped back into primary rate signals.
  • the key component in SDH systems used to reduce these distortions is the so-called desynchronizer or retiming arrangement.
  • the present invention arose in an attempt to improve the system disclosed in our co-pending British patent application 9114841.1, published as GB 2257603A on Jan. 13, 1993, the contents of which are hereby incorporated into this application by this reference.
  • the aim of the present invention is to permit third parties using their own primary rate timing source to carry timing information over an SDH network which is operated by a first party. This is not currently possible and as shown in FIG. 1B of the above mentioned document a separate channel needs to be provided to carry this timing information.
  • the invention provides a retiming arrangement for an SDH (Synchronized Digital Hierarchy) data transmission system by which third parties may use an SDH link, comprises an input ( 5 ) for receipt of a multiplexed STM (Synchronous Transport Module) a signal, a clock recovery circuit ( 20 ) for recovering a clock signal from the STM signal, a demultiplexer ( 21 ) for demultiplexing the STM signal into a plurality of TU (Tributary Unit) signals, a pointer processor ( 25 ) for reading pointer data from a TU signal, a bit dejustifier ( 28 ) for reading bit justification data from the TU signal, a buffer store ( 30 ) with a store monitor ( 34 ) in which store ( 30 ) the processor TU data is stored temporarily before being clocked out at a retimed clock rate, wherein said retiming arrangement is characterised in that means ( 32 ) for generating the retimed clock signal ( 31 ), are provided,
  • FIG. 1 shows schematically an SDH network together with a third party user
  • FIG. 2 is a block diagram illustrating a retiming arrangement according to the invention.
  • an SDH network comprises a network timing source 1 which feeds an, e.g., 2 MHz signal into an exchange 2 .
  • the exchange feeds 2 Mbit signals over N, two as shown, signal connections 3 into an SDH multiplexer 4 .
  • the multiplexed STM-N signal is then fed over an SDH bearer 5 to an SDH demultiplexer 6 .
  • the exchange 2 is also connected to the SDH multiplexer 4 by a control line 7 which synchronizes the bearer 5 at the 2 MHz clock rate.
  • the signal is converted back into the 2 Mbit/s primary rate format and fed over lines 8 to an exchange 9 .
  • a line 10 corresponding to line 7 is provided for deriving timing information from the bearer.
  • a third party user can use the SDH network for conveying timing and other data from a private network 11 .
  • a private timing source 10 which is not synchronous with the network timing source 1 , transmits timing signals, i.e. primary rate signals at 1.544Mbit/s or 2.048 Mbit/s through a link 12 to the SDH multiplexer 4 . After demultiplexing the timing signals are conveyed along line 13 to the private network 14 . It can be seen that by comparing FIG. 1 to FIG. 1 b of our copending British application mentioned previously that the timing information from the third party had in the past to be carried along a separate link.
  • a multiplexed STM-N signal is input firstly to a clock recovery circuit 20 where a so called ‘TO’ clock signal is stripped off on to line 23 .
  • the multiplexed signal is then passed to a demultiplexer 21 where it is demultiplexed into N low order signals, so called TU-11 or TU12 data dependent on the bit rate of the primary signals (1.544 Mbit/s or 2.048 Mbit/s respectively).
  • N primary rate signals 22 is then passed to a retiming arrangement.
  • the TU data is firstly passed to a pointer processor 25 .
  • the pointer processor is part of the high order path adaptation (HPA) and functions to interpret differences in phase and frequency between the clocks at the point of insertion and point of extraction of the SDH network, which are encoded by the TU pointer.
  • HPA high order path adaptation
  • “Pointers” are described in more detail in our co-pending British application referred to previously.
  • each virtual container or VC signal is allowed to float within the aggregate stream of bytes, such that the starting point of the VC within the overall SDH signal can change from one signals' successive frame to another.
  • the pointer value determines the start point of the particular VC.
  • the pointer processor 25 receives an enable signal on line 26 which functions as a dynamic flag to indicate whether the data in any particular TU signal is true or real data, as opposed to being an overhead.
  • the resulting VC data is transferred to a bit dejustifier 28 which forms part of the low order path overhead (LPA).
  • LPA low order path overhead
  • Bit justification is defined within CCITT standards. In essence bit justification data provides a means of indicating where a 2 Mbit data signal is located within a VC. For example at the point of injection into the system there may be more traffic data than can be accommodated within the byte space allocated for that purpose. Any overflow may be accommodated within the justification overhead bytes. Bit justification is used to provide a means of indicating that traffic data is located within the justification overhead bytes and that this needs to be retrieved before the signal can be sent on for further processing. Following bit dejustification the remaining data is passed to an elastic store 30 where temporary phase transients due to gaps caused by the extraction of overhead and justification bytes are absorbed. The primary rate signal 29 , retimed by means to be described is then read out of the elastic store on lines 8 or 13 , using the numbering shown in FIG. 1 .
  • a phase locked loop 32 is operative to take as an input the bearer reference TO clock signal recovered at stage 20 and to output a modified read clock signal for use in retiming data out of the elastic store 30 .
  • the read clock signal 31 can be derived in any one of a number of ways.
  • the phase lock loop 32 includes three phase adjust inputs ⁇ 1 , ⁇ 2 and ⁇ 3 . These are connected to the pointer processor 25 , bit dejustifier 28 and a store monitor 34 respectively. Which, or what combination of input are used is controlled by a mode selector 36 which operates respective switches for each of the phase adjust inputs.
  • a first mode the ⁇ 3 input is selected and the store monitor 34 is arranged to ensure that the elastic store 30 remains half filled such that the rate of the data leaving the store equals the rate at which it is entering the store. In this way the primary rate timing signal can be accurately reproduced.
  • phase inputs ⁇ 1 and ⁇ 2 are selected, with ⁇ 3 being disabled.
  • the recovered bearer clock on line 23 is used directly with phase adjustments being made by the pointer processor 25 and bit dejustifier 28 .
  • the invention offers a means by which the effects of TU-1 pointer changes can be eliminated leaving the output phase response of the desynchronizer to be comparable with that of bit dejustification.
  • the mode selector 36 is operated such that, in normal third party operation, only the ⁇ 2 input is enabled such that only bit dejustification data is used to adjust the TO clock frequency. While as shown the ⁇ 1 input is disabled, in an alternative arrangement the PLL may be operative to respond to ⁇ 1 adjustments, but to cancel each occurrence with one of equal size and of opposite polarity. Thus operation is in similar manner as a PDH demultiplexer. As a safeguard, input ⁇ 3 is also enabled, but the store monitor 34 and elastic store 30 are operated in a different way as will now be described.
  • any temporary loss of synchronization or large amounts of wander in the SDH network will be accommodated within the elastic store 30 .
  • This is designed to be relatively large, typically in excess of 40 microseconds to accommodate the maximum permitted wander in an SDH path. If SDH network synchronization is lost for a long period of time the effect would eventually be an underflow or overflow of the elastic store 30 .
  • the store monitor 34 would then initiate a leak out of phase to recover capacity in the elastic store 32 .
  • the store monitor 34 operates in a different way to that described with reference to normal, or non third-party use.
  • the capacity could be recovered by reverting the desynchronize operation temporarily back to one of the fist two modes—i.e. using only the store monitor on the ⁇ 3 input or adjustment using both ⁇ 1 and ⁇ 2 for a limited period of time.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
US08/945,898 1995-05-05 1996-05-03 Retiming arrangement for SDH data transmission system Expired - Lifetime US6240106B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9509216 1995-05-05
GBGB9509216.9A GB9509216D0 (en) 1995-05-05 1995-05-05 Retiming arrangement for SDH data transmission system
PCT/GB1996/001071 WO1996035275A1 (fr) 1995-05-05 1996-05-03 Dispositif de resynchronisation pour systeme de transmission de donnees a hierarchie numerique synchrone

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US (1) US6240106B1 (fr)
EP (1) EP0824807B1 (fr)
JP (1) JP3656140B2 (fr)
CN (1) CN1084989C (fr)
AU (1) AU704293B2 (fr)
DE (1) DE69611611T2 (fr)
ES (1) ES2153572T3 (fr)
GB (2) GB9509216D0 (fr)
NO (1) NO975088L (fr)
RU (1) RU2155452C2 (fr)
UA (1) UA45398C2 (fr)
WO (1) WO1996035275A1 (fr)

Cited By (6)

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Publication number Priority date Publication date Assignee Title
US6389553B1 (en) * 1998-05-26 2002-05-14 Nortel Networks Limited Redundant link delay maintenance circuit and method
US20020075908A1 (en) * 2000-10-31 2002-06-20 Lg Electronics Inc. Apparatus for establishing path in synchronous digital hierarchy system and method thereof
US6526069B1 (en) * 1998-02-06 2003-02-25 Alcatel Synchronization device for a synchronous digital message transmission system and process for producing a synchronous output signal
US20040037290A1 (en) * 2002-08-08 2004-02-26 Yoav Valadarsky Switching device for telecommunication networks
US7286567B1 (en) * 1998-08-28 2007-10-23 Siemens Aktiengesellschaft Telecommunications system, and methods for transmitting data, and telecommunication system synchronization method
US20160127064A1 (en) * 2013-06-03 2016-05-05 Zte Corporation Clock Data Recovery Method and Device for Branch Signal in SDH

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FI965072A (fi) 1996-12-17 1998-08-13 Nokia Telecommunications Oy Menetelmä tasaustapahtumien aiheuttamien transienttien vaimentamiseksi desynkronisaattorissa
CN1315280C (zh) * 2001-05-15 2007-05-09 华为技术有限公司 Sdh指针处理方法及电路
US7286568B2 (en) * 2002-09-03 2007-10-23 Intel Corporation Techniques to generate a clock signal
IL152314A (en) * 2002-10-16 2007-07-04 Eci Telecom Ltd Handling traffic in a synchronous communication network
CN1841978B (zh) * 2005-04-01 2011-09-14 大唐电信科技股份有限公司 实现多路信号再定时的方法及装置
CN105356995B (zh) * 2015-11-24 2018-06-26 山东胜开电子科技有限公司 一种同步码双向恢复方法及电路

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6526069B1 (en) * 1998-02-06 2003-02-25 Alcatel Synchronization device for a synchronous digital message transmission system and process for producing a synchronous output signal
US6389553B1 (en) * 1998-05-26 2002-05-14 Nortel Networks Limited Redundant link delay maintenance circuit and method
US7286567B1 (en) * 1998-08-28 2007-10-23 Siemens Aktiengesellschaft Telecommunications system, and methods for transmitting data, and telecommunication system synchronization method
US20020075908A1 (en) * 2000-10-31 2002-06-20 Lg Electronics Inc. Apparatus for establishing path in synchronous digital hierarchy system and method thereof
US6970463B2 (en) * 2000-10-31 2005-11-29 Lg Electronics Inc. Apparatus for establishing path in synchronous digital hierarchy system and method thereof
US20040037290A1 (en) * 2002-08-08 2004-02-26 Yoav Valadarsky Switching device for telecommunication networks
US7339936B2 (en) * 2002-08-08 2008-03-04 Eci Telecom Ltd. Switching device for telecommunication networks
US20160127064A1 (en) * 2013-06-03 2016-05-05 Zte Corporation Clock Data Recovery Method and Device for Branch Signal in SDH
US9680585B2 (en) * 2013-06-03 2017-06-13 Zte Corporation Clock data recovery method and device for branch signal in SDH

Also Published As

Publication number Publication date
GB9509216D0 (en) 1995-06-28
CN1183867A (zh) 1998-06-03
EP0824807A1 (fr) 1998-02-25
RU2155452C2 (ru) 2000-08-27
DE69611611T2 (de) 2001-05-03
JP3656140B2 (ja) 2005-06-08
AU704293B2 (en) 1999-04-15
EP0824807B1 (fr) 2001-01-17
WO1996035275A1 (fr) 1996-11-07
CN1084989C (zh) 2002-05-15
AU5509696A (en) 1996-11-21
UA45398C2 (uk) 2002-04-15
NO975088L (no) 1998-01-05
GB2300543A (en) 1996-11-06
JPH11505079A (ja) 1999-05-11
NO975088D0 (no) 1997-11-04
DE69611611D1 (de) 2001-02-22
GB2300543B (en) 1999-10-06
GB9609632D0 (en) 1996-07-10
ES2153572T3 (es) 2001-03-01

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