FI965072A - Menetelmä tasaustapahtumien aiheuttamien transienttien vaimentamiseksi desynkronisaattorissa - Google Patents

Menetelmä tasaustapahtumien aiheuttamien transienttien vaimentamiseksi desynkronisaattorissa Download PDF

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Publication number
FI965072A
FI965072A FI965072A FI965072A FI965072A FI 965072 A FI965072 A FI 965072A FI 965072 A FI965072 A FI 965072A FI 965072 A FI965072 A FI 965072A FI 965072 A FI965072 A FI 965072A
Authority
FI
Finland
Prior art keywords
desynchronizer
smoothing
events
transients caused
damping
Prior art date
Application number
FI965072A
Other languages
English (en)
Swedish (sv)
Other versions
FI965072A0 (fi
Inventor
Reino Urala
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to FI965072A priority Critical patent/FI965072A/fi
Publication of FI965072A0 publication Critical patent/FI965072A0/fi
Priority to US09/331,218 priority patent/US6587533B1/en
Priority to AU53989/98A priority patent/AU5398998A/en
Priority to PCT/FI1997/000788 priority patent/WO1998031117A2/en
Priority to GB9913224A priority patent/GB2335331B/en
Priority to DE19782196T priority patent/DE19782196T1/de
Publication of FI965072A publication Critical patent/FI965072A/fi

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
FI965072A 1996-12-17 1996-12-17 Menetelmä tasaustapahtumien aiheuttamien transienttien vaimentamiseksi desynkronisaattorissa FI965072A (fi)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FI965072A FI965072A (fi) 1996-12-17 1996-12-17 Menetelmä tasaustapahtumien aiheuttamien transienttien vaimentamiseksi desynkronisaattorissa
US09/331,218 US6587533B1 (en) 1996-12-17 1997-12-16 Method for attenuating transients caused by aligning in a desynchronizer
AU53989/98A AU5398998A (en) 1996-12-17 1997-12-16 Method for attenuating transients caused by aligning in a desynchronizer
PCT/FI1997/000788 WO1998031117A2 (en) 1996-12-17 1997-12-16 Method for attenuating transients caused by aligning in a desynchronizer
GB9913224A GB2335331B (en) 1996-12-17 1997-12-16 Method for attenuating transients caused by aligning in a desynchronizer
DE19782196T DE19782196T1 (de) 1996-12-17 1997-12-16 Verfahren zum Dämpfen von durch Justierereignisse in einem Desynchronisator verursachten Transienten

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI965072A FI965072A (fi) 1996-12-17 1996-12-17 Menetelmä tasaustapahtumien aiheuttamien transienttien vaimentamiseksi desynkronisaattorissa

Publications (2)

Publication Number Publication Date
FI965072A0 FI965072A0 (fi) 1996-12-17
FI965072A true FI965072A (fi) 1998-08-13

Family

ID=8547300

Family Applications (1)

Application Number Title Priority Date Filing Date
FI965072A FI965072A (fi) 1996-12-17 1996-12-17 Menetelmä tasaustapahtumien aiheuttamien transienttien vaimentamiseksi desynkronisaattorissa

Country Status (6)

Country Link
US (1) US6587533B1 (fi)
AU (1) AU5398998A (fi)
DE (1) DE19782196T1 (fi)
FI (1) FI965072A (fi)
GB (1) GB2335331B (fi)
WO (1) WO1998031117A2 (fi)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929699A (en) * 1997-12-15 1999-07-27 National Semiconductor Corporation Integrated active integrator filter with compensated unity gain bandwidth
CN100353671C (zh) * 2004-05-26 2007-12-05 华为技术有限公司 时钟合成方法及系统

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2759457B2 (ja) 1988-05-13 1998-05-28 住友製薬株式会社 抗腫瘍性蛋白質
FR2668323B1 (fr) 1990-10-17 1993-01-15 Telecommunications Sa Dispositif de reduction de la gigue due aux sauts de pointeurs dans un reseau de telecommunications numeriques.
FI90709C (fi) 1992-02-14 1994-03-10 Nokia Telecommunications Oy Järjestely osoitinvärinän vaimentamiseksi desynkronisaattorissa
FI95636C (fi) 1992-02-14 1996-02-26 Nokia Telecommunications Oy Desynkronisaattori ja menetelmä osoitinvärinän vaimentamiseksi desynkronisaattorissa
US5404380A (en) * 1992-08-25 1995-04-04 Alcatel Network Systems, Inc. Desynchronizer for adjusting the read data rate of payload data received over a digital communication network transmitting payload data within frames
EP0630127B1 (en) 1993-06-18 1999-01-13 Alcatel Digital phase locked loop arrangement
US5497405A (en) 1993-07-01 1996-03-05 Dsc Communications Corporation Open loop desynchronizer
US5457717A (en) * 1993-11-29 1995-10-10 Dsc Communications Corporation Apparatus and method for eliminating mapping jitter
EP0727887B1 (de) 1995-02-16 2002-08-28 Alcatel Stopfeinrichtung für synchrones digitales Übertragungssystem
US5680422A (en) * 1995-04-27 1997-10-21 Adtran Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
GB9509216D0 (en) 1995-05-05 1995-06-28 Plessey Telecomm Retiming arrangement for SDH data transmission system
US6229863B1 (en) * 1998-11-02 2001-05-08 Adc Telecommunications, Inc. Reducing waiting time jitter

Also Published As

Publication number Publication date
FI965072A0 (fi) 1996-12-17
DE19782196T1 (de) 1999-11-25
GB9913224D0 (en) 1999-08-04
WO1998031117A2 (en) 1998-07-16
WO1998031117A3 (en) 1998-09-11
GB2335331B (en) 2001-03-14
GB2335331A (en) 1999-09-15
AU5398998A (en) 1998-08-03
US6587533B1 (en) 2003-07-01

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