US5939754A - Power MOSFET having a drain heterojunction - Google Patents

Power MOSFET having a drain heterojunction Download PDF

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US5939754A
US5939754A US08/925,048 US92504897A US5939754A US 5939754 A US5939754 A US 5939754A US 92504897 A US92504897 A US 92504897A US 5939754 A US5939754 A US 5939754A
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drain
region
power mosfet
base regions
semiconductor
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Masakatsu Hoshi
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • the present invention relates to a field effect transistor and, more particularly, provides a technology directed toward lowering the on-resistance of a power MOSFET having a high breakdown voltage.
  • FIG. 1 As a lateral power MOSFET in the prior art, a structure shown in FIG. 1, for example, has been known.
  • a high impurity concentration n + -type Si buried layer 3 is formed between a p-type silicon (abbreviated as "Si" hereinafter) substrate 1 and a p-type Si epitaxial layer 2.
  • An n-type Si drain region 4 is formed in the p-type Si epitaxial layer 2 to be connected to the high impurity concentration n + -type Si buried layer 3.
  • P-type Si base regions (channel regions) 5 and a high impurity concentration n + -type Si drain region 18 are formed in the n-type Si drain region 4.
  • n + -type Si source regions 6 are formed in the p-type Si base region 5.
  • a gate electrode 11 made of polysilicon is formed on the p type Si base region 5 and a part of the n-type Si drain region 4 via a gate oxide film 7.
  • a source electrode 12 is formed to be isolated from the gate electrode 11 by a first interlayer film 9.
  • a drain electrode 13 is formed to be isolated from the source electrode 12 by a second interlayer film 10.
  • a predetermined potential e.g., a positive potential is applied to the gate electrode 11 under the condition that a voltage is applied between the drain electrode 13 and the source electrode 12
  • an n-type inversion layer is formed on a surface of the p-type Si base region 5 immediately below the gate electrode 11 so that a drain current is passed from the drain electrode 13 to the source electrode 12.
  • a predetermined potential e.g., a positive potential
  • a negative potential is applied to the gate electrode 11
  • such n-type inversion layer disappears so that the lateral power MOSFET becomes an OFF state.
  • a breakdown voltage V B has a relation with an impurity concentration N d , as expressed by Eq.(1) deduced in compliance with a one-dimensional approximation model.
  • a width W of the depletion layer at breakdown can be expressed by
  • a resistance R d of a semiconductor region having a unit sectional area and a length W can be given by
  • ⁇ n is the electron mobility in bulk of respective semiconductor materials.
  • the impurity concentration of the n-type Si drain region 4 becomes 1.7 ⁇ 10 15 cm -3 based on Eq.(4).
  • the distance W between the p type Si base region 5 and the high impurity concentration n + -type Si drain region 18, 12.5 ⁇ m is needed from Eq.(5).
  • the drain resistance R d becomes a large value such as 3.4 ⁇ 10 -3 ⁇ cm 2 from Eq.(3).
  • the drain resistance R d becomes a larger value.
  • a structurally determined breakdown voltage and a correlative value of on-resistance can be derived in the power MOSFET in the prior art, both the breakdown voltage and the on-resistance being insufficient respectively.
  • the present invention has been made to overcome the above problems and it is an object of the present invention to provide a power MOSFET which is capable of reducing an on-resistance while maintaining a high breakdown voltage between source and drain regions.
  • a first aspect of the present invention is that the power MOSFET having a plurality of base regions, source regions formed in the base regions and a drain region formed between the base regions, wherein the drain region has a convex portion and at least a part of the convex portion is formed of wide bandgap semiconductor which has a wider bandgap rather than other portion.
  • the power MOSFET of the present invention has a hetero junction consisting of wide bandgap semiconductor and another semiconductor having a bandgap narrower than that of the wide bandgap semiconductor in the drain region.
  • the convex drain regions and at least a part of the convex drain regions is formed of wide bandgap semiconductor, the higher breakdown voltage and the lower on-resistance can be achieved simultaneously. More particularly, if the drain resistance which is the major component of the on-resistance is made smaller, the lower on-resistance and the higher breakdown voltage can be obtained simultaneously, which cannot be achieved by the power MOSFET in the prior art. In the power MOSFET according to the first aspect of the present invention, a trade-off curve between the breakdown voltage and the on-resistance comes closer to an origin.
  • the convex portions are formed to be sandwiched in between the gate electrodes via the insulating films so that a maximum electric field point can be located in the wide bandgap semiconductor so as to attain the higher breakdown voltage.
  • a second aspect of the present invention is concerned with a method for manufacturing the power MOSFET explained in the above first aspect of the present invention. More particularly, the second aspect of the present invention is a method for manufacturing the power MOSFET comprising the steps of (a) on a semiconductor region serving as a drain region, forming a wide bandgap semiconductor layer of same conductivity type as that of the semiconductor region and having a bandgap wider than that of the semiconductor region, and (b) removing a predetermined portion of the wide bandgap semiconductor layer and then forming convex wide bandgap drain regions made of the wide bandgap semiconductor layer in proximity to the semiconductor region. It has been well known that it is difficult to form the pn junction in the wide bandgap semiconductor such as SiC, etc. However, according to the method for manufacturing the power MOSFET, the power MOSFET having the higher breakdown voltage and the lower on-resistance can be manufactured extremely easily since no pn junction is provided in the wide bandgap semiconductor.
  • FIG. 1 is a sectional view showing an example of a lateral power MOSFET in the prior art
  • FIG. 2 is a sectional view showing a lateral power MOSFET according to a first embodiment of the present invention
  • FIG. 3 is a schematic sectional view showing potential distribution when the lateral power MOSFET shown in FIG. 2 is in OFF state;
  • FIGS. 4A to 4K are sectional views showing steps in a method for manufacturing the lateral power MOSFET according to the first embodiment of the present invention
  • FIG. 5 is a sectional view showing a lateral power MOSFET according to a second embodiment of the present invention.
  • FIG. 6 is a sectional view showing a power MOSFET according to a third embodiment of the present invention.
  • FIG. 7 is a circuit diagram showing an example of an electrode connection method in the power MOSFET according to the third embodiment of the present invention.
  • FIG. 8 is a sectional view showing a lateral power MOSFET according to another embodiment of the present invention.
  • FIG. 9 is a sectional view showing a lateral power MOSFET according to still another embodiment of the present invention.
  • FIG. 10 is a sectional view showing a power MOSFET according to yet still another embodiment of the present invention.
  • FIG. 2 is a sectional view showing a lateral power MOSFET according to a first embodiment of the present invention.
  • the high impurity concentration n + -type Si buried layer 3 is formed between the p-type Si substrate 1 and the p-type Si epitaxial layer 2.
  • an n-type semiconductor region acting as an n-type Si drain region 4 is formed in the p-type Si epitaxial layer 2 to be connected to the high impurity concentration n + -type Si buried layer 3.
  • p-type Si base regions 5 are formed in the n-type Si drain region 4.
  • High impurity concentration n + -type Si source regions 6 are formed in respective p-type Si base regions 5.
  • Gate electrodes 11 made of polysilicon are formed on the p type Si base region 5 and a part of the n-type Si drain region 4 via a gate oxide film 7 respectively.
  • n-type convex silicon carbide (SiC) drain regions 20 are protruded from the n-type Si drain region 4 to thus constitute wide bandgap drain regions respectively.
  • Insulating films 8 are formed on side walls of n-type convex silicon carbide (SiC) drain region 20 respectively.
  • each n-type SiC drain region 20 is sandwiched in between the gate electrodes 11 via the insulating films 8.
  • High impurity concentration n + -type SiC drain regions 21 each serving as a wide bandgap contact region are formed on top surfaces of the n-type SiC drain regions 20 respectively.
  • a first interlayer insulating film 9 is formed on the gate electrodes 11.
  • Source electrodes 12 are formed on the first interlayer insulating film 9.
  • Respective source electrodes 12 are also brought into contact with the n + -type Si source regions 6 and the p-type Si base region 5 via contact holes formed in the first interlayer Insulating film 9.
  • a second interlayer insulating film 10 is formed on the source electrodes 12.
  • a drain electrode 13 is formed on the second interlayer insulating film 10.
  • the n-type SiC drain regions 20 are connected to the drain electrode 13 via the high impurity concentration n + -type SiC drain regions 21 formed thereon respectively.
  • n-type inversion layer is formed on a surface of the p-type Si base region 5 directly below the gate electrode 11 and as a result a drain current is passed from the drain electrode 13 to the source electrode 12.
  • the gate electrode 11 is set to 0 V, such n-type inversion layer disappears so that the lateral power MOSFET blocks to flow the drain current. As a result, the lateral power MOSFET is brought into an OFF state.
  • An impurity concentration N d and a thickness of the n-type SiC drain region 20, if exemplified by the power MOSFET of 200 V class, can be obtained as 1.6 ⁇ 10 17 cm -3 and 1.2 ⁇ m in design respectively.
  • an accumulation layer of low resistance is formed by the gate voltage on the surface of the n-type Si drain region 4 just under the gate electrode 11. Therefore, a resistance of this area is negligibly small rather than the resistance of the n-type SiC drain region 20. Hence, it is enough to consider only the resistance of the n-type SiC drain region 20.
  • FIG. 3 is a schematic sectional view showing potential distribution when a high potential is applied between the drain and the source of the lateral power MOSFET shown in FIG. 1. Since the gate electrode 11 is fixed at 0 V, the depletion layer can easily extend from the n + -type Si source region 6 toward the n-type Si drain region 4 immediately below the gate electrode 11. In addition, since a metallurgical junction between the n-type Si drain region 4 and the n-type SiC drain region 20 is put between the gate electrodes 11, a potential in such junction region can be suppressed relatively small. Accordingly, a maximum electric field point is located in the n-type SiC drain region 20 and therefore the on-resistance can be reduced with maintaining the desired source-drain breakdown voltage.
  • a diffusion coefficient of impurity is low in the SiC semiconductor region. For this reason, a high temperature was required to activate the impurity in the SiC semiconductor and thus it was difficult to form a pn junction in the SiC semiconductor region.
  • no problem associated with impurity diffusion in the SiC semiconductor is caused in the present invention since the pn junction is formed in the Si semiconductor region.
  • manufacture of the lateral power MOSFET according to the first embodiment of the present invention can be made easy.
  • the high impurity concentration n + -type Si buried layer 3 having an impurity concentration of 10 18 to 10 20 cm -3 is formed by diffusing antimony (Sb) into a part of the p-type silicon substrate 1 by virtue of solid phase diffusion, for example. Then, according to the vapor phase epitaxial growth method which is performed at 1000 to 1200° C.
  • the p-type Si epitaxial layer 2 is formed on the n + -type Si buried layer 3 to have a thickness of 1 ⁇ m to several tens ⁇ m.
  • the n-type Si drain region 4 having an impurity concentration of 10 14 to 10 17 cm -3 is formed by doping n-type impurity into the p-type Si epitaxial layer 2 by virtue of ion implantation, or the like. Then, according to the chemical vapor deposition (CVD) which is carried out at 1200 to 1560° C.
  • CVD chemical vapor deposition
  • the n-type SiC drain region 20 serving as a wide bandgap drain region is formed to have an impurity concentration of 10 15 to 10 18 cm -3 and a thickness of 0.1 ⁇ m to several ⁇ m.
  • the high impurity concentration n + -type SiC drain region 21 serving as a wide bandgap contact region is formed.
  • Nitrogen (N 2 ) may be employed as an n-type dopant introduced into the SiC semiconductor.
  • an oxide film 14 is formed on the n + -type SiC drain region 21 by the CVD method, etc. Then, as shown in FIG. 4C, the oxide film 14 is patterned and the n + -type SiC drain region 21 and the n-type SiC drain region 20 are then selectively removed by the reactive ion etching (RIE) using this oxide film 14 as a mask to reach the n-type Si drain region 4. As a result, the n-type SiC drain regions 20 are formed to have a convex shape protruding from the n-type Si drain region 4, each having a cap layer of the n + -type SiC drain region 21.
  • RIE reactive ion etching
  • the insulating film 8 such as the oxide film is formed by the CVD method, etc. on the whole surface of the resultant structure having the convex shape.
  • the insulating films 8 are selectively left by directional etching such as the RIE on both side walls of the convex n-type SiC drain region 20.
  • the gate oxide film 7 of 10 nm to 200 nm thickness, for example, is formed on the surface of the n-type Si drain region 4.
  • the polysilicon film 19 of 100 nm to 700 nm thickness for example, is deposited by the CVD method, etc. on the gate oxide film 7.
  • the gate electrodes 11 are formed.
  • the polysilicon film 19 is delineated to have diffusion windows for forming the base regions. That is, the gate electrodes 11 act as diffusion masks.
  • the p-type impurity ions such as 11 B + are ion-implanted into the n-type Si drain region 4 via the diffusion windows, then the n-type impurity ions such as 75 As + are ion-implanted by use of another preselected mask delineating the source pattern as well as the diffusion windows, and then annealing is conducted.
  • the p-type Si base regions 5 each having the depth of 1 ⁇ m to 5 ⁇ m and the impurity concentration of 10 16 to 10 18 cm -3 , for example, and the high impurity concentration n + -type Si source regions 6 each having the depth of 0.1 ⁇ m to 1 ⁇ m and the impurity concentration of 10 18 to 10 21 cm -3 , for example, can be formed.
  • the first interlayer insulating film 9 is formed on surfaces of the gate electrodes 11 and so on, and source contact windows used to form the source electrodes are then formed in the first interlayer insulating film 9.
  • the metal film made of tungsten (W), molybdenum (Mo), aluminum (Al), aluminum-silicon alloy (Al--Si) or the like is then deposited on an overall surface by use of the electron beam (EB) evaporation method or the sputtering method.
  • the source electrodes 12 are then formed by the RIE method, etc. using a preselected mask pattern.
  • the second interlayer insulating film 10 is deposited on an overall surface including the surfaces of the n + -type SiC drain region 21 and the source electrode 12.
  • the second interlayer insulating film 10 is then selectively removed from only the surface areas of the high impurity concentration n + -type SiC drain regions 21 to thus form drain contact windows.
  • the lateral power MOSFET having the structure shown in FIG. 2 can be manufactured.
  • FIG. 5 is a sectional view showing a lateral power MOSFET according to a second embodiment of the present invention.
  • the lateral power MOSFET employing the p-type Si substrate 1 is shown in FIG. 5. More particularly, in FIG. 5, the p-type Si epitaxial layer 2 and the high impurity concentration n + -type Si buried layer 3 prescribed in the first embodiment (see, FIG. 2) are not provided, but the n-type Si drain regions 4 are formed locally in the vicinity of the surface of the p-type Si substrate 1 so as to be sandwiched by the p-type Si base regions 5. Remaining parts are similar to those in the first embodiment shown in FIG. 2 and therefore the description thereof will be omitted.
  • the impurity concentration of the n-type Si drain region 4 is selected so that the depletion layer extending from the base-drain boundary does not reach the n-type SiC drain region 20.
  • the impurity concentration of the n-type Si drain region 4 is selected so as not to cause "a punch-through" of the depletion layer in the n-type Si drain region 4. If the impurity concentration is selected like this, the high electric field can be prevented from being applied to the Si semiconductor region in the OFF state. As a result, the higher source-drain breakdown voltage can be easily accomplished.
  • FIG. 6 is a sectional view showing a power MOSFET according to a third embodiment of the present invention.
  • an n-type Si epitaxial layer 16 formed on a high impurity concentration n + -type Si substrate 15 is employed as an n-type Si drain region.
  • p-type Si base regions 5 are then formed in a surface area of the n-type Si drain region 16.
  • High impurity concentration n + -type Si source regions 6 are then formed in respective p-type Si base regions 5.
  • a gate electrode 11 made of polysilicon is then formed on the p-type Si base region 5 and a part of the n-type Si drain region 4 via the gate oxide film 7.
  • convex n-type SIC drain regions 20 are formed on a part of the n-type Si drain region 16.
  • the insulating films 8 are then formed on both sides of the convex n-type SIC drain region 20.
  • the convex n-type SIC drain region 20 is sandwiched by the gate electrodes 11 via the insulating films 8.
  • High impurity concentration n + -type SIC drain regions 21 are then formed on the surfaces of the n-type SIC drain regions 20 respectively.
  • the first interlayer insulating film 9 is then formed on the gate electrodes 11.
  • the source electrodes 12 are then formed on the first interlayer insulating film 9.
  • the second interlayer insulating film 10 is then formed on the source electrodes 12.
  • the first drain electrode 13 is formed to be isolated by the second interlayer insulating film 10.
  • the n-type SIC drain regions 20 are connected to the first drain electrode 13 via the high impurity concentration n + -type SIC drain regions 21 formed thereon.
  • a second drain electrode 17 is formed on a bottom surface of the high impurity concentration n + -type Si substrate 15 and is connected to the n-type Si drain region 16 via the n + -type Si substrate 15 having a low resistivity.
  • the cross-sectional area of current paths becomes wider because the current flows through two drain electrodes 13 and 17, so that the on-resistance can be made lower.
  • the drain voltage is divided by the resistor R1 and the resistor R2 and then a voltage which is lower than that applied between the first drain electrode and source electrode is applied between the second drain electrode and source electrode, the current mainly passes through the first drain electrode.
  • the n-type Si drain region is connected between the first and second drain electrodes, in which a lower potential than that of between the first drain and source electrodes, the higher breakdown voltage of the power MOSFET is easily obtained.
  • FIGS. 8 to 10 in which the gate electrodes 11 are formed locally around the base regions 5.
  • FIGS. 8, 9 and 10 correspond to FIGS. 2, 5 and 6 respectively.
  • a gate capacity can be reduced to thus make a higher speed operation possible.

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  • Condensed Matter Physics & Semiconductors (AREA)
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US08/925,048 1996-09-09 1997-09-08 Power MOSFET having a drain heterojunction Expired - Lifetime US5939754A (en)

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US20040058490A1 (en) * 2000-12-05 2004-03-25 Seiko Instruments Inc. Semiconductor device and method of manufacturing the same
US20040079989A1 (en) * 2002-10-11 2004-04-29 Nissan Motor Co., Ltd. Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same
US20050077583A1 (en) * 2001-10-29 2005-04-14 Power Integrations, Inc. Lateral power MOSFET for high switching speeds
US20050139914A1 (en) * 2003-12-19 2005-06-30 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
US20050176192A1 (en) * 2003-12-19 2005-08-11 Third Dimension (3D) Semiconductor, Inc. Planarization method of manufacturing a superjunction device
US20050181558A1 (en) * 2003-12-19 2005-08-18 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device with conventional terminations
US20050181577A1 (en) * 2003-12-19 2005-08-18 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device
US20050181564A1 (en) * 2003-12-19 2005-08-18 Third Dimension (3D) Semiconductor, Inc. Method for manufacturing a superjunction device with wide mesas
US7015104B1 (en) 2003-05-29 2006-03-21 Third Dimension Semiconductor, Inc. Technique for forming the deep doped columns in superjunction
US20060226494A1 (en) * 2004-12-27 2006-10-12 Third Dimension (3D) Semiconductor, Inc. Tungsten plug drain extension
US20060231915A1 (en) * 2004-12-27 2006-10-19 Third Dimension (3D) Semiconductor, Inc. Process for high voltage superjunction termination
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GB2317054A (en) 1998-03-11
JP3327135B2 (ja) 2002-09-24

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