US20090023260A9 - Technique for forming the deep doped columns in superjunction - Google Patents

Technique for forming the deep doped columns in superjunction Download PDF

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US20090023260A9
US20090023260A9 US11/343,329 US34332906A US2009023260A9 US 20090023260 A9 US20090023260 A9 US 20090023260A9 US 34332906 A US34332906 A US 34332906A US 2009023260 A9 US2009023260 A9 US 2009023260A9
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conductivity type
doped region
dopant
sidewall surface
trenches
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US7504305B2 (en
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Richard Blanchard
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Third Dimension 3D Semiconductor Inc
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Third Dimension 3D Semiconductor Inc
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • the present invention relates generally to semiconductor devices, and more, particularly, to power MOSFET devices.
  • Power MOSFET devices are employed in applications such as automobile electrical systems, power supplies, and power management applications. Such devices should sustain high voltage in the off-state while having a low voltage drop and high current flow in the on-state.
  • FIG. 1 illustrates a typical structure for an N-channel power MOSFET.
  • An Nepitaxial silicon layer 1 formed over an N + silicon substrate 2 contains P-body regions 5 a and 6 a , and N + source regions 7 and 8 for two MOSFET cells in the device.
  • P-body regions 5 and 6 may also include deep P-body regions 5 b and 6 b .
  • a source-body electrode 12 extends across certain surface portions of epitaxial layer 1 to contact the source and body regions.
  • the N-type drain for both cells is formed by the portion of N-epitaxial layer 1 extending to the upper semiconductor surface in FIG. 1 .
  • a drain electrode is provided at the bottom of N + substrate 2 .
  • An insulated gate electrode 18 typically of polysilicon lies primarily over the body and portions of the drain of the device, separated from the body and drain by a thin layer of dielectric, often silicon dioxide.
  • a channel is formed between the source and drain at the surface of the body region when the appropriate positive voltage is applied to the gate with respect to the source and body electrode.
  • the on-resistance of the conventional MOSFET shown in FIG. 1 is determined largely by the drift zone resistance in epitaxial layer 1 .
  • the drift zone resistance is in turn determined by the doping and the layer thickness of epitaxial layer 1 .
  • the doping concentration of epitaxial layer 1 must be reduced while the layer thickness is increased.
  • Curve 20 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET.
  • the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
  • FIG. 3 shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance.
  • This MOSFET is disclosed in paper No. 26.2 in the Proceedings of the IEDM, 1998, p. 683.
  • This MOSFET is similar to the conventional MOSFET shown in FIG. 2 except that it includes P-type doped regions 40 and 42 which extend from beneath the body regions 5 and 6 into the drift region of the device.
  • the P-type doped regions 40 and 42 define columns in the drift region that are separated by N-type doped columns, which are defined by the portions of the epitaxial layer 1 adjacent the P-doped regions 40 and 42 .
  • the alternating columns of opposite doping type cause the reverse voltage to be built up not only in the vertical direction, as in a conventional MOSFET, but in the horizontal direction as well.
  • this device can achieve the same reverse voltage as in the conventional device with a reduced layer thickness of epitaxial layer 1 and with increased doping concentration in the drift zone.
  • Curve 25 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage of the MOSFET shown in FIG. 3 .
  • the on-resistance of this device is substantially reduced relative to the device shown in FIG. 1 , essentially increasing linearly with the breakdown voltage.
  • the improved operating characteristics of the device shown in FIG. 3 are based on charge compensation in the drift region of the transistor. That is, the doping in the drift region is substantially increased, e.g., by an order of magnitude or more, and the additional charge is counterbalanced by the addition of columns of opposite doping type.
  • the blocking voltage of the transistor thus remains unaltered.
  • the charge compensating columns do not contribute to the current conduction when the device is in its on-state.
  • These desirable properties of the transistor depend critically on the degree of charge compensation that is achieved between adjacent columns of opposite doping type.
  • non-uniformities in the dopant gradient of the columns can be difficult to avoid as a result of limitations in the control of process parameters during their fabrication. For example, diffusion across the interface between the columns and the substrate and the interface between the columns and the P-body region will give rise to changes in the dopant concentration of the portions of the columns near those interfaces.
  • the structure shown in FIG. 3 can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant.
  • epitaxial deposition steps are expensive to perform and thus this structure is expensive to manufacture.
  • Another technique for fabricating these devices is shown in co-pending U.S. application Ser. No. 09/970,972, in which a trench is successively etched to different depths.
  • a dopant material is implanted and diffused through the bottom of the trench after each etching step to form a series of doped regions (so-called “floating islands”) that collectively function like the P-type doped regions 40 and 42 seen in FIG. 3 .
  • the on-resistance of a device that uses the floating island technique is not as low as an identical device that uses continuous columns.
  • a method of manufacturing a semiconductor device starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and a lightly doped N region at the top main surface.
  • Each trench has two sidewall surfaces in parallel alignment with each other.
  • a blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed.
  • the bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.
  • the body and the source regions are then formed after the gate dielectric and the gate conductor are formed.
  • the body region consists of an implanted P body region on top of each of the diffused P type doped regions to form the body regions and implanted N + regions within the body regions to form source regions.
  • Above the gate dielectric region is a gate conductor that extends over the P-type body and the N + source regions of two adjoining trenches.
  • a source conductor is connected to the P-type body and the N + source region.
  • the un-doped sidewalls will typically be doped with N type dopant.
  • the trenches may have the shape of a dog bone, a rectangle, a rectangle with rounded ends or a cross with the P type dopant being implanted into the ends of the dog bone, a rectangle, or a rectangle with rounded ends, and in opposite sides of the cross.
  • Rectangular-shaped trenches may be arranged in an array of rows and columns with the ends of the trenches in the column being implanted with P type dopants and the ends of the trenches in the rows being implanted with N type dopants.
  • Cross-shaped trenches may be implanted with P-type dopant along one set of axes, and with N-type dopant along a second set of axes at 90° to the first set.
  • the angle of the implant can be selected so that the bottoms of the trenches are not implanted.
  • the technique may be used to manufacture the termination regions by varying the shape, the depth and width of the trenches, in conjunction with the implant angle.
  • FIG. 1 is a sectional view of a prior art conventional MOSFET
  • FIG. 2 is a chart showing breakdown voltage, the on-resistances and current
  • FIG. 3 is a sectional view of a prior art superjunction transistor
  • FIGS. 4-14 illustrate the process steps used to manufacture the disclosed semiconductor device
  • FIGS. 15, 23 , 24 and 25 illustrate the different shapes that can be used to manufacture the disclosed semiconductor device
  • FIGS. 16, 18 , and 19 illustrate the different arrangements of the trenches to achieve the disclosed device
  • FIG. 17 is a sectional view of the disclosed device illustrating the source region
  • FIGS. 20, 26 and 27 illustrate possible termination arrangements of the semiconductor device
  • FIG. 21 shows a top view of the termination region
  • FIG. 22 is a sectional view of FIG. 21 .
  • FIGS. 4-18 A technique for forming lightly doped columns that extend almost through a layer of deposited epitaxial semiconductor material is best understood by referring to FIGS. 4-18 while reading the description below.
  • This technique uses trenches etched into the silicon to form lightly doped columns.
  • One type of trenches has a dimension in a first direction that is greater than the dimension in a second direction that is perpendicular to the first direction and is generally rectangular shaped, while a second type is cross-shaped.
  • FIG. 16 shows the top view of a series of generally rectangular shaped trenches 35 following two separate implantation steps that have doped the two narrow walls 31 and 33 of the trenches 35 .
  • FIGS. 9 and 10 show the technique that is used to perform the two implantation steps.
  • the two separate implantation steps are performed at an angle with respect to the surface of the substrate that allows the dopant to be implanted into just the two narrow “end” sidewalls 31 and 33 .
  • the presence of a layer of material such as silicon dioxide or silicon nitride (or a sandwich of such materials) prevents the ions that are being implanted from reaching the semiconductor sidewalls 37 that are along the long axis of each trench.
  • any dopant that has been implanted in the bottom of the trench may be removed by etching the trench deeper, and then the dopant may be diffused until the desired dopant distribution is obtained.
  • the trench is then filled using an oxidation or deposition step.
  • the shape of the trench is not limited to just being rectangular. Many other possible trench shapes such as dog-bones 235 , or rectangles with rounded ends 135 ( FIG. 15 ), or crosses are also possible.
  • the profile of the implanted dopant is slightly different, allowing the optimization of the shape of the implanted region. Both of the trench geometries avoid placing dopant atoms near a corner, which might result in better control of the resulting dopant profile.
  • the pattern of trenches across the surface of the device may also be varied to obtain the best performance. Examples of trench placement are shown in FIG. 16 which shows a square array, FIG. 18 which shows a staggered array 110 and FIG. 19 which illustrates an array 133 of rows and columns.
  • the number and locations of the trenches is important because it affects overall device efficiency.
  • a lightly doped epitaxial layer 1 is deposited on a heavily doped substrate 2 .
  • a blocking layer 41 of silicon dioxide is either grown or deposited on the top surface of the epitaxial.
  • the blocking layer has a desired thickness of between 400 and 2,000 ⁇ .
  • the blocking layer 41 is masked by a mask 43 to facilitate its etching.
  • trenches 45 are etched into the epitaxial layer 1 as illustrated in FIG. 7 .
  • a blocking layer 47 is grown or deposited on all of the sidewalls and bottoms of each trench 45 as is shown in FIG. 8 .
  • the thickness of blocking layer 47 is between 200 and 2000 ⁇ .
  • a first implant of boron ions is performed in the narrow end 33 at an angle alpha that in conjunction with the thickness of the blocking layer 47 will limit the penetration of the dopant in to the epitaxial 1 .
  • the thickness of the blocking layer 41 is sufficient enough to prevent the penetration of the dopant into the tops of the columns 21 .
  • the result is implanted ions 51 in the column 21 at the small side 33 .
  • Generally to prevent the penetrations of the ions in the bottom of the trench alpha should be equal to the tangent G, the depth of the trench T, the width of the trench.
  • FIG. 10 a second implant using the same dopant species is performed at the other small side 31 of the trenches 45 at an angle beta that is traditional equal to alpha minus 90 degrees leaving implanted ions 52 in the small side 31 as is shown in FIGS. 10 and 11 .
  • the implants are performed parallel to the long axis, the F side, of the geometry that is used, so no dopant penetrates through the oxide on these sidewalls because of the large angle away from being perpendicular.
  • the trench is etched to remove the blocking layer 47 and any implanted ions at the bottom of the trenches to a depth H shown generally at 53 .
  • a diffusion step is performed to create P-type doped regions 55 and 57 .
  • the trenches 45 are filled with an insulator such as silicon dioxide in FIG. 14 .
  • the trenches can have many different shapes such as the square shape 100 of FIG. 15 a , the elongated shape 101 of FIG. 15 b , or the dog bone shape 103 of FIG. 15 c . No dopant is introduced on the walls at the long sides of the structure for any of the geometries.
  • FIG. 15 show the location of the implanted dopant 36 and 38 following the first and second implants as shown in FIGS. 9 and 10 .
  • the trenches are filled.
  • a dielectric will be used, though it is possible to fill it with polysilicon and re-crystallize the polysilicon, or to fill the trench with single crystal silicon using epitaxial deposition.
  • the active region that includes the body, gate dielectric and conductor, and the source regions should be placed anywhere there is no trench present to provide channel regions for carrier flow.
  • active regions can be anywhere in the rows and columns between the trenches. Depending on the dimensions of the trench, polygonal, cellular or stripe geometries are all feasible.
  • a striped geometry might run parallel to the long axis of the trenches (top row of FIG. 16 ).
  • a cellular geometry might enclose each trench as shown on the bottom row 16 b of FIG. 16 . If a cell is formed at each end of the trench (middle row of FIG. 16 ), the source injects carriers around 3 sides, but not at the fourth side.
  • the cross section for either cellular version is the same through the doped column and is shown in FIG. 17 .
  • FIG. 19 The Use of Trenches Having Different Orientations in Combination with Implants with Dopants Having Different Conductivity Types is illustrated in FIG. 19 .
  • the creation of the active region includes the steps of implanting the P type source body region 5 on top of the P columns 36 and 38 .
  • a source 7 of N type dopant is then implanted on top of the source body regions 5 .
  • a gate oxide 6 is deposited and the gate electrode 18 is formed in the gate oxide between the rows 108 and 148 over the sources 7 .
  • the source electrode is connected to the source and source body region of each device.
  • a variation of the technique that was previously discussed uses the implantation of dopants of both conductivity types in the active region of the device.
  • the second dopant type is implanted at an angle of 90° and 270° to the first dopant implant, as shown in FIG. 19 . It provides the needed amount of dopant compensation and/or charge balance to obtain a high breakdown voltage.
  • the structures 11 have N-type dopants implanted at regions 136 and 138 and P-type dopants implanted at regions 36 and 38 .
  • a second set of rectangular trenches 35 that are perpendicular to the first set of trenches 35 provide this capability are shown in FIG. 19 .
  • FIG. 23 While geometries that allow the doping of the walls of a single trench with dopants of both conductivity types is shown in FIG. 23 . Unwanted doping of the top region of any sidewall which could occur when two dopants are implanted at 90° to each other can be prevented by using a blocking layer having a greater thickness along the top part of the sidewall than previously shown.
  • a formation of a termination at the device perimeter that is compatible with the sequence used in the fabrication of the super-junction structure at the center of the device is often a challenge.
  • FIG. 20 shows a top view
  • FIGS. 21 and 22 show a side view of trenches 35 , 121 and 122 at the termination having different lengths, device 207 , dotted line trenched 201 and device 209 and/or having both different lengths and widths trenches 207 , 211 and 200 —and different width trenches 207 , 201 and 205 .
  • the trench length directly determines the depth along the sidewall that is implanted on the two walls at the ends of each trench while the trench width directly affects the total charge introduced in these two sidewalls.
  • both the depth of the junctions formed by the introduced dopant and the total dopant amount that is introduced can be optimized.
  • the positions as well as the depths of the diffused P-type junctions in the termination region can be optimized to produce the highest breakdown voltage.
  • trenches that are not generally rectangular in shape (such as crosses 214 , squares 215 or circles 216 of FIGS. 24 and 25 ) that may also have different dimensions to etch trenches that are generally rectangular in shape, but with their axes along a line that is different from that of the trenches etched in the active region of the device. Examples of these trenches are shown in FIG. 26 .
  • the termination structure uses a second implant step with a dopant having the same conductivity type as that of the region containing the trenches.
  • This additional implant provides dopant that can either partially compensate the dopant from the first implant, or provide charge to balance the dopant introduced by the first implant.
  • trenches that are not generally rectangular in shape such as squares or trenches
  • may also have different dimensions or to etch trenches that are generally rectangular in shape with their axes along a line that is different from that of the trenches etched in the active region of the device as is shown in FIGS. 19 and 27 .
  • Implanting the first dopant type along one set of axes and the second dopant type along another set of axes that is 90° to the first set of axes provides the needed amount of dopant compensation and/or charge balance to obtain a high breakdown voltage.

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Abstract

A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. Non-provisional patent application Ser. No. 10/857,323 filed on May 28, 2004 entitled “A Technique for Forming the Deep Doped Columns in Superjunction.”
    • BACKGROUND OF THE INVENTION
  • The present invention relates generally to semiconductor devices, and more, particularly, to power MOSFET devices.
  • Power MOSFET devices are employed in applications such as automobile electrical systems, power supplies, and power management applications. Such devices should sustain high voltage in the off-state while having a low voltage drop and high current flow in the on-state.
  • FIG. 1 illustrates a typical structure for an N-channel power MOSFET. An Nepitaxial silicon layer 1 formed over an N+ silicon substrate 2 contains P- body regions 5 a and 6 a, and N+ source regions 7 and 8 for two MOSFET cells in the device. P- body regions 5 and 6 may also include deep P- body regions 5 b and 6 b. A source-body electrode 12 extends across certain surface portions of epitaxial layer 1 to contact the source and body regions. The N-type drain for both cells is formed by the portion of N-epitaxial layer 1 extending to the upper semiconductor surface in FIG. 1. A drain electrode is provided at the bottom of N+ substrate 2. An insulated gate electrode 18 typically of polysilicon lies primarily over the body and portions of the drain of the device, separated from the body and drain by a thin layer of dielectric, often silicon dioxide. A channel is formed between the source and drain at the surface of the body region when the appropriate positive voltage is applied to the gate with respect to the source and body electrode.
  • The on-resistance of the conventional MOSFET shown in FIG. 1 is determined largely by the drift zone resistance in epitaxial layer 1. The drift zone resistance is in turn determined by the doping and the layer thickness of epitaxial layer 1. However, to increase the breakdown voltage of the device, the doping concentration of epitaxial layer 1 must be reduced while the layer thickness is increased. Curve 20 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage for a conventional MOSFET. Unfortunately, as curve 20 shows, the on-resistance of the device increases rapidly as its breakdown voltage increases. This rapid increase in resistance presents a problem when the MOSFET is to be operated at higher voltages, particularly at voltages greater than a few hundred volts.
  • FIG. 3 shows a MOSFET that is designed to operate at higher voltages with a reduced on-resistance. This MOSFET is disclosed in paper No. 26.2 in the Proceedings of the IEDM, 1998, p. 683. This MOSFET is similar to the conventional MOSFET shown in FIG. 2 except that it includes P-type doped regions 40 and 42 which extend from beneath the body regions 5 and 6 into the drift region of the device. The P-type doped regions 40 and 42 define columns in the drift region that are separated by N-type doped columns, which are defined by the portions of the epitaxial layer 1 adjacent the P-doped regions 40 and 42. The alternating columns of opposite doping type cause the reverse voltage to be built up not only in the vertical direction, as in a conventional MOSFET, but in the horizontal direction as well. As a result, this device can achieve the same reverse voltage as in the conventional device with a reduced layer thickness of epitaxial layer 1 and with increased doping concentration in the drift zone. Curve 25 in FIG. 2 shows the on-resistance per unit area as a function of the breakdown voltage of the MOSFET shown in FIG. 3. Clearly, at higher operating voltages, the on-resistance of this device is substantially reduced relative to the device shown in FIG. 1, essentially increasing linearly with the breakdown voltage.
  • The improved operating characteristics of the device shown in FIG. 3 are based on charge compensation in the drift region of the transistor. That is, the doping in the drift region is substantially increased, e.g., by an order of magnitude or more, and the additional charge is counterbalanced by the addition of columns of opposite doping type. The blocking voltage of the transistor thus remains unaltered. The charge compensating columns do not contribute to the current conduction when the device is in its on-state. These desirable properties of the transistor depend critically on the degree of charge compensation that is achieved between adjacent columns of opposite doping type. Unfortunately, non-uniformities in the dopant gradient of the columns can be difficult to avoid as a result of limitations in the control of process parameters during their fabrication. For example, diffusion across the interface between the columns and the substrate and the interface between the columns and the P-body region will give rise to changes in the dopant concentration of the portions of the columns near those interfaces.
  • The structure shown in FIG. 3 can be fabricated with a process sequence that includes multiple epitaxial deposition steps, each followed by the introduction of the appropriate dopant. Unfortunately, epitaxial deposition steps are expensive to perform and thus this structure is expensive to manufacture. Another technique for fabricating these devices is shown in co-pending U.S. application Ser. No. 09/970,972, in which a trench is successively etched to different depths. A dopant material is implanted and diffused through the bottom of the trench after each etching step to form a series of doped regions (so-called “floating islands”) that collectively function like the P-type doped regions 40 and 42 seen in FIG. 3. However, the on-resistance of a device that uses the floating island technique is not as low as an identical device that uses continuous columns.
  • Accordingly, it would be desirable to provide a method of fabricating the MOSFET structure shown in FIG. 3 that requires a minimum number of deposition steps so that it can be produced less expensively while also allowing sufficient control of process parameters so that lightly doped columns that extend almost through a layer of deposited can be formed.
    • SUMMARY OF THE INVENTION
  • A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.
  • The body and the source regions are then formed after the gate dielectric and the gate conductor are formed. The body region consists of an implanted P body region on top of each of the diffused P type doped regions to form the body regions and implanted N+ regions within the body regions to form source regions. Above the gate dielectric region is a gate conductor that extends over the P-type body and the N+ source regions of two adjoining trenches. A source conductor is connected to the P-type body and the N+ source region.
  • The un-doped sidewalls will typically be doped with N type dopant. The trenches may have the shape of a dog bone, a rectangle, a rectangle with rounded ends or a cross with the P type dopant being implanted into the ends of the dog bone, a rectangle, or a rectangle with rounded ends, and in opposite sides of the cross.
  • Rectangular-shaped trenches may be arranged in an array of rows and columns with the ends of the trenches in the column being implanted with P type dopants and the ends of the trenches in the rows being implanted with N type dopants. Cross-shaped trenches may be implanted with P-type dopant along one set of axes, and with N-type dopant along a second set of axes at 90° to the first set.
  • The angle of the implant can be selected so that the bottoms of the trenches are not implanted.
  • The technique may be used to manufacture the termination regions by varying the shape, the depth and width of the trenches, in conjunction with the implant angle.
  • The identification of the type of doping use herein only refers to that shown in the particular embodiment. Those skilled in the art know that similar results may be achieved by using P type dopant instead of N type and visa versa. The use of the particular type of dopant in the description of the embodiments should in no way limit the scope of the claims.
    • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • FIG. 1 is a sectional view of a prior art conventional MOSFET;
  • FIG. 2 is a chart showing breakdown voltage, the on-resistances and current;
  • FIG. 3 is a sectional view of a prior art superjunction transistor;
  • FIGS. 4-14 illustrate the process steps used to manufacture the disclosed semiconductor device;
  • FIGS. 15, 23, 24 and 25 illustrate the different shapes that can be used to manufacture the disclosed semiconductor device;
  • FIGS. 16, 18, and 19 illustrate the different arrangements of the trenches to achieve the disclosed device;
  • FIG. 17 is a sectional view of the disclosed device illustrating the source region;
  • FIGS. 20, 26 and 27 illustrate possible termination arrangements of the semiconductor device;
  • FIG. 21 shows a top view of the termination region; and
  • FIG. 22 is a sectional view of FIG. 21.
    • DETAILED DESCRIPTION OF THE INVENTION
  • A technique for forming lightly doped columns that extend almost through a layer of deposited epitaxial semiconductor material is best understood by referring to FIGS. 4-18 while reading the description below. This technique uses trenches etched into the silicon to form lightly doped columns. One type of trenches has a dimension in a first direction that is greater than the dimension in a second direction that is perpendicular to the first direction and is generally rectangular shaped, while a second type is cross-shaped. FIG. 16 shows the top view of a series of generally rectangular shaped trenches 35 following two separate implantation steps that have doped the two narrow walls 31 and 33 of the trenches 35. FIGS. 9 and 10 show the technique that is used to perform the two implantation steps. The two separate implantation steps are performed at an angle with respect to the surface of the substrate that allows the dopant to be implanted into just the two narrow “end” sidewalls 31 and 33. The presence of a layer of material such as silicon dioxide or silicon nitride (or a sandwich of such materials) prevents the ions that are being implanted from reaching the semiconductor sidewalls 37 that are along the long axis of each trench. Following the implantation step, any dopant that has been implanted in the bottom of the trench may be removed by etching the trench deeper, and then the dopant may be diffused until the desired dopant distribution is obtained. The trench is then filled using an oxidation or deposition step.
  • The shape of the trench is not limited to just being rectangular. Many other possible trench shapes such as dog-bones 235, or rectangles with rounded ends 135 (FIG. 15), or crosses are also possible. The profile of the implanted dopant is slightly different, allowing the optimization of the shape of the implanted region. Both of the trench geometries avoid placing dopant atoms near a corner, which might result in better control of the resulting dopant profile.
  • The pattern of trenches across the surface of the device may also be varied to obtain the best performance. Examples of trench placement are shown in FIG. 16 which shows a square array, FIG. 18 which shows a staggered array 110 and FIG. 19 which illustrates an array 133 of rows and columns. The number and locations of the trenches is important because it affects overall device efficiency.
  • One fabrication sequence for the doped columns will now be discussed.
  • Referring to FIG. 4 a lightly doped epitaxial layer 1 is deposited on a heavily doped substrate 2. Then as shown in FIG. 5 a blocking layer 41 of silicon dioxide is either grown or deposited on the top surface of the epitaxial. The blocking layer has a desired thickness of between 400 and 2,000 Å. In FIG. 6 the blocking layer 41 is masked by a mask 43 to facilitate its etching. Following the etching of the blocking layer 41, trenches 45 are etched into the epitaxial layer 1 as illustrated in FIG. 7. A blocking layer 47 is grown or deposited on all of the sidewalls and bottoms of each trench 45 as is shown in FIG. 8. The thickness of blocking layer 47 is between 200 and 2000 Å.
  • Referring to FIG. 9, a first implant of boron ions is performed in the narrow end 33 at an angle alpha that in conjunction with the thickness of the blocking layer 47 will limit the penetration of the dopant in to the epitaxial 1. The thickness of the blocking layer 41 is sufficient enough to prevent the penetration of the dopant into the tops of the columns 21. The result is implanted ions 51 in the column 21 at the small side 33. Generally to prevent the penetrations of the ions in the bottom of the trench alpha should be equal to the tangent G, the depth of the trench T, the width of the trench.
  • In FIG. 10 a second implant using the same dopant species is performed at the other small side 31 of the trenches 45 at an angle beta that is traditional equal to alpha minus 90 degrees leaving implanted ions 52 in the small side 31 as is shown in FIGS. 10 and 11.
  • The implants are performed parallel to the long axis, the F side, of the geometry that is used, so no dopant penetrates through the oxide on these sidewalls because of the large angle away from being perpendicular.
  • In FIG. 12 the trench is etched to remove the blocking layer 47 and any implanted ions at the bottom of the trenches to a depth H shown generally at 53.
  • In FIG. 13 a diffusion step is performed to create P-type doped regions 55 and 57. The trenches 45 are filled with an insulator such as silicon dioxide in FIG. 14. The trenches can have many different shapes such as the square shape 100 of FIG. 15 a, the elongated shape 101 of FIG. 15 b, or the dog bone shape 103 of FIG. 15 c. No dopant is introduced on the walls at the long sides of the structure for any of the geometries.
  • The FIG. 15 show the location of the implanted dopant 36 and 38 following the first and second implants as shown in FIGS. 9 and 10.
  • After dopant implantation and diffusion to form the doped columns, the trenches are filled. Typically a dielectric will be used, though it is possible to fill it with polysilicon and re-crystallize the polysilicon, or to fill the trench with single crystal silicon using epitaxial deposition. Once the surface is planarized, the active region that includes the body, gate dielectric and conductor, and the source regions should be placed anywhere there is no trench present to provide channel regions for carrier flow. For the array 104 of FIG. 16, active regions can be anywhere in the rows and columns between the trenches. Depending on the dimensions of the trench, polygonal, cellular or stripe geometries are all feasible. A striped geometry might run parallel to the long axis of the trenches (top row of FIG. 16). A cellular geometry might enclose each trench as shown on the bottom row 16 b of FIG. 16. If a cell is formed at each end of the trench (middle row of FIG. 16), the source injects carriers around 3 sides, but not at the fourth side. The cross section for either cellular version is the same through the doped column and is shown in FIG. 17.
  • The Use of Trenches Having Different Orientations in Combination with Implants with Dopants Having Different Conductivity Types is illustrated in FIG. 19.
  • The creation of the active region includes the steps of implanting the P type source body region 5 on top of the P columns 36 and 38. A source 7 of N type dopant is then implanted on top of the source body regions 5. A gate oxide 6 is deposited and the gate electrode 18 is formed in the gate oxide between the rows 108 and 148 over the sources 7. Finally, the source electrode is connected to the source and source body region of each device.
  • A variation of the technique that was previously discussed uses the implantation of dopants of both conductivity types in the active region of the device. In this variation, the second dopant type is implanted at an angle of 90° and 270° to the first dopant implant, as shown in FIG. 19. It provides the needed amount of dopant compensation and/or charge balance to obtain a high breakdown voltage. Where the structures 11 have N-type dopants implanted at regions 136 and 138 and P-type dopants implanted at regions 36 and 38. A second set of rectangular trenches 35 that are perpendicular to the first set of trenches 35 provide this capability are shown in FIG. 19. While geometries that allow the doping of the walls of a single trench with dopants of both conductivity types is shown in FIG. 23. Unwanted doping of the top region of any sidewall which could occur when two dopants are implanted at 90° to each other can be prevented by using a blocking layer having a greater thickness along the top part of the sidewall than previously shown.
    • A Compatible Termination Structure
  • A formation of a termination at the device perimeter that is compatible with the sequence used in the fabrication of the super-junction structure at the center of the device is often a challenge.
  • In the present embodiment, however, it is possible to form a compatible termination structure by either using the same process sequence, or by adding one more implants to the existing process sequence. These two possibilities are discussed in greater detail below.
    • A Compatible Termination Structure that Requires No Additional Process Steps
  • This termination structure is best understood by referring to FIGS. 21 and 22. FIG. 20 shows a top view and FIGS. 21 and 22 show a side view of trenches 35, 121 and 122 at the termination having different lengths, device 207, dotted line trenched 201 and device 209 and/or having both different lengths and widths trenches 207, 211 and 200—and different width trenches 207, 201 and 205. The trench length directly determines the depth along the sidewall that is implanted on the two walls at the ends of each trench while the trench width directly affects the total charge introduced in these two sidewalls. By varying the trench length and width, both the depth of the junctions formed by the introduced dopant and the total dopant amount that is introduced can be optimized. By also controlling the number and the locations of the trenches that are etched in the termination region, as shown in FIG. 20, the positions as well as the depths of the diffused P-type junctions in the termination region can be optimized to produce the highest breakdown voltage.
  • It is also possible to etch trenches that are not generally rectangular in shape (such as crosses 214, squares 215 or circles 216 of FIGS. 24 and 25) that may also have different dimensions to etch trenches that are generally rectangular in shape, but with their axes along a line that is different from that of the trenches etched in the active region of the device. Examples of these trenches are shown in FIG. 26.
  • A Compatible Termination Structure that Requires an Additional Implant Step
  • The termination structure uses a second implant step with a dopant having the same conductivity type as that of the region containing the trenches. This additional implant provides dopant that can either partially compensate the dopant from the first implant, or provide charge to balance the dopant introduced by the first implant. By etching a second set of trenches 123 that are generally rectangular shaped, and that have their major axis at an angle offset to the axis of the first set of trenches and by varying the dimensions of the trenches as discussed above, it is possible to control both the location and the amount of dopant introduced. Examples of possible termination trenches of this type are shown in FIG. 26. It is also possible to etch trenches that are not generally rectangular in shape (such as squares or trenches) that may also have different dimensions or to etch trenches that are generally rectangular in shape with their axes along a line that is different from that of the trenches etched in the active region of the device as is shown in FIGS. 19 and 27. Implanting the first dopant type along one set of axes and the second dopant type along another set of axes that is 90° to the first set of axes provides the needed amount of dopant compensation and/or charge balance to obtain a high breakdown voltage.

Claims (32)

1. A method of manufacturing a semiconductor device comprising:
providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface side;
providing in the semiconductor substrate a plurality of trenches, with each trench having a first extending portion extending from the first main surface towards the heavily doped region to a first depth position, each trench having a first sidewall surface and a second sidewall surface;
forming a blocking layer on the first and second sidewalls and the bottom of each trench;
implanting a dopant of a second conductivity type into the first sidewall surface to form a first doped region of the second conductivity type at the first sidewall surface;
implanting a dopant of the second conductivity type into the second sidewall surface, to provide a second doped region of the second conductivity type at the second surface;
removing the blocking layer from the first and second sidewalls and bottoms of each trench;
etching the bottoms of the trench to remove any implanted dopants of the second conductivity type;
diffusing the implanted dopant of the second conductivity type; and
filling the trenches.
2. The method according to claim 1, wherein the plurality of trenches are arranged in an array and the method further comprises:
providing a third doped region of the second conductivity type at the first main surface side of the first doped region to be electrically connected to the first region of a first trench;
providing a fourth doped region of the second conductivity type at the first main surface side of the second doped region to be electrically connected to the second region of a second trench; and
providing a gate electrode layer between the third and fourth doped regions, with a gate insulation layer interposed therebetween.
3. The method according to claim 2, wherein the gate electrode insulator layer is formed on the first main surface.
4. The method according to claim 1 wherein each of the plurality of trenches has a rectangular shape and the first and second sidewalls are each located on a narrow side of the rectangular shape.
5. The method according to claim 4 further comprising following the step of implanting a dopant of the second conductivity type into the second sidewall surface, to provide a second doped region of the second conductivity type at the second surface, performing the steps of:
implanting a dopant of the first conductivity type into a third sidewall surface to form a third doped region of the first conductivity type; and
implanting a dopant of the first conductivity type into a fourth sidewall surface opposite the third sidewall surface, to provide a fourth doped region of the first conductivity type at the second surface.
6. The method according to claim 1 wherein each of the plurality of trenches has a cross shape and the first and second sidewalls are each located on an ordinate leg of the cross.
7. The method according to claim 6 further comprising, following the step of implanting a dopant of the second conductivity type into the second sidewall surface, to provide a second doped region of the second conductivity type at the second surface, performing the steps of:
implanting a dopant of the first conductivity type into a third sidewall surface to form a third doped region of the first conductivity type;
implanting a dopant of the first conductivity type into a fourth sidewall surface opposite the third sidewall surface, to provide a fourth doped region of the first conductivity type at the fourth surface and wherein the third and fourth sidewall surfaces are located on an abscissa leg of the cross.
8. The method according to claim 1 wherein each of the plurality of trenches has a rectangular shape and the first and second sidewalls are each located on a narrow side of the rectangular shape with the plurality of trenches being arranged in a plurality of columns.
9. The method according to claim 8 wherein at least two of the columns are separated from each other by a second plurality of trenches arranged in rows, and the method further comprises, following the step of, implanting a dopant of the second conductivity type into the second sidewall surface, to provide a second doped region of the second conductivity type at the second surface, performing the steps of
implanting a dopant of the first conductivity type into the first sidewall surface to form a first doped region of the first conductivity type in each member of the second plurality of trenches; and
implanting a dopant of the first conductivity type into a second sidewall surface opposite the first sidewall surface, to provide a second doped region of the first conductivity type at the second surface in each member of the second plurality of trenches.
10. The method according to claim 1 wherein the step of implanting a dopant of a second conductivity type into the first sidewall surface to form a first doped region of the second conductivity type at the first sidewall surface further comprises implanting the dopant at a first angle.
11. The method according to claim 10 wherein the first angle is less than the tangent of the depth of the trench to the width of a side of the trench that is at a right angle to the first sidewall surface.
12. The method according to claim 11 wherein the step of implanting a dopant of the second conductivity type into the second sidewall surface to form a second doped region of the second conductivity type at the second sidewall surface further comprises implanting the dopant at a second angle that is ninety degrees larger than the first angle.
13. A semiconductor device formed by the method of claim 1.
14. A method of manufacturing a semiconductor device comprising:
providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface side;
providing in the semiconductor substrate a plurality of trenches, with each trench having a first extending portion extending from the first main surface towards the heavily doped region to a first depth position, each trench having a first sidewall surface and a second sidewall surface;
forming an blocking layer on the first and second sidewalls and the bottom of each trench;
implanting a dopant of a second conductivity type into the first sidewall surface at a first angle that is less than the tangent of the depth of the trench to the width of a side of the trench that is at a right angle to the first sidewall surface to form a first doped region of the second conductivity type at the first sidewall surface;
implanting a dopant of the second conductivity type into the second sidewall surface at a second angle that is ninety degrees larger than the first angle, to provide a second doped region of the second conductivity type at the second surface;
removing the blocking layer from the first and second sidewalls and bottoms of each trench;
diffusing the implanted dopant of the second conductivity type; and
filling the trenches.
15. The method according to claim 14, wherein the plurality of trenches are arranged in an array and the method further comprises:
providing a third doped region of the second conductivity type at the first main surface side of the first doped region to be electrically connected to the first region of a first trench;
providing a fourth doped region of the second conductivity type at the first main surface side of the second doped region to be electrically connected to the second region of a second trench; and
providing a gate electrode layer between the third and fourth doped regions, with a gate insulation layer interposed therebetween.
16. The method according to claim 15, wherein the gate electrode insulator layer is formed on the first main surface.
17. The method according to claim 14 wherein each of the plurality of trenches has a rectangular shape and the first and second sidewalls are each located on a narrow side of the rectangular shape.
18. The method according to claim 17 further comprising following the step of implanting a dopant of the second conductivity type into the second sidewall surface, to provide a second doped region of the second conductivity type at the second surface, performing the steps of
implanting a dopant of the first conductivity type into a third sidewall surface to form a third doped region of the first conductivity type; and
implanting a dopant of the first conductivity type into a fourth sidewall surface opposite the third sidewall surface, to provide a fourth doped region of the first conductivity type at the second surface.
19. The method according to claim 14 wherein each of the plurality of trenches has a cross shape and the first and second sidewalls are each located on an ordinate leg of the cross.
20. The method according to claim 19 further comprising, following the step of implanting a dopant of the second conductivity type into the second sidewall surface, to provide a second doped region of the second conductivity type at the second surface, performing the steps of:
implanting a dopant of the first conductivity type into a third sidewall surface to form a third doped region of the first conductivity type; and
implanting a dopant of the first conductivity type into a fourth sidewall surface opposite the third sidewall surface, to provide a fourth doped region of the first conductivity type at the fourth surface and wherein the third and fourth sidewall surfaces are located on an abscissa leg of the cross.
21. The method according to claim 14 wherein each of the plurality of trenches has a rectangular shape and the first and second sidewalls are each located on a narrow side of the rectangular shape with the plurality of trenches being arranged in a plurality of columns.
22. The method according to claim 21 wherein at least two of the columns are separated from each other by a second plurality of trenches arranged in rows, and the method further comprises, following the step of, implanting a dopant of the second conductivity type into the second sidewall surface, to provide a second doped region of the second conductivity type at the second surface, performing the steps of:
implanting a dopant of the first conductivity type into the first sidewall surface to form a first doped region of the first conductivity type in each member of the second plurality of trenches; and
implanting a dopant of the first conductivity type into a second sidewall surface opposite the first sidewall surface, to provide a second doped region of the first conductivity type at the second surface in each member of the second plurality of trenches.
23. A semiconductor device formed by the method of claim 14.
24. A method of manufacturing a semiconductor device comprising:
providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface side;
providing in the semiconductor substrate a plurality of trenches, with each trench having a first extending portion extending from the first main surface towards the heavily doped region to a first depth position, each trench having a first sidewall surface and a second sidewall surface;
forming a blocking layer on the first and second sidewalls and the bottom of each trench;
doping the first sidewall surface with a dopant of a second conductivity type to form a first doped region of the second conductivity type at the first sidewall surface;
doping the second sidewall surface with a dopant of the second conductivity type to form a second doped region of the second conductivity type at the second surface; and
removing the blocking layer from the first and second sidewalls and bottoms of each trench.
25. The method according to claim 24, wherein the plurality of trenches are arranged in an array and the method further comprises:
etching the bottoms of the trench to remove any implanted dopants of the second conductivity type;
diffusing the implanted dopant of the second conductivity type;
filling the trenches;
providing a third doped region of the second conductivity type at the first main surface side of the first doped region to be electrically connected to the first region of a first trench;
providing a fourth doped region of the second conductivity type at the first main surface side of the second doped region to be electrically connected to the second region of a second trench; and
providing a gate electrode layer between the third and fourth doped regions, with a gate insulation layer interposed therebetween.
26. The method according to claim 25, wherein the gate electrode insulator layer is formed on the first main surface.
27. The method according to claim 24 wherein each of the plurality of trenches has a rectangular shape and the first and second sidewalls are each located on a narrow side of the rectangular shape.
28. The method according to claim 27 further comprising following the step of doping the second sidewall surface, performing the steps of:
doping a third sidewall surface with a dopant of the first conductivity type to form a third doped region of the first conductivity type; and
doping a fourth sidewall surface opposite the third sidewall surface with a dopant of the first conductivity type to form a fourth doped region of the first conductivity type.
29. The method according to claim 24 wherein each of the plurality of trenches has a cross shape and the first and second sidewalls are each located on an ordinate leg of the cross.
30. A semiconductor device formed by the method of claim 1.
31. A method of manufacturing a semiconductor device comprising:
providing a semiconductor substrate having first and second main surfaces opposite to each other, the semiconductor substrate having a heavily doped region of a first conductivity type at the second main surface and having a lightly doped region of the first conductivity type at the first main surface side;
providing in the semiconductor substrate a plurality of trenches, with each trench having a first extending portion extending from the first main surface towards the heavily doped region to a first depth position, each trench having a first sidewall surface and a second sidewall surface;
forming a blocking layer of silicon dioxide on the first and second sidewalls and the bottom of each trench, the blocking layer having a thickness of about 400-2000 Angstroms (Å);
implanting a dopant of a second conductivity type into the first sidewall surface at an angle α to form a first doped region of the second conductivity type at the first sidewall surface;
implanting a dopant of the second conductivity type into the second sidewall surface at an angle α minus 90 degrees to provide a second doped region of the second conductivity type at the second surface;
removing the blocking layer from the first and second sidewalls and bottoms of each trench by etching;
etching the bottoms of the trench to remove any implanted dopants of the second conductivity type;
diffusing the implanted dopant of the second conductivity type; and
filling the trenches with doped or undoped polysilicon.
32. A semiconductor device formed by the method of claim 31.
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Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090026586A1 (en) * 2005-04-22 2009-01-29 Icemos Technology Corporation Superjunction Device Having Oxide Lined Trenches and Method for Manufacturing a Superjunction Device Having Oxide Lined Trenches
US7446018B2 (en) 2005-08-22 2008-11-04 Icemos Technology Corporation Bonded-wafer superjunction semiconductor device
US7723201B2 (en) * 2006-01-09 2010-05-25 International Business Machines Corporation Structure and method for making on-chip capacitors with various capacitances
US7429772B2 (en) * 2006-04-27 2008-09-30 Icemos Technology Corporation Technique for stable processing of thin/fragile substrates
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US7948033B2 (en) 2007-02-06 2011-05-24 Semiconductor Components Industries, Llc Semiconductor device having trench edge termination structure
US8580651B2 (en) * 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US7723172B2 (en) 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
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US8012806B2 (en) 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices
US8159039B2 (en) * 2008-01-11 2012-04-17 Icemos Technology Ltd. Superjunction device having a dielectric termination and methods for manufacturing the device
US7846821B2 (en) 2008-02-13 2010-12-07 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US7795045B2 (en) * 2008-02-13 2010-09-14 Icemos Technology Ltd. Trench depth monitor for semiconductor manufacturing
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US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
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Citations (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158206A (en) * 1977-02-07 1979-06-12 Rca Corporation Semiconductor device
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US5019522A (en) * 1986-03-21 1991-05-28 Advanced Power Technology, Inc. Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
US5045903A (en) * 1988-05-17 1991-09-03 Advanced Power Technology, Inc. Topographic pattern delineated power MOSFET with profile tailored recessed source
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5366914A (en) * 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
US5472888A (en) * 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
US5598018A (en) * 1978-10-13 1997-01-28 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US5744994A (en) * 1996-05-15 1998-04-28 Siliconix Incorporated Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
US5939754A (en) * 1996-09-09 1999-08-17 Nissan Motor Co., Ltd. Power MOSFET having a drain heterojunction
US6081009A (en) * 1997-11-10 2000-06-27 Intersil Corporation High voltage mosfet structure
US6184555B1 (en) * 1996-02-05 2001-02-06 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
US6190970B1 (en) * 1999-01-04 2001-02-20 Industrial Technology Research Institute Method of making power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6222229B1 (en) * 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6239463B1 (en) * 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US6291856B1 (en) * 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6307246B1 (en) * 1998-07-23 2001-10-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor resurf devices formed by oblique trench implantation
US6362505B1 (en) * 1998-11-27 2002-03-26 Siemens Aktiengesellschaft MOS field-effect transistor with auxiliary electrode
US6376314B1 (en) * 1997-11-07 2002-04-23 Zetex Plc. Method of semiconductor device fabrication
US6391723B1 (en) * 1999-05-31 2002-05-21 Stmicroelectronics S.R.L. Fabrication of VDMOS structure with reduced parasitic effects
US20020070418A1 (en) * 2000-12-07 2002-06-13 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6410958B1 (en) * 2000-11-27 2002-06-25 Kabushiki Kaisha Toshiba Power MOSFET having laterally three-layered structure formed among element isolation regions
US6452230B1 (en) * 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
US6459124B1 (en) * 1996-10-02 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and process for manufacturing the same, and electronic device
US6495421B2 (en) * 1999-12-15 2002-12-17 Koninklijke Philips Electronics N.V. Manufacture of semiconductor material and devices using that material
US6501130B2 (en) * 2001-01-24 2002-12-31 Power Integrations, Inc. High-voltage transistor with buried conduction layer
US6504230B2 (en) * 1999-09-07 2003-01-07 Infineon Technologies Ag Compensation component and method for fabricating the compensation component
US6509220B2 (en) * 2000-11-27 2003-01-21 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US6566201B1 (en) * 2001-12-31 2003-05-20 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6624494B2 (en) * 2001-10-04 2003-09-23 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US6710418B1 (en) * 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4983535A (en) * 1981-10-15 1991-01-08 Siliconix Incorporated Vertical DMOS transistor fabrication process
US4717681A (en) * 1986-05-19 1988-01-05 Texas Instruments Incorporated Method of making a heterojunction bipolar transistor with SIPOS
US5002631A (en) * 1990-03-09 1991-03-26 At&T Bell Laboratories Plasma etching apparatus and method
JP3291957B2 (en) * 1995-02-17 2002-06-17 富士電機株式会社 Vertical trench MISFET and method of manufacturing the same
US6034389A (en) * 1997-01-22 2000-03-07 International Business Machines Corporation Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
DE19801095B4 (en) 1998-01-14 2007-12-13 Infineon Technologies Ag Power MOSFET
EP1393362B1 (en) * 2001-04-28 2011-12-14 Nxp B.V. Method of manufacturing a trench-gate semiconductor device
JP4171268B2 (en) * 2001-09-25 2008-10-22 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP3927111B2 (en) * 2002-10-31 2007-06-06 株式会社東芝 Power semiconductor device

Patent Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158206A (en) * 1977-02-07 1979-06-12 Rca Corporation Semiconductor device
US5598018A (en) * 1978-10-13 1997-01-28 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US5742087A (en) * 1978-10-13 1998-04-21 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US5019522A (en) * 1986-03-21 1991-05-28 Advanced Power Technology, Inc. Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
US5786619A (en) * 1988-02-25 1998-07-28 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5472888A (en) * 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5045903A (en) * 1988-05-17 1991-09-03 Advanced Power Technology, Inc. Topographic pattern delineated power MOSFET with profile tailored recessed source
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5366914A (en) * 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
US6184555B1 (en) * 1996-02-05 2001-02-06 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
US5744994A (en) * 1996-05-15 1998-04-28 Siliconix Incorporated Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
US5929690A (en) * 1996-05-15 1999-07-27 Siliconix Incorporated Three-terminal power MOSFET switch for use as synchronous rectifier or voltage clamp
US5939754A (en) * 1996-09-09 1999-08-17 Nissan Motor Co., Ltd. Power MOSFET having a drain heterojunction
US6459124B1 (en) * 1996-10-02 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and process for manufacturing the same, and electronic device
US6239463B1 (en) * 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US6376314B1 (en) * 1997-11-07 2002-04-23 Zetex Plc. Method of semiconductor device fabrication
US6081009A (en) * 1997-11-10 2000-06-27 Intersil Corporation High voltage mosfet structure
US6307246B1 (en) * 1998-07-23 2001-10-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor resurf devices formed by oblique trench implantation
US6291856B1 (en) * 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6362505B1 (en) * 1998-11-27 2002-03-26 Siemens Aktiengesellschaft MOS field-effect transistor with auxiliary electrode
US6452230B1 (en) * 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
US6359309B1 (en) * 1999-01-04 2002-03-19 Industrial Technology Research Institute Power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6190970B1 (en) * 1999-01-04 2001-02-20 Industrial Technology Research Institute Method of making power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6222229B1 (en) * 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6391723B1 (en) * 1999-05-31 2002-05-21 Stmicroelectronics S.R.L. Fabrication of VDMOS structure with reduced parasitic effects
US6504230B2 (en) * 1999-09-07 2003-01-07 Infineon Technologies Ag Compensation component and method for fabricating the compensation component
US6495421B2 (en) * 1999-12-15 2002-12-17 Koninklijke Philips Electronics N.V. Manufacture of semiconductor material and devices using that material
US6509220B2 (en) * 2000-11-27 2003-01-21 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US6410958B1 (en) * 2000-11-27 2002-06-25 Kabushiki Kaisha Toshiba Power MOSFET having laterally three-layered structure formed among element isolation regions
US20020070418A1 (en) * 2000-12-07 2002-06-13 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6501130B2 (en) * 2001-01-24 2002-12-31 Power Integrations, Inc. High-voltage transistor with buried conduction layer
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6624494B2 (en) * 2001-10-04 2003-09-23 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6566201B1 (en) * 2001-12-31 2003-05-20 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6710400B2 (en) * 2001-12-31 2004-03-23 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6710418B1 (en) * 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120306003A1 (en) * 2011-05-31 2012-12-06 Infineon Technologies Ag Transistor with controllable compensation regions
US20120305993A1 (en) * 2011-05-31 2012-12-06 Infineon Technologies Austria Ag Transistor with controllable compensation regions
US8698229B2 (en) * 2011-05-31 2014-04-15 Infineon Technologies Austria Ag Transistor with controllable compensation regions
US8803205B2 (en) * 2011-05-31 2014-08-12 Infineon Technologies Austria Ag Transistor with controllable compensation regions
DE102015116579A1 (en) 2015-09-30 2017-03-30 Infineon Technologies Austria Ag Superjunction semiconductor device and manufacturing method

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