JP6046072B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device or a manufacturing method thereof, and more particularly to a superjunction semiconductor device or a manufacturing method thereof.

  In recent years, environmentally friendly products and environmental protection technologies have been recommended, and there are many demands for energy-saving electronic devices. In order to respond to the increasing need for such devices, the semiconductor industry is moving toward a perspective that further considers energy use. Accordingly, superjunction metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed that provide improved energy efficiency. Compared to conventional planar MOSFET structures, superjunction MOSFETs can reduce the on-resistance very low without affecting the voltage tolerance of the device. As a result, a MOSFET having a low on-resistance per unit area is generated.

  A typical superjunction MOSFET device includes two regions, an active region (also referred to as a cell region) and a termination region. The termination region of the superjunction MOSFET device is designed to maintain the lateral potential difference in the device. When the potential difference maintained by the termination region is small, the electric field generated in the vertical and horizontal directions in the device is large. Therefore, the function of the terminal area of the device is likely to deteriorate.

  Thus, there is a need for an improved superjunction device.

  An object of the present invention is to provide a superjunction semiconductor device or a method for manufacturing the same.

  The present invention provides a semiconductor device, and is formed in a first conductivity type substrate having an active region and a termination region, a first conductivity type epitaxial layer formed on the substrate, and an active region epitaxial layer. A plurality of first trenches, a plurality of second trenches formed in the epitaxial layer of the termination region, and an injection blocking layer formed at the bottom of the first and second trenches, conformally, the first and second trenches A second conductivity type liner formed along the sidewalls of the first and second conductivity types, and a dielectric material filling the first and second trenches defining the plurality of first columns and the plurality of second columns, respectively. A gate dielectric layer formed on the epitaxial layer; two floating gates formed on the gate dielectric layer opposite the first column farthest from the termination region; and the two floating gates To include a source region formed, an interlayer insulating film layer covering the gate dielectric layer and a floating gate, and a contact plug formed on the source region through the interlayer insulating film layer.

  The present invention also provides a method of manufacturing a semiconductor device, provides a substrate of a first conductivity type, a step in which the substrate has an active region and a termination region, and forms an epitaxial layer of the first conductivity type on the substrate. A step of forming a plurality of first trenches in the epitaxial layer of the active region, a step of forming a plurality of second trenches in the epitaxial layer of the termination region, and a step of Forming an injection blocking layer at the bottom, forming a liner conformally on the sidewalls of the first trench and the second trench, and applying a dopant of a second conductivity type different from the first conductivity type to the liner; Implanting, filling the first and second trenches with a dielectric material to form a plurality of first columns and a plurality of second columns, respectively, and epitaxy the gate dielectric layer Forming on the gate layer, forming two floating gates on the gate dielectric layer on the opposite side of the first column farthest from the termination region, and a source region between the two floating gates Forming an interlayer insulating film layer covering the gate dielectric layer and the floating gate, and forming a contact plug on the source through the interlayer insulating film. The implantation blocking layer prevents dopants from entering the bottom of the first and second trenches.

  The present invention prevents the loss of potential difference caused by diffusion at the bottom of the trench, thereby creating an electric field at the bottom of the trench in the termination region of the superjunction device that normally occurs in conventional superjunction devices. Reduce. Also, since there is no high electric field at the bottom of the trench in the termination region, the problem of breakage in the termination region of the superjunction device is effectively eliminated.

The invention will be more fully understood by considering the following detailed description of various embodiments of the invention in conjunction with the accompanying drawings.
It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment. It is sectional drawing explaining the flow of the formation method of the super junction semiconductor device which concerns on this embodiment.

  1 to 13 are cross-sectional views illustrating a flowchart of a method for forming a superjunction semiconductor device according to this embodiment.

  Referring to FIG. 1, a first conductivity type substrate 100 is provided. The substrate 100 includes an active region 100a and a termination region 100b adjacent to the active region 100a. The substrate 100 is a bulk silicon substrate, a silicon on insulator (SOI) substrate, or the like. In addition, other appropriate substrates such as a multilayer substrate, a gradient substrate, a hybrid alignment substrate, and the like are also used. The substrate 100 includes a p-type first conductivity type, for example, a boron-doped substrate. As another example, the substrate 100 includes an n-type first conductivity type, for example, a phosphor or an arsenic substrate. Other suitable substrates are also used. In this embodiment, the substrate 100 is a highly doped n-type (N +) substrate.

  Referring to FIG. 2, a first conductivity type epitaxial layer 102 is formed on a substrate 100. The substrate 100 has a higher doping concentration than the epitaxial layer 102. For example, when the first conductivity type is n-type, the substrate 100 is a heavily doped n-type (N +) substrate 100 and the epitaxial layer 102 is a lightly doped n-type (N−) epitaxial layer. It is. The epitaxial layer 102 is formed to a thickness of 1 to 100 μm by epitaxial growth based on the width of the device.

  After the formation of the epitaxial layer 102, a process for forming a plurality of trenches in the epitaxial layer 102 is performed. Referring to FIG. 3, a plurality of first trenches 104 are formed in the epitaxial layer 102 of the active region 100a, and a plurality of second trenches 106 are formed in the epitaxial layer 102 of the termination region 100b. The first trench 104 and the second trench 106 are formed by lithography and etching processes. As an example, the distance between the first trench 104 and the second trench 106 varies from the active region 100a to the termination region 100b. For example, the distance between the first trench 104 and the second trench 106 increases from the active region 100a to the termination region 100b. In particular, the distance a is smaller than the distance b, the distance b is smaller than the distance c, the distance c is smaller than the distance d, and the distance d is smaller than the distance e. In another example, the distance between the first trench 104 and the second trench 106 is the same.

  After formation of the first trench and the second trench, an implant blocker is formed in the first trench 104 and the second trench 106. 4A to 4D are diagrams showing steps for forming the injection blocking layer 108. FIG. Referring to FIG. 4A, a first oxide layer 108A, a nitride layer 108B, and a second dioxide layer 108C are successively and conformally formed on the epitaxial layer 102 (in other words, the first The monoxide layer 108A, the nitride layer 108B, and the second dioxide layer 108C are sequentially formed on the epitaxial layer 102 along the sidewalls and bottoms of the first trench 104 and the second trench 106, and the first oxide layer 108A, The nitride layer 108B and the second dioxide layer 108C are formed in a common shape.) The thickness ratio between the first oxide layer 108A, the nitride layer 108B, and the second dioxide layer 108C is about 1 to 10: 1 to 10: 1 to 50. The first oxide layer 108A and the second dioxide layer 108C include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, or a combination thereof, and the nitride layer 108B includes silicon nitride, oxynitride, or a combination thereof. including. In the present embodiment, the first oxide layer 108A is a silicon oxide layer, the nitride layer 108B is a silicon nitride layer, and the second dioxide layer is a TEOS oxide layer. Layers 108A, 108B, and 108C are formed by a vapor deposition process, such as chemical vapor deposition (CVD), or thermally grown by an oxidation or nitridation process. As shown in FIG. 4B, after the formation of layer 108A, layer 108B, and layer 108C, mask layer 210 is formed to completely expose first trench 104 and second trench 106 that expose the surface of second dioxide layer 108C. Fill. Referring to FIG. 4C, the first oxide layer 108A, the nitride layer 108B, and a portion of the second dioxide layer 108C that are not covered by the mask layer 210 are removed. The removal method is a wet etching process. After the step of FIG. 4C, the mask layer 210 is removed, and as shown in FIG. 4D, the first oxide layer 108A, the nitride layer 108B, and the remaining portion of the second dioxide layer 108C form an implantation blocking layer 108. . Implant blocking layer 108 does not contact the sidewalls of trenches 104 and 106 directly. The bottom (part of the bottom) and the side walls of the trench 104 and the trench 106 are exposed. The total thickness of the injection blocking layer 108 varies from 1000A to 5000A. In this embodiment, the total thickness of the injection blocking layer 108 is about 2000A.

  FIG. 4E is a cross-sectional view of the injection blocking layer 108 according to a modification of the present invention. In the variation of FIG. 4E, the first oxide layer 108A ′, the nitride layer 108B ′, and the second dioxide layer 108C ′ are directly formed in the first trench 104 by, for example, a high density plasma chemical vapor deposition (HDPCVD) process. And formed at the bottom of the second trench 106. In a variation, layer 108A ′, layer 108B ′, and layer 108C ′ are formed directly only in trenches 104 and 106, so the removal process shown in FIGS. 4A-4C is not required, and layers 108A ′, The injection blocking layer 108 ′ formed by the layer 108 B ′ and the layer 108 C ′ covers the side wall (a part of the side wall) at the bottom of the first trench 104 and the second trench 106. The thickness ratio between the first oxide layer 108A ', the nitride layer 108B', and the second dioxide layer 108C 'is about 1 to 10: 1 to 10: 1 to 50. The total thickness of the injection blocking layer 108 'varies from 1000A to 5000A. In a variation of the invention, the total thickness of the injection blocking layer 108 'is about 2000A.

  Although the injection blocking layer 108 shown in FIGS. 4D and 4E is an oxide-nitride-oxide composite layer, it should be noted that the injection blocking layer has a different structure, such as a nitride-oxide. A nitride composite layer, a nitride-oxide composite layer, or an oxide-oxynitride-oxide composite layer. The injection blocking layer 108 ′ shown in FIG. 4E is also used as an example described below.

  After the formation of the injection blocking layer 108 ', a liner 110 is formed conformally on the epitaxial layer 102 as shown in FIG. 5 (in other words, the liner 110 is formed of the first trench 104 and the second trench). 106 along the side wall and bottom of 106 and along the top surface of epitaxial layer 102. The liner 110 includes a dielectric material, such as silicon oxide, silicon nitride, oxynitride, or other suitable material. It should be noted that the steps shown in FIG. 5 are performed on the injection blocking layer 108 ′ shown in FIG. 4E, but the steps of FIG. 5 may also be performed on the injection blocking layer 108 shown in FIG. 4D. Good. In the example of forming the liner 110 on the implant blocking layer 108 shown in FIG. 4D, the liner 110 is also formed on the sidewalls and bottom of the trenches 104 and 106 that are not covered by the implant blocking layer 108. The liner 110 has a thickness of about 100 to 500A.

  Referring to FIG. 6, following the step of FIG. 5, an implantation process 300 is performed to implant a second conductivity type dopant into the liner 110 on the sidewalls of the trench 104 and the trench 106 at an angle. The first conductivity type and the second conductivity type are different. For example, when the first conductivity type is n-type, the second conductivity type is p-type. In performing the implantation process 300, the implantation blocking layer 108 ′ blocks dopants from entering the bottoms of the first trench 104 and the second trench 106.

  Referring to FIG. 7, after the dopant of the second conductivity type is implanted into the liner 110, the dielectric material is filled in the first trench 104 and the second trench 106, so that the plurality of first columns 112 and the plurality of second columns are filled. Two columns 114 are formed respectively. The dielectric material is silicon oxide, silicon nitride, oxynitride, low dielectric constant dielectric, other suitable dielectric materials, or combinations thereof. Methods for filling the dielectric material include vapor deposition processes and CMP processes. The deposition process includes CVD. The CMP process also removes part of the liner 110 on the epitaxial layer 102 side.

  Following the steps of FIG. 7, a gate dielectric layer 116 is formed on the epitaxial layer 102, as shown in FIG. The gate dielectric layer 116 comprises silicon oxide, silicon nitride, oxynitride, a high dielectric constant dielectric, other dielectric materials suitable for the gate dielectric, or combinations thereof. The high dielectric constant dielectric is a metal oxide such as Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy. , Ho, Er, Tm, Yb, Lu, and mixtures thereof. The gate dielectric layer 116 may be formed by conventional processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. It is formed by.

As shown in FIG. 9, after forming the gate dielectric layer 116, the two floating gates 118 are on the gate dielectric layer opposite the first column 112 in the active region 100a farthest from the termination region 100b. It is formed. The floating gate 118 is formed of a material including metal, polysilicon, tungsten silicide (WSi ₂ ), or a combination thereof. The floating gate 118 is formed using, for example, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), other suitable processes, or combinations thereof. In addition, as shown in FIG. 9, a plurality of floating gates 120 are simultaneously formed on the gate dielectric layer 116 in the termination region 100b, and the floating gate 120 is connected to a part of the second column 114 in the termination region 100b. A part of the epitaxial layer 102 is covered. The material and formation method of the floating gate 120 are the same as those of the floating gate 118 and will not be described in detail here.

  Following the step of FIG. 9, as shown in FIG. 10, a source region 122 is formed in the epitaxial layer 102 between the floating gates 118. The source region 122 is formed by a doping process common in the art, for example, an ion implantation process.

  Referring to FIG. 11, after forming source region 122, interlayer insulating film (ILD) layer 124 is formed. The ILD 124 is formed so as to cover the gate dielectric layer 116, the floating gate 118, and the floating gate 120 together with the contact hole 124 a exposing the source region 122.

  After the step of FIG. 11, a process of forming a contact plug is performed to complete the formation of the superjunction device. Referring to FIG. 12, contact plug 126 extending through contact hole 124a of ILD layer 124 is formed on source region 122, thereby completing formation of superjunction device 1000. Note that the superjunction device of FIG. 12 is formed from the structure shown in FIG. 4E, but as shown in FIG. 13, the superjunction device is also manufactured from the structure shown in FIG. 4D. That is. As shown in FIG. 13, in the example of fabricating a superjunction device from the structure shown in FIG. 4D, a liner 110 is formed on the sidewalls and bottom of the trench 104 and the trench 106 that are not covered by the implant blocking layer 108 ′. The

  The present invention uses the injection blocking layer 108 or the injection blocking layer 108 ′ to reduce the potential difference in the termination region of the superjunction device caused by diffusion of the dopant injected into the liner 110 at the bottom of the second trench 106. Prevent loss. This can reduce the electric field generated at the bottom of the trench in the termination region of the superjunction device that normally occurs in conventional superjunction devices. Also, since there is no high electric field at the bottom of the trench in the termination region, damage problems in the termination region of the superjunction device are effectively eliminated.

  In the present invention, preferred embodiments have been disclosed as described above, but these are not intended to limit the present invention in any way, and various modifications can be made without departing from the technical idea of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Substrate 100a ... Active region 100b ... Termination region 102 ... Epitaxial layer 104 ... First trench 106 ... Second trench 108 ... Injection blocking layer 108A ... First oxide layer 108B ... Nitride layer 108C ... Second dioxide layer 108A '... First Monoxide layer 108B '... Nitride layer 108C' ... Second dioxide layer 116 ... Gate dielectric layer 118 ... Floating gate 112 ... First column 120 ... Floating gate 122 ... Source region 124 ... ILD
126 ... Contact plug 210 ... Mask layer 300 ... Implantation process

Claims (11)

A first conductivity type substrate having an active region and a termination region;
An epitaxial layer of the first conductivity type on the substrate;
A plurality of first trenches in the epitaxial layer of the active region;
A plurality of second trenches in the epitaxial layer of the termination region;
An injection blocking layer formed on the epitaxial layer at the bottom of the first trench and the second trench;
A liner formed conformally along the sidewalls of the first and second trenches;
A dielectric material filling the first trench and the second trench defining a plurality of first columns and a plurality of second columns, respectively;
A second conductivity type region disposed in a portion adjacent to the liner along the sidewalls of the first trench and the second trench in the epitaxial layer;
A gate dielectric layer on the epitaxial layer;
Two floating gates formed on the gate dielectric layer;
A source region of a second conductivity type different from the first conductivity type formed between the two floating gates;
An interlayer dielectric layer covering the gate dielectric layer and the floating gate;
A contact plug formed on the source region through the interlayer insulating layer;
With
The liner has the second conductivity type dopant and a dielectric material;
The injection blocking layer includes an oxide-nitride-oxide composite layer, a nitride-oxide-nitride composite layer, an oxide-oxynitride-oxide composite layer, or a nitride-oxide composite layer. A semiconductor device including the semiconductor device.   The injection blocking layer includes a silicon oxide-silicon nitride-tetraethyl orthosilicate (hereinafter referred to as TEOS) oxide composite layer, and a thickness ratio between the silicon oxide, the silicon nitride, and the TEOS oxide is about 1. The semiconductor device according to claim 1, wherein the semiconductor device is 10: 1 to 10: 1 to 50.   2. The semiconductor device according to claim 1, wherein the total thickness of the injection blocking layer is about 300 to 5000 mm.   The semiconductor device according to claim 1, wherein the injection blocking layer covers the bottom portions of the first trench and the second trench.   A plurality of floating gates formed on the gate dielectric layer in the termination region, the floating gates covering a portion of the second column and a portion of the epitaxial layer in the termination region; The semiconductor device according to claim 1. Providing a first conductivity type substrate having an active region and a termination region;
Forming the first conductivity type epitaxial layer on the substrate;
Forming a plurality of first trenches in the epitaxial layer of the active region;
Forming a plurality of second trenches in the epitaxial layer of the termination region;
Forming an injection blocking layer on the epitaxial layer at the bottom of the first trench and the second trench;
Forming a liner equilaterally on the sidewalls of the first trench and the second trench;
Implanting a dopant of a second conductivity type different from the first conductivity type into the liner on the sidewalls of the first trench and the second trench to form a second conductivity type region ;
Filling the first trench and the second trench respectively with a dielectric material to form a plurality of first columns and a plurality of second columns;
Forming a gate dielectric layer on the epitaxial layer;
Forming two floating gates on the gate dielectric layer;
Forming a source region of the second conductivity type between the two floating gates;
Forming an interlayer dielectric layer covering the gate dielectric layer and the floating gate; and
Forming a contact plug on the source region through the interlayer insulating film,
The implantation blocking layer prevents the dopant from entering the bottom of the first trench and the second trench;
The injection blocking layer includes an oxide-nitride-oxide composite layer, a nitride-oxide-nitride composite layer, or a nitride-oxide composite layer,
The second conductivity type region is disposed in a portion of the epitaxial layer adjacent to the liner along the side walls of the first trench and the second trench.   The injection blocking layer includes a silicon oxide-silicon nitride-tetraethyl orthosilicate (hereinafter referred to as TEOS) oxide composite layer, and a thickness ratio between the silicon oxide, the silicon nitride, and the TEOS oxide is about 1 The method according to claim 6, wherein the method is from 10: 1 to 10: 1 to 10: 1 to 50.   The method of claim 6, wherein the total thickness of the injection blocking layer is about 300-5000 mm.   The method of claim 6, wherein the injection blocking layer covers the bottom of the first trench and the second trench.   The method of claim 6, wherein the injection blocking layer is formed by a high density plasma deposition process.   Forming a plurality of floating gates on the gate dielectric layer in the termination region, the floating gate covering a portion of the second column and a portion of the epitaxial layer in the termination region; 7. The method of claim 6, wherein:

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