TWI557916B - Semiconductor device and method of manufacturing the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present disclosure relates to semiconductor devices, and more particularly to a super junction semiconductor device and a method of fabricating the same.

In recent years, due to the promotion of environmentally friendly products and green technology, the industry has a large demand for power-saving electronic devices. To meet this growing demand, the semiconductor industry is paying more attention to the energy sector. Therefore, a super junction gold oxide half field effect transistor which can provide better energy efficiency has been developed. Compared with the traditional planar gold oxide half field effect transistor structure, the super junction gold oxide half field effect transistor can reduce the on-resistance to a very low level without affecting the voltage tolerance of the device. Therefore, a gold oxide half field effect transistor having a low on-resistance per unit area can be obtained.

A typical super junction gold oxide half field effect transistor device includes two regions: an active region (also referred to as a cell region) and a termination region. The terminal area of the super junction gold oxide half field effect transistor device is designed to sustain the transverse voltage of the device. When the voltage applied to the terminal area is small, a large electric field is generated in the vertical and horizontal directions of the device. Therefore, the terminal area of the device is prone to collapse.

Therefore, there is a need in the industry for an improved super junction gold oxide half field effect transistor device.

The present disclosure provides a semiconductor device including: a substrate having a first conductivity type and having an active region and a termination region; an epitaxial layer disposed on the substrate and having a first conductivity type; and a plurality of first trenches Provided in the epitaxial layer of the active region; a plurality of second trenches disposed in the epitaxial layer of the termination region; a implant barrier layer formed at the bottom of the first trench and the second trench; the liner layer, Having a second conductivity type and conforming along sidewalls of the first trench and the second trench, wherein the first conductivity type is different from the second conductivity type; the dielectric material is filled in the first trench and the second a trench, and respectively defining a plurality of first pillars and a plurality of second pillars; a gate dielectric layer disposed on the epitaxial layer; and two floating gates formed on the gate dielectric layer And disposed on the opposite side of the first pillar farthest from the terminal region; the source region is formed between the floating gates; the interlayer dielectric layer covers the gate dielectric layer and the floating gate; and contacts A plug is formed over the source region and through the interlayer dielectric layer.

The present disclosure further provides a method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type, wherein the substrate has an active region and a termination region; forming an epitaxial layer on the substrate, the epitaxial layer having a first conductivity Forming a plurality of first trenches in the epitaxial layer of the active region; forming a plurality of second trenches in the epitaxial layer of the termination region; forming a implant barrier layer on the first trench and the second trench a bottom portion; a lining is formed on the sidewalls of the first trench and the second trench; and the second conductive type dopant is implanted into the liner, wherein the first conductive type is different from the second conductive type, and the implant is blocked The layer blocks the dopant to prevent the dopant from entering the bottom of the first trench and the second trench; filling the dielectric material into the first trench and the second trench to form a plurality of first pillars and a plurality of second pillars, respectively Forming a gate dielectric layer on the epitaxial layer; forming two floating gates on the gate dielectric layer, and Two floating gates are disposed on opposite sides of the first pillar farthest from the termination region; a source region is formed between the floating gates; and an interlayer dielectric layer is formed to cover the gate dielectric layer and the floating gate And forming a contact plug on the source region and passing through the interlayer dielectric layer.

In order to make the features and advantages of the present disclosure more comprehensible, the preferred embodiments are described below, and are described in detail below with reference to the accompanying drawings.

100‧‧‧Base

100a‧‧‧active area

100b‧‧‧terminal area

102‧‧‧ epitaxial layer

104‧‧‧First groove

106‧‧‧Second trench

108‧‧‧ implant barrier

108A‧‧‧First oxide layer

108B‧‧‧ nitride layer

108C‧‧‧Second oxide layer

108’‧‧‧ implant barrier

108A’‧‧‧First oxide layer

108B’‧‧‧ nitride layer

108C’‧‧‧Second oxide layer

110‧‧‧ lining

112‧‧‧First column

114‧‧‧second column

116‧‧‧ gate dielectric layer

118‧‧‧Floating gate

120‧‧‧Floating gate

122‧‧‧ source area

124‧‧‧Interlayer dielectric layer

124a‧‧‧Contact opening

126‧‧‧Contact plug

210‧‧‧ Cover layer

300‧‧‧planting steps

A‧‧‧distance

B‧‧‧distance

C‧‧‧distance

D‧‧‧distance

E‧‧‧distance

Figs. 1 to 3, 4A to 4D', and 5 to 13 are cross-sectional views showing various stages of the method of manufacturing the superjunction semiconductor device of the present embodiment.

The semiconductor device of the present disclosure will be described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the various aspects of the disclosure. The specific elements and arrangements described below are provided to provide a brief description of the disclosure. Of course, these are only used as examples and not as a limitation of the disclosure. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the disclosure, and are not intended to be a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It is to be understood that the elements specifically described or illustrated may be in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

1-13 are the super junction semiconductor devices of the embodiments of the present disclosure. A cross-sectional view of each stage of the manufacturing process.

Referring to Figure 1, a substrate 100 having a first conductivity type is provided. this The substrate 100 has an active region 100a and a termination region 100b adjacent to the active region 100a. The substrate 100 can be a body substrate, an insulating layer overlying a substrate, or other similar substrate. In addition, substrate 100 can also be other suitable substrates, such as multilayer substrates, gradient substrates, hybrid oriented substrates, or other similar substrates. In some embodiments, the first conductivity type of the substrate 100 can be a P-type, for example, the substrate 100 can be a boron doped substrate. In other embodiments, the first conductivity type of the substrate 100 can be N-type, for example, the substrate 100 can be a phosphorus or arsenic doped substrate. Substrate 100 can also be any other suitable substrate. In an embodiment, the substrate 100 is a heavily doped N-type (N+) substrate.

Referring to FIG. 2, an epitaxial layer 102 having a first conductivity type is formed. On the substrate 100. The doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 102. For example, when the first conductivity type is N-type, the substrate 100 may be a heavily doped N-type (N+) substrate, and the epitaxial layer 102 may be a lightly doped N-type (N-) epitaxial layer. Depending on the size of the device, the epitaxial layer 102 can be formed by epitaxial growth to a thickness of about 1 μm to about 100 μm after the epitaxial layer 102, and a plurality of trenches are formed in the epitaxial layer 102. Referring to FIG. 3, a plurality of first trenches 104 are formed in the epitaxial layer 102 of the active region 100a, and a plurality of second trenches 106 are formed in the epitaxial layer 102 of the termination region 100b. The first trench 104 and the second trench 106 can be formed by a lithography and etching process. In some embodiments, the distance between the first trench 104 and the second trench 106 may vary in the direction of the active region 100a to the termination region 100b. For example, the distance between the first trench 104 and the second trench 106 may be increased from the active region 100a to the termination region 100b. In detail, the distance a is smaller than the distance b, the distance b is smaller than the distance c, the distance c is smaller than the distance d, and the distance d is smaller than the distance e. However, in other embodiments, the distance between the first trench 104 and the second trench 106 may be the same.

After forming the first trench 104 and the second trench 106, forming The implant barrier layer is in the first trench 104 and the second trench 106. 4A-4D illustrate a method of fabricating the implant barrier layer 108 of the disclosed embodiment. Referring to FIG. 4A, the first oxide layer 108A, the nitride layer 108B, and the second oxide layer 108C are sequentially formed on the epitaxial layer 102. The thickness ratio of the first oxide layer 108A, the nitride layer 108B, and the second oxide layer 108C is 1-10:1-10:1-50. The first oxide layer 108A and the second oxide layer 108C may include ruthenium oxide, tetraethyl orthosilicate (TEOS) oxide, or a combination thereof. The nitride layer 108B may include tantalum nitride, hafnium oxynitride or a combination thereof. In one embodiment, the first oxide layer 108A is a hafnium oxide layer, the nitride layer 108B is a tantalum nitride layer, and the second oxide layer 108C is a tetraethyl orthosilicate (TEOS) oxide layer. The first oxide layer 108A, the nitride layer 108B, and the second oxide layer 108C may be formed by a deposition step, such as chemical vapor deposition. Alternatively, the first oxide layer 108A, the nitride layer 108B, and the second oxide layer 108C may be formed by thermal growth by an oxidation or nitridation step. As shown in FIG. 4B, after the first oxide layer 108A, the nitride layer 108B, and the second oxide layer 108C are formed, the mask layer 210 is formed to fill the first trench exposing the surface of the second oxide layer 108C. The groove 104 and the second groove 106. Referring to FIG. 4C, the portions of the first oxide layer 108A, the nitride layer 108B, and the second oxide layer 108C that are not covered by the mask layer 210 are removed. This removal method can be wet etching. After the step of FIG. 4C, the mask layer 210 is removed. First oxide layer 108A, nitride layer 108B, and The portion of the dioxide layer 108C remaining forms a graft barrier layer 108, as shown in Figure 4D. In this embodiment, the implant barrier layer 108 does not directly contact the sidewalls of the trenches 104 and 106 and exposes the bottom sidewalls of the trenches 104 and 106. The implant barrier layer 108 has a total thickness of from 1000 angstroms to 5000 angstroms. In one embodiment, the implant barrier layer 108 has a total thickness of about 2000 angstroms.

FIG. 4D' illustrates a implant barrier layer 108 of another embodiment of the present disclosure. Sectional view. In the embodiment of Fig. 4D', the first oxide layer 108A', the nitride layer 108B', and the second oxide layer 108C' are formed directly on the bottoms of the trenches 104 and 106. The method of forming the first oxide layer 108A', the nitride layer 108B', and the second oxide layer 108C' may be, for example, high density plasma chemical vapor deposition (HDPCVD). In this embodiment, since the first oxide layer 108A', the nitride layer 108B', and the second oxide layer 108C' are formed only directly in the trenches 104 and 106, and by the film layers 108A', 108B', and 108C The resulting implant barrier layer 108' covers the bottom sidewalls of the trenches 104 and 106, so this embodiment does not require the removal step shown in Figures 4A-4C. The thickness ratio of the first oxide layer 108A', the nitride layer 108B', and the second oxide layer 108C' is about 1-10:1-10:1-50. The implant barrier layer 108' has a total thickness of from 1000 angstroms to 5000 angstroms. In one embodiment, the implant barrier layer 108' has a total thickness of about 2000 angstroms.

Although the implant barrier layer 108 of the 4D and 4D' patterns is oxide/nitrogen The oxide-nitride-oxide composite layer, the implant barrier layer 108 may also include other structures, such as a nitride-oxide-nitride composite layer, a nitride. /nitride-oxide composite layer, or oxide-oxynitride-oxide composite layer. In the following text, The present disclosure will be further illustrated by taking the implant barrier layer 108' of the 4D' diagram as an example.

As shown in Fig. 5, after forming the implant barrier layer 108', conforming The underlayer 110 is formed on the epitaxial layer 102. The liner 110 may comprise a dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride or other suitable material. It will be appreciated that although the steps of Figure 5 are implemented on the implant barrier layer 108' of Figure 4D', the steps of Figure 5 can also be implemented on the implant barrier layer 108 of Figure 4D. In the embodiment in which the liner 110 is formed on the implant barrier 108 of FIG. 4D, the liner 110 is also formed on the sidewalls and bottom of the trenches 104 and 106 that are not covered by the implant barrier 108. Liner layer 110 can have a thickness of between about 100 and 500 angstroms.

Referring to Figure 6, after the step of Figure 5, a planting step 300 is performed to implant the second conductivity type dopant into the liner 110 on the sidewalls of the trenches 104 and 106 at an angle. The first conductivity type is different from the second conductivity type. For example, when the first conductivity type is an N type, the second conductivity type is a P type. In the implanting step 300, the implant barrier layer 108' blocks the dopant to prevent dopants from entering the bottom of the trenches 104 and 106.

Referring to FIG. 7 , after the lining layer 110 is implanted with the second conductive type dopant, the dielectric material is filled into the first trench 104 and the second trench 106 to form a plurality of first pillars 112 and a plurality of Two columns 114. The dielectric material can be tantalum oxide, tantalum nitride, hafnium oxynitride, a low dielectric constant dielectric material, other suitable dielectric materials, or combinations thereof. The method of filling the dielectric material may include a deposition step and a chemical mechanical polishing step. This deposition step can include chemical vapor deposition. This chemical mechanical polishing step also removes the liner 110 on the epitaxial layer 102.

As shown in FIG. 8, after the step of FIG. 7, a gate dielectric layer 116 is formed on the epitaxial layer 102. The gate dielectric layer 116 may include tantalum oxide, tantalum nitride, Niobium oxynitride, high-k dielectric, other dielectric materials suitable as gate dielectric layers, or combinations thereof. The high-k dielectric may include metal oxides such as Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, An oxide of Dy, Ho, Er, Tm, Yb, Lu or a mixture thereof. The gate dielectric layer 116 can be formed by conventional steps in the art, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, thermal oxidation, UV-Ozone oxidation, or a combination thereof. .

As shown in FIG. 9, after the gate dielectric layer 116 is formed, two floating gates 118 are formed on the gate dielectric layer, and the two floating gates 118 are disposed at a distance from the gate dielectric layer 116. The opposite side of the first post 112 in the active zone 102a furthest from the termination zone 100b. The material of the floating gate 118 may include metal, polysilicon, tungsten germanium (WSi ₂ ), or a combination thereof. The method of forming the floating gate 118 can be low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, any other suitable step, or a combination thereof. In addition, as shown in FIG. 9, a plurality of floating gates 120 may be simultaneously formed on the gate dielectric layer 116 of the termination region 100b, and the floating gate 120 covers a portion of the second pillars in the termination region 100b. 114 and a portion of the epitaxial layer 102. The material and formation method of the floating gate 120 is similar to that of the floating gate 118, and thus the description will not be repeated.

As shown in FIG. 10, after the step of FIG. 9, the source region 112 is formed in the epitaxial layer 102 between the floating gates 118. The source region 112 can be formed by a doping step commonly used in the art, such as an ion implantation step.

Referring to FIG. 11, after the source region 112, an interlayer dielectric layer 124 is formed. The interlayer dielectric layer 124 can cover the gate dielectric layer 116 and the floating gate 118 and 120, and may have a contact hole 124a exposing the source region 112.

After the step of Figure 11, a contact plug is formed to complete the super junction Manufacturing of the device. Referring to FIG. 12, a contact plug 126 is formed over the source region 122 and extends through the contact opening 124a of the interlayer dielectric layer 124 to complete the fabrication of the superjunction device 1000. It should be understood that although the super junction device of Fig. 12 is manufactured from the structure of Fig. 4D', the super junction device can also be fabricated from the structure of Fig. 4D, as shown in Fig. 13. In an embodiment in which the superjunction device is fabricated from the structure of Figure 4D, the liner 110 is formed on the sidewalls and bottom of the trenches 104 and 106 that are not covered by the implant barrier layer 108', as shown in FIG.

The present disclosure uses a graft barrier 108 or 108' to prevent over-contact loading The terminal region is caused by the diffusion of the implant dopant in the liner 100 into the bottom of the second trench 106, thereby causing a voltage loss, thereby reducing the electric field generated by the conventional super junction device at the bottom of the trench at the termination region. Since the super junction device of the present disclosure has no high electric field at the bottom of the trench in the terminal region, the terminal region collapse problem of the super junction device can be effectively eliminated.

Although the embodiments of the present disclosure and their advantages have been disclosed above, It is understood that any person having ordinary skill in the art can make changes, substitutions, and refinements without departing from the spirit and scope of the disclosure. In addition, the scope of the disclosure is not limited to the processes, machines, manufactures, compositions, devices, methods, and steps in the specific embodiments described in the specification, and those of ordinary skill in the art may disclose the disclosure It is understood that the processes, machines, manufactures, compositions, devices, methods, and procedures that are presently or in the future may be used in accordance with the present disclosure as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present disclosure The above processes, machines, manufacturing, material compositions, devices, methods and steps are included. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the disclosure also includes a combination of the scope of the patent application and the embodiments.

100‧‧‧Base

100a‧‧‧active area

100b‧‧‧terminal area

102‧‧‧ epitaxial layer

108’‧‧‧ implant barrier

108A’‧‧‧First oxide layer

108B’‧‧‧ nitride layer

108C’‧‧‧Second oxide layer

110‧‧‧ lining

112‧‧‧First column

114‧‧‧second column

116‧‧‧ gate dielectric layer

118‧‧‧Floating gate

120‧‧‧Floating gate

122‧‧‧ source area

124‧‧‧Interlayer dielectric layer

126‧‧‧Contact plug

A‧‧‧distance

B‧‧‧distance

C‧‧‧distance

D‧‧‧distance

E‧‧‧distance

Claims (13)

A semiconductor device comprising: a substrate having a first conductivity type and having an active region and a termination region; an epitaxial layer disposed on the substrate and having the first conductivity type; a first trench is disposed in the epitaxial layer of the active region; a plurality of second trenches are disposed in the epitaxial layer of the termination region; and a implant barrier layer is formed on the first trench and the first trench a bottom of the trench; a liner having a second conductivity type and conforming along a sidewall of the first trench and the second trench, wherein the first conductivity type and the second conductivity type a dielectric material filling the first trench and the second trench, and defining a plurality of first pillars and a plurality of second pillars respectively; a gate dielectric layer disposed on the epitaxial layer Two floating gates are formed on the gate dielectric layer and disposed on opposite sides of the first pillar farthest from the termination region; a source region is formed on the floating Between the gates; an interlayer dielectric layer covering the gate dielectric layer and the floating gate; and a contact plug formed on the source region and wearing The interlayer dielectric layer. The semiconductor device of claim 1, wherein the implant barrier layer comprises an oxide/nitride/oxide composite layer, a nitride/oxide/nitride composite layer, and an oxide/nitrogen oxide An oxide/oxide composite layer or a nitride/oxide composite layer. The semiconductor device according to claim 1, wherein the implant resistance The barrier layer comprises a tetraethyl orthosilicate (TEOS) oxide composite layer, wherein the thickness ratio of yttrium oxide: tantalum nitride: tetraethyl citrate oxide is 1-10: 1-10:1-50. The semiconductor device of claim 1, wherein the implant barrier layer has a total thickness of 300-5000 angstroms. The semiconductor device of claim 1, wherein the implant barrier layer covers sidewalls of the first trench and the bottom of the second trench. The semiconductor device of claim 1, further comprising a plurality of floating gates formed on the gate dielectric layer of the termination region, wherein the floating gate covers a portion of the termination region Column and part of the epitaxial layer. A method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type, wherein the substrate has an active region and a termination region; forming an epitaxial layer on the substrate, the epitaxial layer Having the first conductivity type; forming a plurality of first trenches in the epitaxial layer of the active region; forming a plurality of second trenches in the epitaxial layer of the termination region; forming an implant barrier layer a trench and a bottom of the second trench; compliant forming a liner on sidewalls of the first trench and the second trench; implanting a second conductivity type dopant into the liner, wherein The first conductivity type is different from the second conductivity type, and the implant barrier layer blocks the dopant, preventing the dopant from entering the bottom of the first trench and the second trench; filling a dielectric material The first trench and the second trench respectively form a plurality of first pillars and a plurality of second pillars; forming a gate dielectric layer on the epitaxial layer; Forming two floating gates on the gate dielectric layer, and the two floating gates are disposed on opposite sides of the first pillar farthest from the terminal region; forming a source region Between the floating gates; forming an interlayer dielectric layer covering the gate dielectric layer and the floating gate; and forming a contact plug on the source region and passing through the interlayer dielectric layer. The method of fabricating a semiconductor device according to claim 7, wherein the implant barrier layer comprises an oxide/nitride/oxide composite layer, a nitride/oxide/nitride composite layer, and an oxide. / oxynitride / oxide composite layer, or a nitride / oxide composite layer. The method of manufacturing a semiconductor device according to claim 7, wherein the implant barrier layer comprises a tetraethyl orthosilicate (TEOS) oxide composite layer, wherein ruthenium oxide : Tantalum nitride: The thickness ratio of tetraethyl citrate oxide is 1-10:1-10:1-50. The method of fabricating a semiconductor device according to claim 7, wherein the implant barrier layer has a total thickness of 300 to 5000 angstroms. The method of fabricating a semiconductor device according to claim 7, wherein the implant barrier layer covers sidewalls of the first trench and the bottom of the second trench. The method of fabricating a semiconductor device according to claim 7, wherein the implant barrier layer is formed by a high density plasma deposition step. The method for fabricating a semiconductor device according to claim 7, further comprising forming a plurality of floating gates on the gate dielectric layer of the termination region, wherein The floating gate covers a portion of the second pillar and a portion of the epitaxial layer in the termination region.