CN115224108A - Three-dimensional memory structure - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
The invention provides a three-dimensional memory structure, which comprises a semiconductor substrate and a stack structure positioned on the semiconductor substrate, wherein the stack structure comprises gate layers and insulating medium layers which are alternately arranged; the array common-source structure penetrates through a channel hole of the stacked structure and the array common-source structure along a direction vertical to the semiconductor substrate, and a space is reserved between the channel hole and the array common-source structure; a source region located within the semiconductor substrate; the array common source structure comprises an inner core and an outer layer surrounding the inner core, wherein the inner core comprises a polycrystalline silicon filling layer; the outer layer includes a metal layer, the outer layer being electrically connected to the source region. The array common source structure comprises an outer layer and an inner core, the conditions of the whole stress, the resistance, the electric leakage and the like of the device can be improved by filling the inner core, the speed of the device is increased, and the performance of the device is optimized.
Description
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a three-dimensional memory structure.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to address the difficulties encountered with flat flash memory and to pursue lower production costs per unit cell, three-dimensional memory structures have come to light, which can result in each memory die in a memory device having a greater number of memory cells.
In a non-volatile memory, such as a NAND memory, one way to increase the memory density is by using a vertical memory array, i.e. a 3D NAND memory, and the existing 3D NAND flash memory manufacturing process mainly includes: firstly, a stacked structure formed by alternately stacking sacrificial layers and inter-gate dielectric layers is formed, and then the sacrificial layers are removed and filled to form a gate layer so as to obtain a 3D NAND flash memory, with the development of the process, in order to achieve higher storage density, the number of stacked layers in the 3D NAND flash memory is also significantly increased, such as 32 layers, 64 layers, 96 layers, even 128 layers and the like, however, with the increase of the number of stacked layers in the 3D NAND flash memory, the stress, resistance and the like of the device structure are difficult to effectively improve due to the filling of gate isolation grooves, the leakage current is increased, meanwhile, the process difficulty is increased, such as the difficulty in etching is increased, and in order to reduce the challenge of etching holes in the stacked structure, the height of each sacrificial layer is always compressed, so that the height of the whole stacked structure is reduced, but the Resistance (RS) of a gate word line layer (WL) is sharply increased, and the performance of the device is affected.
Therefore, it is necessary to provide a three-dimensional memory structure and a method for fabricating the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional memory structure, which is used to solve the problems in the prior art that the gate isolation trench filling causes the stress, resistance, leakage current, etc. of the device structure to be difficult to be effectively improved, and the gate word line resistance is increased due to the height of the compressed sacrificial layer.
To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensional memory structure, the method comprising the steps of:
providing a semiconductor substrate;
forming a laminated structure on the semiconductor substrate, forming a channel hole and a grid isolation groove with a space between the channel hole and the laminated structure, wherein the channel hole and the grid isolation groove penetrate through the laminated structure along a direction vertical to the semiconductor substrate;
forming a source electrode region in the semiconductor substrate corresponding to the bottom of the grid electrode separation groove; and
and forming an inner core and an outer layer surrounding the inner core in the grid isolation groove to form an array common source structure, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected with the source electrode region.
Optionally, the stacked structure includes sacrificial layers and insulating dielectric layers stacked alternately, and the preparation method includes the steps of:
removing the sacrificial layer based on the gate isolation grooves to form sacrificial gaps; and
and forming a gate layer in the sacrificial gap.
Optionally, the gate isolation groove includes N sub-gate isolation grooves which are communicated with each other up and down, where N is an integer greater than or equal to 2.
Optionally, the channel hole includes N sub-channel holes which are vertically communicated with each other, each sub-channel hole corresponds to each sub-gate separation groove one to one, and at least the 1 st sub-channel hole to the N-1 st sub-channel hole correspond to the 1 st sub-gate separation groove to the N-1 st sub-gate separation groove and are prepared based on the same process.
Optionally, the 1 st to N-1 st sub-channel holes and the 1 st to N-1 st sub-gate trenches are prepared based on the same process, the step of forming the N-1 st sub-channel hole and the N-1 st sub-gate trench includes the steps of forming the N-1 st sub-channel hole and preparing the N-1 st sub-channel hole to obtain the channel hole, and filling the channel hole with a functional material layer, and the step of filling the functional material layer further includes the steps of: and forming an N sub-grid isolation groove to prepare the grid isolation groove.
Optionally, the stack structure includes N sub-stack structures sequentially stacked in a direction perpendicular to the surface of the semiconductor substrate, each sub-stack structure corresponds to each sub-gate spacer, and the method for forming the gate spacer and the stack structure includes:
forming a bottom sub-laminated structure on the semiconductor substrate;
forming a bottom layer sacrificial column penetrating through the bottom layer sub-laminated structure in the bottom layer sub-laminated structure;
forming a top-layer sub-laminated structure on the bottom-layer sub-laminated structure and the bottom-layer sacrificial column;
forming a top-layer sub-gate separation groove exposing the lower-layer sacrificial column in the top-layer sub-laminated structure;
and removing the lower sacrificial columns through the top layer sub-grid isolation grooves.
Optionally, the method further includes, after forming the gate spacer, the steps of: and forming an isolation layer on the side wall of the grid isolation groove, wherein the outer layer is formed on the isolation layer.
Optionally, the method further includes, after forming the isolation layer, the steps of: and preparing a transition layer on the surface of the isolation layer, wherein the outer layer is formed on the surface of the transition layer.
Optionally, the method further includes, after forming the channel hole, the steps of: and forming a high-dielectric-constant dielectric layer on the inner wall of the channel hole, forming a functional side wall layer on the surface of the high-dielectric-constant dielectric layer, and forming a channel layer on the surface of the functional side wall layer.
Optionally, the manufacturing method further includes a step of manufacturing a bottom stacked structure on the semiconductor substrate, where the stacked structure is formed on the bottom stacked structure, and the manufacturing method further includes a step of manufacturing a bottom epitaxial layer at the bottom of the channel hole, where the bottom epitaxial layer is in contact with the bottom stacked structure, and a sidewall protection layer is formed on an outer wall of the epitaxial layer based on the bottom stacked structure.
Optionally, the process of forming the outer layer further includes forming a gate spacer cavity in the gate spacer based on the outer layer, the gate spacer cavity constituting the inner core, wherein the outer layer surrounds the gate spacer cavity.
Optionally, the method further comprises the following step after the outer layer is formed: and forming a conductive plug extending into the top of the grid isolation groove.
Optionally, the inner core comprises a polysilicon fill layer; the outer layer includes a metal layer.
Optionally, the metal layer comprises a fluorine-free tungsten layer.
The invention also provides a three-dimensional memory structure, which is preferably prepared by the three-dimensional memory preparation method provided by the invention, and the three-dimensional memory structure comprises:
a semiconductor substrate;
the stacked structure is positioned on the semiconductor substrate and comprises gate layers and insulating medium layers which are alternately arranged;
a channel hole and an array common source structure penetrating through the stacked structure in a direction perpendicular to the semiconductor substrate, the channel hole and the array common source structure having a spacing therebetween;
a source region located within the semiconductor substrate;
the array common source structure includes: the source electrode comprises an inner core and an outer layer surrounding the inner core, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected with the source electrode.
Optionally, the gate isolation groove includes N sub-gate isolation grooves which are communicated with each other up and down, where N is an integer greater than or equal to 2.
Optionally, the channel hole includes N sub-channel holes which are communicated with each other up and down, and each sub-channel hole corresponds to each sub-gate separation groove one to one; the stack structure comprises N sub-stack structures which are sequentially stacked in the direction vertical to the surface of the semiconductor substrate, and each sub-stack structure corresponds to each sub-grid separation groove one to one.
Optionally, the array common source structure further comprises an isolation layer surrounding the outer layer.
Optionally, the array common source structure further comprises a transition layer located between the isolation layer and the outer layer.
Optionally, the three-dimensional memory structure further includes a high-dielectric-constant dielectric layer, a functional sidewall layer, and a channel layer, which are sequentially stacked, wherein the high-dielectric-constant dielectric layer is formed on an inner wall of the channel hole.
Optionally, the three-dimensional memory structure further includes a gate spacer cavity formed in the gate spacer, the gate spacer cavity constituting the inner core, the outer layer surrounding the gate spacer cavity.
Optionally, the three-dimensional memory structure further comprises a conductive plug extending into a top of the gate spacer.
Optionally, the inner core comprises a polysilicon fill layer; the outer layer includes a metal layer.
Optionally, the metal layer comprises a fluorine-free tungsten layer.
As described above, in the three-dimensional memory structure and the manufacturing method of the invention, the gate isolation trench is filled into a structure at least including an inner core and an outer layer surrounding the inner core, so that the improvement of the overall stress, resistance, electric leakage and the like of the device can be realized by filling the inner core on the premise of outer layer conduction, and in addition, the gate isolation trench cavity is manufactured in the gate isolation trench, so that the stress caused by a material layer can be relieved, the stress of the whole device structure can be relieved, the resistance of the device can be reduced, and the performance of the device can be improved; meanwhile, the grid electrode separation groove of the three-dimensional memory is prepared into a structure comprising at least two sub-grid electrode separation grooves which are communicated up and down, and the arrangement of the plurality of sub-grid electrode separation grooves can enable the preparation of a single sub-grid electrode separation groove to be easy to control, so that the key size (CD) of the single sub-grid electrode separation groove can be reduced, the distance between a channel hole and the grid electrode separation groove is increased, the length of a subsequent grid electrode layer can be increased, the resistance of the grid electrode layer is reduced, the speed of a device is improved, and the performance of the device is optimized.
Drawings
FIG. 1 is a flow chart of a process for fabricating a three-dimensional memory structure according to the present invention.
Figure 2 shows a schematic representation of the provision of a semiconductor substrate in the fabrication of a three-dimensional memory structure of the present invention.
Fig. 3 is a schematic diagram illustrating the formation of a stacked structure in the fabrication of a three-dimensional memory structure according to the present invention.
Figure 4 is a schematic representation of the formation of gate spacers and channel holes for the fabrication of a three-dimensional memory structure in accordance with one embodiment of the present invention.
Fig. 5 is a diagram illustrating the formation of a first sub-gate spacer trench for the fabrication of a three-dimensional memory structure in accordance with an example of the present invention.
Figure 6 illustrates a schematic representation of the formation of a first sacrificial post for the fabrication of a three-dimensional memory structure in accordance with one example of the present invention.
Figure 7 illustrates a diagram for forming a second sub-stack structure for three-dimensional memory structure fabrication in an example of the present invention.
Fig. 8 is a diagram illustrating the formation of a second sub-gate spacer trench for the fabrication of a three-dimensional memory structure in accordance with an example of the present invention.
Figure 9 illustrates the formation of gate spacers and channel holes for the fabrication of a three-dimensional memory structure in accordance with one example of the present invention.
Figure 10 (a) is a diagram illustrating a top view of the formation of gate spacers in the fabrication of an exemplary three-dimensional memory structure of the present invention.
Figure 10 (b) is a diagram illustrating a top view of the formation of gate spacers in the fabrication of an exemplary three-dimensional memory structure of the present invention.
Figure 11 (a) shows a schematic representation of the formation of second sacrificial columns for the preparation of a three-dimensional memory structure in an example of the invention.
Fig. 11 (b) is a diagram illustrating the formation of a second sub-channel hole for the preparation of a three-dimensional memory structure according to an example of the invention.
FIG. 12 is a schematic representation of the formation of a high-k dielectric layer, a functional sidewall layer and a channel layer in a channel hole during the fabrication of a three-dimensional memory structure according to the present invention.
Fig. 13 is a schematic representation of the formation of a sacrificial epitaxial layer in the fabrication of a three-dimensional memory structure according to the present invention.
FIG. 14 is a schematic representation of the formation of an insulating spacer layer in the fabrication of a three-dimensional memory structure according to the present invention.
Fig. 15 is a schematic representation of the removal of the sacrificial epitaxial layer during the fabrication of the three-dimensional memory structure of the present invention.
Fig. 16 is a diagram illustrating the removal of the bottom sacrificial layer in the fabrication of the three-dimensional memory structure of the present invention.
FIG. 17 is a schematic representation of the formation of a sidewall protection layer in the fabrication of a three-dimensional memory structure according to the present invention.
Figure 18 is a diagram illustrating the formation of sacrificial gaps in the fabrication of a three-dimensional memory structure according to the present invention.
Fig. 19 (a) shows a schematic representation of the formation of a gate layer in the fabrication of an exemplary three-dimensional memory structure of the present invention.
Fig. 19 (b) shows a schematic representation of the formation of a gate layer in the fabrication of an exemplary three-dimensional memory structure of the present invention.
Fig. 20 (a) is a diagram illustrating an example of forming an outer layer and an inner core in the fabrication of a three-dimensional memory structure according to the present invention.
Figure 20 (b) is a diagram illustrating another example of forming an outer layer and an inner core in the fabrication of a three-dimensional memory structure according to the present invention.
Fig. 21 is a schematic diagram illustrating the formation of conductive plugs in the fabrication of a three-dimensional memory structure according to the present invention.
FIG. 22 is a schematic representation of the formation of a top capping layer in the fabrication of a three-dimensional memory structure according to the present invention.
Fig. 23 shows an example of the arrangement of the channel holes and the gate spacers in the three-dimensional memory structure of the present invention.
Fig. 24 is a graph showing resistance as a function of gate height.
Description of the element reference numerals
101 semiconductor substrate
102 laminated structure
102a sub-stack structure
103 insulating dielectric layer
104 sacrificial layer
105 bottom laminate structure
105a bottom dielectric layer
105b bottom sacrificial layer
106 channel hole
106a sub-channel hole
107 gate spacer
107a sub-gate spacer
108 sacrificial post
109 high dielectric constant dielectric layer
110 functional sidewall layer
111 channel layer
112 filling the insulating layer
113 insulation gap
114 sacrificial epitaxial layer
115 insulating spacer layer
116 sidewall protection layer
117 Gate layer
118 stack structure
118a sub-stack structure
119 barrier layer
120 outer layer
121 source region
122 conductive plug
123 inner core
124a first cover layer
124b second cover layer
125 connecting block
126 top layer of coating
127 bottom epitaxial layer
S1 to S2
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The first embodiment is as follows:
as shown in fig. 1, the present invention provides a method for manufacturing a three-dimensional memory structure, comprising the following steps:
providing a semiconductor substrate;
forming a laminated structure on the semiconductor substrate, and forming a channel hole and a grid isolation groove with a space between the channel hole and the laminated structure, wherein the channel hole and the grid isolation groove penetrate through the laminated structure along a direction vertical to the semiconductor substrate;
forming a source electrode region in the semiconductor substrate corresponding to the bottom of the grid electrode separation groove; and
and forming an inner core and an outer layer surrounding the inner core in the grid isolation groove to form an array common source structure, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected with the source electrode region.
The following will describe the fabrication process of the three-dimensional memory structure in detail with reference to the accompanying drawings.
As shown in S1 in fig. 1 and fig. 2, a semiconductor substrate is provided.
Specifically, the semiconductor substrate 101 may be selected according to actual requirements of a device, the semiconductor substrate 101 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, and the like, in other embodiments, the semiconductor substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or Silicon carbide, and the semiconductor substrate 101 may also be a stacked structure, such as a Silicon/Germanium-Silicon stacked layer, and in this embodiment, the semiconductor substrate 101 includes a monocrystalline Silicon substrate. The semiconductor substrate 101 may be an ion-doped substrate, and may be doped P-type or N-type, the semiconductor substrate 101 may further include a plurality of peripheral devices, such as field effect transistors, capacitors, inductors, and/or pn junction diodes, and the semiconductor substrate 101 may further include a peripheral circuit.
As shown in S2 of fig. 1 and fig. 3 to 12, a stacked structure 102 is formed on the semiconductor substrate 101, and a channel hole 106 and a gate isolation groove 107 having a distance from the channel hole 106 are formed in the stacked structure 102, wherein the channel hole 106 and the gate isolation groove 107 both penetrate through the stacked structure 102 along a direction perpendicular to the semiconductor substrate 101.
As an example, the gate isolation trench 107 includes N sub-gate isolation trenches 107a, N is greater than or equal to 2, see fig. 4 and 9. In other embodiments, the channel hole 106 also includes N sub-channel hole structures disposed in communication with each other.
As an example, the stacked structure 102 includes sacrificial layers 104 and insulating dielectric layers 103 stacked alternately.
Specifically, the stacked structure 102 includes insulating dielectric layers 103 and sacrificial layers 104 stacked alternately, the insulating dielectric layers 103 of the stacked structure 102 include but are not limited to silicon dioxide layers, the sacrificial layers 104 of the stacked structure 102 include but are not limited to silicon nitride layers, and the insulating dielectric layers 103 and the sacrificial layers have a certain selection ratio in the same etching/etching process to ensure that the insulating dielectric layers 103 are hardly removed when the sacrificial layers are removed. Wherein, the stacked structure can be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process. In an example, the stacked structure may include the insulating dielectric layers 103 and the sacrificial layers that are alternately stacked from bottom to top in sequence, both the bottom layer and the top layer of the stacked structure are the insulating dielectric layers 103, and an upper surface of the insulating dielectric layer 103 located at the top layer is an upper surface of the stacked structure. The number of layers of the insulating dielectric layer 103 and the sacrificial layer in the stacked structure may include 32 layers, 64 layers, 96 layers, 128 layers, or the like, and specifically, the number of layers of the insulating dielectric layer 103 and the sacrificial layer 104 in the stacked structure may be set according to actual needs, which is not limited herein.
According to the invention, the gate isolation groove 107 is prepared in the laminated structure, and the structure comprising at least two sub-gate isolation grooves 107a is further prepared, wherein three or more sub-gate isolation grooves 107a are arranged in a vertically communicated manner, and the arrangement of the plurality of sub-gate isolation grooves 107a can enable the preparation of a single sub-gate isolation groove 107a to be easily controlled, so that the Critical Dimension (CD) of the single sub-gate isolation groove can be reduced, and the critical dimension comprises the width of the gate isolation groove. At present, with the increase of the number of layers of the three-dimensional memory, in order to reduce the challenges to the holes (such as gate spacer grooves and CH), such as the difficulty of etching, and try to control the thinning of the sacrificial layer, so that the thickness of the whole stacked structure is thinned, and finally, the resistance of the filled Gate Layer (GL) is linearly increased, as shown in fig. 24, so as to affect the device performance, the scheme of the present invention is adopted, as shown in fig. 10, and the gate spacer grooves 107 including at least two sub-gate spacer grooves 107a are prepared, so that the characteristic size of the gate spacer grooves 107 can be reduced, the width of w in the figure can be reduced, and further, the distance between the channel holes 106 and the gate spacer grooves 107 can be increased, that is, the length of d can be increased, so that the length of the subsequent gate layer can be increased, the resistance of the gate layer can be reduced, the device speed can be increased, and the device performance can be optimized. The cross-sectional view of the structure shown in fig. 9 may bebase:Sub>A cross-section taken along the directionbase:Sub>A-base:Sub>A from the top view shown in fig. 10 (base:Sub>A), and fig. 10 (b) isbase:Sub>A schematic view showing another positional relationship between the gate spacer and the channel hole. It should be noted that the critical dimension of the gate spacer can be reduced by 50% from 180nm to 120nm by the process of the present invention, the dimension of d can be increased from 130nm to 160nm, and the resistivity after filling can be reduced by 20%.
Of course, in other embodiments, the gate isolation trench 107 may be a via hole formed by directly penetrating through the stacked structure 102, such as a gap formed by directly penetrating through all the stacked structures 102 after the channel hole 106 is formed, wherein the cross-sectional shape of the gate trench 107 at this time includes an inverted trapezoid.
As an example, as shown in fig. 5, the stacked structure 102 includes N sub-stacked structures 102a sequentially stacked in a direction perpendicular to the surface of the semiconductor substrate 101, each sub-stacked structure 102a corresponds to each sub-gate isolation trench 107a one-to-one, and the method for forming the gate isolation trench 107 and the stacked structure 102 includes:
forming a bottom sub-stack structure on the semiconductor substrate 101;
forming a bottom layer sacrificial column penetrating through the bottom layer sub-laminated structure in the bottom layer sub-laminated structure;
forming a top-layer sub-laminated structure on the bottom-layer sub-laminated structure and the bottom-layer sacrificial column;
forming a top-layer sub-gate separation groove exposing the lower-layer sacrificial column in the top-layer sub-laminated structure;
and removing the lower sacrificial columns through the top layer sub-grid isolation grooves.
Specifically, in an example, a method for forming the gate spacer 107 and the stacked structure 102 more specifically is provided, and includes the following specific steps:
forming a first sub-stack structure on the semiconductor substrate 101;
forming a first sub-grid separation groove penetrating through the first sub-laminated structure in the first sub-laminated structure;
filling a first sacrificial column in the first sub-grid separation groove;
forming a second sub-laminated structure on the first sub-laminated structure on which the first sacrificial post is formed, and forming a second sub-gate separation groove penetrating through the second sub-laminated structure in the second sub-laminated structure;
forming a second sacrificial post in the second sub-gate isolation groove;
continuing to form a subsequent sub-stack structure 102a, a sub-gate separation groove 107a and a sacrificial column 108 on the semiconductor substrate 101 until an nth sub-stack structure, an nth sub-gate separation groove and an nth-1 sacrificial column are formed, so that the top sub-gate separation groove exposes the sacrificial column in the lower sub-gate separation groove, wherein when the gate separation groove comprises two sub-gate separation grooves, the second gate separation groove is not filled;
each sacrificial post 108 is removed based on the top sub-gate spacer, resulting in the gate spacer 107 and the stacked structure 102.
Specifically, an example of preparing the gate spacer 107 and the stacked structure 102 according to the present invention is provided, wherein two sub-gate spacers 107a are illustrated in the drawing as an example, and certainly, three or more sub-gate spacers may be illustrated in other examples, and it should be noted that a plurality of sub-gate spacers 107a may be sequentially referred to as a first sub-gate spacer, a second sub-gate spacer, and a third sub-gate spacer from the semiconductor substrate 101 to an nth sub-gate spacer, similarly, the names of each sub-stacked structure 102a and each sacrificial post 108 are similar, and the nth sub-gate spacer, the nth sub-stacked structure, and the N sacrificial post correspond to one another, where the sub-gate spacers 107a correspond to the sub-stacked structure 102a refer to portions of the material layer of the stacked structure formed at the periphery of the sub-gate spacers 107a and in contact with the sub-gate spacers 107a, and the sub-gate spacers 107a correspond to the sub-gate posts 108.
In an example, as shown in fig. 5 to 11, the sub-gate separation groove 107a is illustrated as including two sub-gate separation grooves. As shown in fig. 5, first, the sub-stack structure 102a, i.e. the first sub-stack structure, is formed on the semiconductor substrate 101 in a manner consistent with the formation of the stack structure described above, and includes the sacrificial layer and the insulating dielectric layer 103 stacked alternately, the number of layers of each material layer is determined by actual arrangement, preferably, the material layer at the bottom and the material layer at the top of the sub-stack structure 102a are both set as the insulating dielectric layer 103, and then, the sub-gate separation groove 107a, i.e. the first sub-gate separation groove, is formed in the formed sub-stack structure 102a, which may be completed by an etching process; then, as shown in fig. 6, filling sacrificial columns, that is, the first sacrificial columns, in the formed sub-gate isolation grooves 107a, depositing a hole-filling sacrificial material layer on the surface of the structure by using a deposition process, and then performing a chemical mechanical polishing process to polish the tops of the sacrificial columns to be flush with the upper surface of the first sub-stack structure, thereby obtaining the first sacrificial columns, where the material of each sacrificial column may be polysilicon, and the sacrificial columns are removed in a subsequent process; then, as shown in fig. 7, continuing to alternately deposit the sacrificial layer and the insulating medium layer 103 on the structure on which the first sacrificial post is formed, and forming another layer of the sub-stacked structure 102a, i.e., the second sub-stacked structure; continuing, as shown in fig. 8, forming second sub-gate isolation grooves in the subsequently formed second sub-stack structure, and enabling the second sub-gate isolation grooves to be disposed in one-to-one correspondence with the first sub-gate isolation grooves formed before, and the sub-gate isolation groove 107a on the upper layer exposes the sacrificial post 108 filled in the sub-gate isolation groove 107a on the lower layer; finally, as shown in fig. 9, the first sacrificial columns in the lower layer are removed based on the second sub-gate isolation trench formed in the upper layer, so as to obtain a first sub-gate isolation trench and a second sub-gate isolation trench which are arranged in a vertically-communicated manner, and obtain the finally-required gate isolation trench, where each sacrificial column may be removed by wet etching, and it should be further noted that, in an optional example, when the gate isolation trench 107 includes three or more sub-gate isolation trenches 107a which are arranged in a vertically-communicated manner, in the preparation process, the sub-gate isolation trenches 107a formed in the first layer to the second last layer are filled with the sacrificial columns 108, and the last layer, that is, the sub-gate isolation trench 107a in the uppermost layer, is not etched, only the sub-channel via in the uppermost layer is etched, and the sacrificial layers in other sub-channel vias are removed, so as to form a vertically-communicated via structure. And then forming a storage structure in the through hole, etching the sub-grid separation groove on the uppermost layer, removing the sacrificial layer in other sub-grid separation grooves, and forming the grid separation grooves which are communicated up and down.
As an example, as shown in fig. 11 (a), the step of continuing to form the subsequent sub-stack structure 102a, the sub-gate separation groove 107a and the sacrificial post 108 on the semiconductor substrate 101 further includes: and filling the Nth sub-gate separation groove to form an Nth sacrificial column.
Specifically, in this example, the method further includes a step of filling the sacrificial column in the sub-gate isolation groove 107a at the topmost layer, that is, when the gate isolation groove 107 includes N sub-gate isolation grooves 107a, the nth sub-gate isolation groove is filled with the nth sacrificial column, so that an auxiliary material layer, such as a photoresist layer, can be conveniently formed on the gate isolation groove, and further, the performance of other processes is facilitated, for example, the gate isolation groove can be shielded, so that a process can be performed in the channel hole 106 in the stacked structure, and thus, the process in the channel hole can be prevented from affecting the gate isolation groove 107.
As an example, the channel hole 106 includes N sub-channel holes 106 which are disposed to be communicated with each other, and each of the sub-channel holes 106 corresponds to each of the sub-gate isolation grooves 107a one-to-one, wherein at least the 1 st sub-channel hole to the N-1 st sub-channel hole correspond to the 1 st sub-gate isolation groove to the N-1 st sub-gate isolation groove and are prepared based on the same process.
Specifically, in an example, the channel hole 106 includes N sub-channel holes 106 which are vertically connected to each other, and the sub-channel holes are a first sub-channel hole, a second sub-channel hole, and an nth sub-channel hole sequentially from the top of the semiconductor substrate 101, in an optional example, each of the sub-channel holes 106a corresponds to each of the sub-gate isolation grooves 107a one to one, that is, the nth sub-channel hole 106a corresponds to the nth sub-gate isolation groove 107a one to one, and both of the sub-channel holes and the nth sub-gate isolation groove are formed in the same sub-stacked structure 102a, and in an optional example, the corresponding sub-channel hole 106a and the corresponding sub-gate isolation groove 107a are prepared based on the same process, for example, after the first sub-stacked structure 102a is formed, a first sub-gate isolation groove 107a and a first sub-channel hole 106 are formed in the first sub-stacked structure 102a based on the same process.
As an example, the 1 st to N-1 st sub-channel holes and the 1 st to N-1 st sub-gate trenches are prepared based on the same process, the step of forming the N-1 st sub-channel hole and the N-1 st sub-gate trench and then preparing the N-1 th sub-channel hole to obtain the channel hole 106, and the step of filling the channel hole 106 with a functional material layer, the step of filling the functional material layer further including: an nth sub-gate spacer is formed to prepare the gate spacer 107.
Specifically, in an example, referring to fig. 11 (b), there is provided a process for preparing the channel hole 106 and the gate spacer 107 in a three-dimensional memory structure, in which an N-1 th sub-channel hole and a sub-channel hole before the N-1 th sub-gate spacer are prepared based on the same process as an N-1 th sub-gate spacer and a sub-gate spacer before the N-1 th sub-gate spacer, that is, a first sub-stack structure is formed on the semiconductor substrate, a first sub-gate spacer and a first sub-channel hole penetrating through the first sub-stack structure are formed in the first sub-stack structure, a first sacrificial post is filled in the first sub-gate spacer and the first sub-channel hole, the above steps are repeated until an N-1 th sub-stack structure, an N-1 th sub-channel hole, an N-1 th sub-gate spacer and an N-1 th sub-gate spacer are formed, after the above-mentioned steps are formed, forming an nth sub-stack structure on the obtained structure, and forming an nth sub-channel hole, in this case, not forming an nth sub-gate spacer groove in this step, at this time, removing each sacrificial post in each sub-channel hole based on the nth sub-channel hole to obtain each sub-channel hole, forming the channel hole 106, and further performing filling of a functional material layer in the channel hole, in one case, the functional material layer may be the aforementioned stack of the high dielectric constant dielectric layer, the functional sidewall, and the channel layer, and then, in this case, forming an nth sub-gate spacer groove in the nth sub-stack structure after the completion of the filling of the functional material layer, thereby removing each sacrificial post in each sub-gate spacer groove based on the nth sub-gate spacer groove, and obtaining each sub-grid electrode isolation groove to form the grid electrode isolation groove.
As an example, the step of forming the channel hole 106 further includes: forming a high-dielectric-constant dielectric layer 109 on the inner wall of the channel hole 106, forming a functional sidewall layer 110 on the surface of the high-dielectric-constant dielectric layer 109, and forming a channel layer 111 on the surface of the functional sidewall layer 110.
Specifically, in an example, as shown in fig. 12, the method further includes a step of forming the high-k dielectric layer 109, the functional sidewall layer 110, and the channel layer 111 in the channel hole 106, in an optional example, each sacrificial pillar is filled in the gate isolation groove 107, and the sacrificial pillar is filled in the sub-gate isolation groove 107a on the uppermost layer, at this time, a mask layer is formed on the obtained structure, the mask layer shields the gate isolation groove 107 and exposes the channel hole 106 to be processed, the channel hole 106 is processed based on the mask layer, for example, the sacrificial material layer in the channel hole 106 may be removed, and then a deposition process is performed in the channel hole 106, so that the gate isolation groove 107 may be protected.
Specifically, a high-K dielectric layer 109 is formed on the inner wall of the channel hole 106, that is, the high-K dielectric layer 109 (high-K dielectric layer) is formed on the sidewall and bottom surface of the channel hole 106, and a subsequently formed gate layer is in contact with the high-K dielectric layer 109, and may be made of aluminum oxide or the like, and may be formed by atomic layer deposition. The functional sidewall layer 110 is formed on the surface of the high-k dielectric layer 109, and in an alternative example, the functional sidewall layer 110 sequentially includes a barrier layer, a memory layer and a tunneling layer (not shown) from the sidewall of the trench hole 106 to the center.
Wherein the barrier layer may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; preferably, in this embodiment, an atomic layer deposition process is used to form the barrier layer on the sidewall surface of the channel hole 106; the memory layer may be formed using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; preferably, in this embodiment, the memory layer is formed by an atomic layer deposition process; the tunneling layer may be formed using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; preferably, in this embodiment, the tunneling layer is formed by using an atomic layer deposition process. In an example, the blocking layer may include, but is not limited to, a silicon oxide layer, the memory layer may include, but is not limited to, a silicon nitride layer, and the tunneling layer may include, but is not limited to, a silicon oxide layer. In one example, the barrier layer comprises a silicon oxide layer, the memory layer comprises a silicon nitride layer, and the tunneling layer comprises a silicon oxide layer, thereby forming a functional sidewall layer of an ONO structure.
Specifically, a channel layer 111 is further formed on the surface of the functional sidewall layer 110. Wherein, a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process may be adopted to form the channel layer 111 on the surface of the functional sidewall; preferably, in this embodiment, the channel layer 111 is formed on the surface of the functional sidewall by using an atomic layer deposition process, and in an example, the material of the channel layer 111 may include polysilicon. Of course, in other examples, the material of the channel layer 111 may be other semiconductor materials.
Specifically, in an example, the sum of the thicknesses of the high-k dielectric layer 109, the functional sidewall and the channel layer 111 may be less than half of the width of the channel hole 106, and at this time, a reserved space filled with an insulating layer is remained in the channel hole 106 after the channel layer 111 is formed. When the reserved space is reserved, a step of forming a filling insulating layer 112 in the channel hole 106 is further included, and the filling insulating layer 112 may be formed in the channel hole 106 by using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; preferably, in the present embodiment, an atomic layer deposition process is used to form the filling insulation layer 112 in the channel hole 106. The material of the filling insulation layer 112 may include an oxide dielectric layer, such as silicon oxide, etc., and the filling insulation layer may fill the channel hole 106. In addition, in an example, the insulation gap 113 may also be formed in the filling insulation layer 112 by controlling a deposition process parameter of the filling insulation layer 112.
As an example, the manufacturing of the three-dimensional memory structure further includes a step of forming a bottom epitaxial layer 127 at the bottom of the channel hole 106, wherein the bottom epitaxial layer 127 extends into the semiconductor substrate 101, and at least the channel layer 111 is in contact with the bottom epitaxial layer 127.
As an example, the method for manufacturing a three-dimensional memory structure further includes a step of manufacturing a bottom stacked structure 105 on the semiconductor substrate 101, and the stacked structure 102 is formed on the bottom stacked structure 105, wherein in an example, the bottom stacked structure 105 is included, an upper surface of the bottom epitaxial layer 127 is lower than an upper surface of the bottom stacked structure 105, and the method for manufacturing a three-dimensional memory structure further includes a step of forming a sidewall protection layer 116 on an outer wall of the bottom epitaxial layer 127 based on the bottom stacked structure 105. In an alternative example, the bottom stacked structure 105 may include a bottom dielectric layer 105a and a bottom sacrificial layer 105b located between adjacent bottom dielectric layers, wherein the upper surface of the bottom epitaxial layer 127 is higher than the upper surface of the bottom sacrificial layer 105 b. Alternatively, the bottom dielectric layer may include, but is not limited to, a silicon oxide layer, and the bottom sacrificial layer may include, but is not limited to, a silicon nitride layer.
As an example, the step of forming the gate spacer 107 further includes:
as shown in fig. 13, a sacrificial epitaxial layer 114 is formed at the bottom of the gate trench 107, in an example, the thickness of the sacrificial epitaxial layer 114 is greater than the distance from the upper surface of the bottom sacrificial layer to the bottom surface of the gate trench 107, and specifically, the sacrificial epitaxial layer 114 may be formed by, but not limited to, a Selective Epi (SEG) process;
further, as shown in fig. 14, an insulating isolation layer 115 is formed on the sidewall of the gate spacer 107; specifically, the insulating isolation layer 115 is formed on the bottom and the sidewall of the gate spacer 107, and then the insulating isolation layer 115 on the bottom of the gate spacer 107 is removed, wherein the insulating isolation layer 115 may include, but is not limited to, a silicon oxide layer;
next, as shown in fig. 15, the sacrificial epitaxial layer 114 is removed, and the sacrificial epitaxial layer 114 may be removed by using, but not limited to, a wet etching process;
next, as shown in fig. 16, the bottom sacrificial layer is removed based on the gate isolation trench 107 to form a bottom sacrificial gap, which may be removed by, but not limited to, a wet etching process, and further, in an alternative example, the sidewall protection layer 116 is formed on the sidewall of the bottom epitaxial layer 127, and a silicon oxide layer may be formed by, but not limited to, a thermal oxidation process as the sidewall protection layer 116;
finally, as shown in fig. 17, the insulating isolation layer 115 is removed, and the insulating isolation layer 115 may be removed by, but not limited to, a wet etching process.
As shown in fig. 18, the stacked structure 102 includes sacrificial layers and insulating dielectric layers stacked alternately, and the method for manufacturing the three-dimensional memory structure further includes the steps of: the sacrificial layer is removed on the basis of the gate spacer 107 to form a sacrificial gap.
Specifically, the sacrificial layer 104 may be removed by a wet etching process, and the sacrificial layer may be removed by wet etching using a wet etching solution which has a high etching removal rate for the sacrificial layer and is hardly removed by the insulating dielectric layer 103; specifically, the wet etching solution is placed in the gate spacer groove 107, and the wet etching solution laterally etches the sacrificial layer to completely remove the sacrificial layer.
In other embodiments, the sacrificial epitaxial layer 114 and the insulating isolation layer 115 may not be formed, and the sacrificial layer and the bottom sacrificial layer in the stacked-layer structure 103 may be removed through the gate spacer directly after the gate spacer 107 is formed. Resulting in the structure shown in fig. 18.
As shown in fig. 19, the manufacturing method further includes a step of forming a gate layer 117 in the sacrificial gap.
Fig. 19 (a) is a schematic structural diagram illustrating the formation of the gate layer 117 in the presence of the bottom stacked structure 105. In other embodiments, the bottom stacked structure 105 may not be present, and only the sacrificial layer in the stacked structure 102 needs to be removed when the sacrificial layer is removed through the gate isolation trench, and fig. 19 (b) shows a schematic structural diagram of forming the gate layer 117 when the bottom stacked structure 105 is not present.
Specifically, the gate layer 117 may be formed in the sacrificial gap by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the material of the gate layer 117 may include a metal (such as tungsten or cobalt, etc.) or silicon, and preferably, in this embodiment, the material of the gate layer 117 may include tungsten. In one example, the gate layer 117 is formed in the sacrificial gap and the gate layer is formed in the bottom sacrificial gap, so that the bottom stacked structure 105 including the bottom dielectric layers and the gate layer therebetween is obtained. In addition, in an example, the gate layer material is deposited in the gate isolation trench 107, and then a step of removing the gate layer material in the gate isolation trench 107 is further included.
As shown in S3 of fig. 1 and fig. 12, forming a source region 121 in the semiconductor substrate 101 corresponding to the bottom of the gate spacer 107;
as shown in S4 of fig. 1 and fig. 20 to 21, an inner core 123 and an outer layer 120 surrounding the inner core 123 are formed in the gate spacer 107 to form an array common source structure, wherein the inner core 123 and the outer layer 120 are made of different materials, and the outer layer 120 is electrically connected to the source region 121.
By way of example, the inner core 123 comprises a polysilicon fill layer.
As an example, the outer layer 120 includes a metal layer.
As an example, the metal layer includes a tungsten structural layer; as an example, the metal layer includes a fluorine-free tungsten layer.
Specifically, in this step, the outer layer 120 and the inner core 123 are formed in the gate isolation trench, wherein the filler in the gate isolation trench 107 may achieve its conductive function based on the outer layer, in an example, the outer layer 120 includes a tungsten structure layer, in a further optional example, the tungsten structure layer includes a fluorine-free tungsten layer, and the design of the fluorine-free tungsten layer may avoid preparation of a barrier layer, so that reduction of the size of the gate isolation trench may be facilitated, and increase of the distance between the trench hole and the gate isolation trench may be facilitated, so that the length of a subsequent gate layer may be increased, the resistance of the gate layer may be reduced, the device speed may be increased, and the device performance may be optimized. In addition, the filling of the gate spacer 107 is designed to be the filling manner of the outer layer 120 and the inner core 123, so that the performance of the entire gate spacer filling can be improved based on the material of the inner core 123 and the like on the premise of realizing the function of the gate spacer in the device, in an example, the material of the inner core 123 may be a material having a resistance smaller than that of the tungsten structure layer, so that the resistance of the entire filling can be improved, and the device performance can be improved, in an optional example, the inner core 123 includes a polysilicon filling layer, as shown in fig. 20 (a). Of course, in other examples, the inner core 123 may also be an air cavity formed without additional filling of the material layer, such as a gate spacer cavity described later, as shown in fig. 20 (b). In addition, the tungsten structure layer may be a single tungsten material layer, or may be a laminated structure of a tungsten material layer and other material layers, such as a laminate with other metals, as the outer layer.
As an example, as shown in fig. 20 (b), the process of forming the outer layer 120 further includes forming a gate spacer cavity in the gate spacer 107 based on the outer layer 120, the gate spacer cavity constituting the inner core 123, and the outer layer 120 surrounding the gate spacer cavity.
Specifically, in one example, the outer layer 120 can be formed by an atomic layer deposition process to facilitate forming the outer layer 120 on the surface of the isolation layer, thereby facilitating the formation of the gate spacer cavity. For example, it may be a tungsten layer formed by an atomic layer deposition process.
As an example, as shown in fig. 21, after forming the outer layer 120, the method further includes: at least a conductive plug 122 is prepared in the gate spacer 107, and the conductive plug extends into the top of the gate spacer, so that the conductive plug and the outer layer 120 enclose the gate spacer cavity 123.
By way of example, the conductive plug is prepared using a physical vapor deposition process with a low void fill.
Specifically, as shown in fig. 21, the method further includes a step of forming a conductive plug 122 in the gate isolation trench 107, where the conductive plug 122 is formed at a top position of the gate isolation trench 107 and contacts with the outer layer 120 to achieve electrical connection, and the conductive plug 122 and the outer layer 120 jointly enclose the gate isolation trench cavity, which can relieve stress generated by surrounding material layers, reduce resistance, ground, relieve stress of the entire device structure, and reduce leakage current. In addition, the conductive plug 122 is formed in the gate isolation trench 107 and extends to the material layer at the periphery of the gate isolation trench 107, for example, as shown in fig. 21, it may extend into the first capping layer 124a and the second capping layer 124b formed on the stacked structure.
In one example, as shown in fig. 20, the step of forming the gate spacer further includes: an isolation layer 119 is formed on sidewalls of the gate spacer 107, and an outer layer 120 is formed on a surface of the isolation layer 119, in one example, after forming the gate layer 117 in the sacrificial gap.
Specifically, an isolation layer may be formed on the sidewall of the gate isolation trench 107, the isolation layer may be formed on the sidewall and the bottom of the gate isolation trench 107 first, then the isolation layer at the bottom of the gate isolation trench 107 is removed, and then the outer layer 120 is formed on the surface of the isolation layer, wherein the isolation layer may be formed on the sidewall of the gate isolation trench 107 by using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the isolation layer is used to electrically isolate the outer layer 120 from the gate layer 117, and the isolation layer may be made of a material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or the like.
As an example, the method further includes, after forming the isolation layer, the steps of: and preparing a transition layer on the surface of the isolation layer, wherein the outer layer is formed on the surface of the transition layer. In other embodiments, the metal layer may be formed directly on the surface of the isolation layer without including the transition layer. Specifically, in an example, the outer layer 120 is formed on the surface of the transition layer, wherein the transition layer may be a titanium layer, a titanium nitride layer, or a stacked structure of the two.
As an example, the step of forming the outer layer 120 may further include: source regions 121 are formed in the semiconductor substrate 101 corresponding to the bottoms of the gate spacers 107, wherein the outer layer 120 is in contact with the source regions 121.
Specifically, in an example, ion implantation may be performed on the semiconductor substrate 101 at the bottom of the gate spacer 107 to form the source region 121, in an optional example, when ion implantation is performed on the semiconductor substrate 101 at the bottom of the gate spacer 107, the bottom isolation layer oxide layer at the bottom of the gate spacer 107 is not removed, that is, the source region is formed after the isolation layer is formed, and the presence of the bottom oxide layer may protect the semiconductor substrate 101 during ion implantation to avoid lattice damage to the semiconductor substrate 101, and of course, in other examples, the source region may also be formed before the isolation layer is formed, as shown in fig. 12. In one example, the method further comprises removing the bottom oxide layer after forming the source region in the semiconductor substrate 101 at the bottom of the gate spacer 107. Specifically, the bottom oxide layer may be removed by a dry etching process or a wet etching process. The spacers may be formed prior to the sidewalls and bottom of the gate spacer 107, and in order to ensure that the outer layer 120 formed in the gate spacer 107 is in electrical contact with the source region, the method further includes removing the spacers located at the bottom of the gate spacer 107 after the spacers are formed.
Specifically, in an example, referring to fig. 21, the method further includes a step of preparing a connection block 125 after the material layer is completely prepared in the channel hole 106, in an example, after the channel hole 106 is filled, a first covering layer 124a is prepared on the surface of the obtained semiconductor structure and patterned, the channel hole 106 is shown, a conductive material is deposited on the top of the corresponding channel hole 106 to form the connection block 125, the connection block is located on the top of the channel hole 106 and is in contact with the functional sidewall and the channel layer 111 to realize electrical connection, and a second covering layer 124b is prepared on the obtained structure after the connection block 125 is formed, wherein the material of the first covering layer 124a and the second covering layer 124b includes but is not limited to silicon oxide, in an example, when the conductive plug is formed, the conductive plug extends into the first covering layer 124a and the second covering layer 124b, and optionally, the upper surface of the conductive plug is higher than the upper surface of the first covering layer 124a, and the upper surface of the conductive plug is lower than the upper surface of the second covering layer 124 b.
Specifically, in one example, after the conductive plug is formed, a top capping layer 126 is further prepared on the resulting semiconductor structure, and the top capping layer contacts the conductive plug. In one example, when the first cover layer and the second cover layer are formed, the top cover layer also extends into the second cover layer where it is in contact with the conductive plug.
It should be further noted that, in an example, the transition layer includes a titanium layer and a titanium nitride layer formed in sequence, the titanium layer is prepared by an HP (high density deposition) process, the titanium nitride layer is prepared by an atomic layer deposition process, the outer layer includes a tungsten layer and is prepared by an atomic layer deposition process, the inner core includes the gate spacer cavity, the conductive plug includes a tungsten conductive plug obtained by physical vapor deposition and chemical mechanical polishing, and a cost can be saved by 50% compared with a process for preparing a conductive material by polysilicon filling, polysilicon etching back and chemical vapor deposition of tungsten metal.
Example two:
as shown in fig. 22 and 23, referring to fig. 1 to 21, the present invention further provides a three-dimensional memory structure, which is preferably prepared by the preparation method of the present invention, and the three-dimensional memory structure includes:
a semiconductor substrate 101;
a stacked structure 118 located on the semiconductor substrate, wherein the stacked structure 118 comprises gate layers 117 and insulating medium layers 103 which are alternately arranged;
a channel hole 106 and an array common source structure passing through the stacked structure 118 in a direction perpendicular to the semiconductor substrate 101, the channel hole 106 and the array common source structure having a spacing therebetween;
a source region 121 located within the semiconductor substrate;
the array common source structure includes: an inner core 123 and an outer layer 120 surrounding the inner core 123, the inner core 123 being of a different material than the outer layer 120, the outer layer 120 being electrically connected to the source region 121.
By way of example, the gate isolation trench 107 includes N sub-gate isolation trenches 107a arranged in a vertically-connected manner, where N is an integer greater than or equal to 2.
Specifically, the semiconductor substrate 101 may be selected according to actual requirements of a device, the semiconductor substrate 101 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, and the like, in other embodiments, the semiconductor substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or Silicon carbide, and the semiconductor substrate 101 may also be a stacked structure, such as a Silicon/Germanium-Silicon stacked layer, and in this embodiment, the semiconductor substrate 101 includes a monocrystalline Silicon substrate. The semiconductor substrate 101 may be an ion-doped substrate, may be P-doped or N-doped, and the semiconductor substrate 101 may further include a plurality of peripheral devices, such as field effect transistors, capacitors, inductors, and/or pn junction diodes, and the semiconductor substrate 101 may further include a peripheral circuit.
Specifically, the stacked structure includes insulating dielectric layers 103 and sacrificial layers 104 stacked alternately, the insulating dielectric layers 103 of the stacked structure include but are not limited to silicon dioxide layers, the sacrificial layers of the stacked structure include but are not limited to silicon nitride layers, and the insulating dielectric layers 103 and the sacrificial layers have a certain selection ratio in the same etching/etching process to ensure that the insulating dielectric layers 103 are hardly removed when the sacrificial layers are removed. In an example, the stacked structure may include the insulating dielectric layers 103 and the sacrificial layers that are alternately stacked in sequence from bottom to top, both the bottom layer and the top layer of the stacked structure are the insulating dielectric layers 103, and an upper surface of the insulating dielectric layer 103 located at the top layer is an upper surface of the stacked structure. The number of layers of the insulating dielectric layers 103 and the sacrificial layers in the stacked structure may include 32, 64, 96, or 128 layers, and the like, and specifically, the number of layers of the insulating dielectric layers 103 and the sacrificial layers in the stacked structure may be set according to actual needs, which is not limited herein.
In the stacked structure, an array common source structure is formed, wherein the array common source structure is formed based on the gate spacer 107 and its internal filler, and the internal filler at least includes the inner core and the outer layer. The gate isolation groove 107 is prepared in the stacked structure, and a structure including at least two sub-gate isolation grooves 107a is further prepared, three or more sub-gate isolation grooves 107a are arranged in an up-and-down communication manner, wherein the arrangement of the plurality of sub-gate isolation grooves 107a can enable the preparation of a single sub-gate isolation groove 107a to be easily controlled, so that the Critical Dimension (CD) including the width of the gate isolation groove can be reduced. At present, with the increase of the number of layers of the three-dimensional memory, in order to reduce the challenges to the holes (such as the gate spacer grooves 107 and ch), such as the difficulty of etching, and try to control the thinning of the sacrificial layer, so that the thickness of the whole stacked structure is thinned, and finally, the resistance of the filled Gate Layer (GL) is linearly increased, as shown in fig. 24, so as to affect the device performance, the scheme of the present invention is adopted, as shown in fig. 10, so that the characteristic size of the gate spacer groove 107 can be reduced, the width of w in the figure is reduced, and further, the distance between the channel hole 106 and the gate spacer groove 107 can be increased, that is, the length of d is increased, so that the length of the subsequent gate layer can be increased, the resistance of the gate layer is reduced, the device speed is increased, and the device performance is optimized. It should be noted that the critical dimension of the gate spacer groove can be reduced by 50% from 180nm to 120nm by adopting the process of the present invention, the dimension of d can be increased from 130nm to 160nm, and the resistivity after filling can be reduced by 20%.
As an example, the stacked structure 118 includes N sub-stacked structures 118 sequentially stacked in a direction perpendicular to the surface of the semiconductor substrate 101, and each sub-stacked structure 118 corresponds to each sub-gate isolation trench 107a one-to-one.
As an example, the channel hole 106 includes N sub-channel holes 106 that are disposed to be communicated with each other, and each of the sub-channel holes 106 corresponds to each of the sub-gate isolation grooves 107a one-to-one.
Specifically, the plurality of sub-gate trenches 107a may be sequentially referred to as a first sub-gate trench 107a, a second sub-gate trench 107a, a third sub-gate trench 107a, and an nth sub-gate trench 107a from the semiconductor substrate 101 to the first sub-gate trench 107a, and similarly, the names of the sub-stacked structures 102a are similar, the nth sub-gate trench 107a and the nth sub-stacked structure 102a correspond to each other one by one, and the sub-gate trench 107a and the sub-stacked structure 102a correspond to each other, which is a portion of a material layer of a stacked structure formed on the periphery of the sub-gate trench 107a and contacting the sub-gate trench 107 a. In an example, the channel hole 106 includes N sub-channel holes 106, which are disposed in a vertical direction and are sequentially a first sub-channel hole 106, a second sub-channel hole 106, and an nth sub-channel hole 106 from the semiconductor substrate 101 to the top, in an optional example, each sub-channel hole 106 corresponds to each sub-gate isolation groove 107a one by one, that is, the nth sub-channel hole 106 corresponds to the nth sub-gate isolation groove 107a one by one, and both sub-channel holes and the nth sub-gate isolation grooves are formed in the same sub-stacked structure 102a, in an optional example, the corresponding sub-channel hole 106 and the corresponding sub-gate isolation groove 107a are prepared based on the same process, for example, after the first sub-stacked structure 102a is formed, a first sub-gate isolation groove 107a and a first sub-channel hole 106 are formed in the first sub-stacked structure 102a based on the same process.
As an example, the three-dimensional memory structure further includes a high-k dielectric layer 109, a functional sidewall layer 110, and a channel layer 111, which are sequentially stacked, wherein the high-k dielectric layer 109 is formed on an inner wall of the channel hole 106.
Specifically, a high-K dielectric layer 109 is formed on the inner wall of the channel hole 106, that is, a high-K dielectric layer 109 (high-K dielectric layer) is formed on the sidewall and bottom surface of the channel hole 106, and a subsequently formed gate layer is in contact with the high-K dielectric layer 109, and may be made of aluminum oxide or the like. The functional sidewall layer 110 is formed on the surface of the high-k dielectric layer 109, and in an alternative example, the functional sidewall layer 110 sequentially includes a barrier layer, a memory layer and a tunneling layer (not shown) from the sidewall of the trench hole 106 to the center. In an example, the blocking layer may include, but is not limited to, a silicon oxide layer, the memory layer may include, but is not limited to, a silicon nitride layer, and the tunneling layer may include, but is not limited to, a silicon oxide layer. In one example, the barrier layer comprises a silicon oxide layer, the memory layer comprises a silicon nitride layer, and the tunneling layer comprises a silicon oxide layer, thereby forming a functional sidewall layer 110 of an ONO structure. Specifically, a channel layer 111 is further formed on the surface of the functional sidewall layer 110, and in an example, a material of the channel layer 111 may include polysilicon. Of course, in other examples, the material of the channel layer 111 may be other semiconductor materials.
Specifically, in an example, the sum of the thicknesses of the high-k dielectric layer 109, the functional sidewall and the channel layer 111 may be less than half of the width of the channel hole 106, and at this time, a reserved space filled with an insulating layer is remained in the channel hole 106 after the channel layer 111 is formed. Wherein, when the pre-space is reserved, a step of forming a filling insulation layer in the channel hole 106 is further included, wherein a material of the filling insulation layer may include an oxide dielectric layer, such as silicon oxide and the like, and the filling insulation layer may fill the channel hole 106. In addition, in an example, the insulation gap 113 may also be formed in the filling insulation layer by controlling a deposition process parameter of the filling insulation layer.
As an example, the three-dimensional memory structure further includes a bottom epitaxial layer 127 formed at the bottom of the channel hole 106, wherein the bottom epitaxial layer 127 extends into the semiconductor substrate 101, and at least the channel layer 111 is in contact with the bottom epitaxial layer 127.
As an example, a bottom stacked structure 105 is further formed on the semiconductor substrate 101, the bottom stacked structure 105 is located between the semiconductor substrate 101 and the stacked structure, and the bottom stacked structure 105 may include a bottom dielectric layer and a bottom sacrificial layer located between adjacent bottom dielectric layers. Alternatively, the bottom dielectric layer may include, but is not limited to, a silicon oxide layer, and the bottom sacrificial layer may be made of a material identical to that of the gate layer. Fig. 19 (a) is a schematic structural diagram illustrating the formation of the gate layer 117 in the presence of the bottom stacked structure 105. In other embodiments, the bottom stacked structure 105 may not be present, and only the sacrificial layer in the stacked structure 102 needs to be removed when the sacrificial layer is removed through the gate isolation trench, and fig. 19 (b) shows a schematic structural diagram of forming the gate layer 117 when the bottom stacked structure 105 is not present.
Illustratively, a sidewall protection layer 116 is further formed on a portion of the outer wall of the bottom epitaxial layer 127, wherein the sidewall protection layer 116 is located at the periphery of the bottom epitaxial layer 127, in an example, in a gap corresponding to the bottom sacrificial layer in the bottom stacked structure 105.
Specifically, the three-dimensional memory structure further includes a source region 121, the source region is formed in the semiconductor substrate 101 corresponding to the bottom of the gate spacer 107, and the outer layer 120 is in contact with the source region.
Specifically, an ion implantation process may be used to perform ion implantation on the semiconductor substrate 101 at the bottom of the gate spacer 107 to form an ion implantation region, so as to obtain the source region.
By way of example, the inner core 123 comprises a polysilicon fill layer.
As an example, the outer layer 120 includes a metal layer.
As an example, the metal layer includes a tungsten structural layer; as an example, the metal layer includes a fluorine-free tungsten layer.
Specifically, the outer layer 120 and the inner core 123 are formed in the gate isolation trench, wherein the filler in the gate isolation trench 107 may realize its conductive function based on the outer layer, in an example, the outer layer 120 includes a tungsten structure layer, in a further optional example, the tungsten structure layer includes a fluorine-free tungsten layer, and the fluorine-free tungsten layer is designed to avoid preparation of a barrier layer, so that reduction of the size of the gate isolation trench may be facilitated, and increase of the distance between a channel hole and the gate isolation trench may be facilitated, so that the length of a subsequent gate layer may be increased, the resistance of the gate layer may be reduced, the device speed may be increased, and the device performance may be optimized. In addition, the filling of the gate spacer 107 is designed to be the filling manner of the outer layer 120 and the inner core 123, so that the performance of the entire gate spacer filling can be improved based on the material of the inner core 123 and the like on the premise of realizing the function of the gate spacer in the device, in an example, the material of the inner core 123 may be a material having a resistance smaller than that of the tungsten structure layer, so that the resistance of the entire filling can be improved, and the device performance can be improved, in an optional example, the inner core 123 includes a polysilicon filling layer, as shown in fig. 20 (a). Of course, in other examples, the inner core 123 may also be an air cavity formed without additional filling of the material layer, such as the gate spacer cavity described, as shown in fig. 20 (b). In addition, the tungsten structure layer may be a single tungsten material layer, or may be a laminated structure of a tungsten material layer and other material layers, such as a laminate with other metals, as the outer layer.
As an example, the three-dimensional memory structure further includes an isolation layer 119, the isolation layer 119 is formed on the sidewall of the gate spacer 107, and the outer layer 120 is formed on the surface of the isolation layer, that is, the array common source structure further includes the isolation layer 119 surrounding the outer layer 120.
As an example, the three-dimensional memory structure further includes a transition layer formed on the surface of the isolation layer 119, and the outer layer 120 is formed on the surface of the transition layer, that is, the array common source structure further includes a transition layer located between the isolation layer 119 and the outer layer 120.
Specifically, the material of the isolation layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, etc., and in an example, the outer layer 120 is formed on the surface of the transition layer, wherein the transition layer may be a titanium layer, a titanium nitride layer, or a stacked structure of the two.
As an example, the three-dimensional memory structure further comprises a gate spacer cavity formed in the gate spacer 107, the outer layer 120 surrounding the gate spacer cavity, the gate spacer cavity constituting the inner core.
As an example, the three-dimensional memory structure further includes a conductive plug 122, the conductive plug 122 is formed at least in the gate isolation groove 107, the conductive plug 122 extends into the top of the gate isolation groove 107, and the conductive plug 122 and the outer layer 120 enclose the gate isolation groove cavity.
Specifically, the conductive plug 122 is formed at the top of the gate isolation trench 107 and contacts the outer layer 120 to realize electrical connection, and the conductive plug 122 and the outer layer 120 together enclose the gate isolation trench cavity, which can relieve stress generated by surrounding material layers, reduce resistance, ground, relieve stress of the entire device structure, and reduce leakage current. In addition, the conductive plug 122 is formed in the gate isolation trench 107 and extends to the material layer at the periphery of the gate isolation trench 107, for example, as shown in fig. 21, it may extend into the first and second capping layers formed on the stacked structure.
Specifically, in an example, the three-dimensional memory structure further includes a connection block, the connection block is located at the top of the channel hole 106 and contacts the functional sidewall and the channel layer 111 to achieve electrical connection, the connection block may be located in a first cover layer, the first cover layer is located on the surface of the stacked structure, and in addition, the connection block further includes a second cover layer covering the surface of the first cover layer, wherein when the conductive plug is formed, the conductive plug extends into the first cover layer and the second cover layer, optionally, the upper surface of the conductive plug is higher than the upper surface of the first cover layer, and the upper surface of the conductive plug is lower than the upper surface of the second cover layer.
Specifically, in one example, after the conductive plug is formed, a top cover layer is further prepared on the obtained semiconductor structure, and the top cover layer is in contact with the conductive plug. In one example, when the first cover layer and the second cover layer are formed, the top cover layer also extends into the second cover layer where it is in contact with the conductive plug.
In summary, the present invention provides a three-dimensional memory structure and a method for fabricating the same, the method comprising the following steps: providing a semiconductor substrate; forming a laminated structure on the semiconductor substrate, and forming a channel hole and a grid isolation groove with a space between the channel hole and the laminated structure, wherein the channel hole and the grid isolation groove penetrate through the laminated structure along a direction vertical to the semiconductor substrate; forming a source electrode region in the semiconductor substrate corresponding to the bottom of the grid electrode separation groove; and forming an inner core and an outer layer surrounding the inner core in the grid isolation groove to form an array common source structure, wherein the inner core and the outer layer are made of different materials, and the outer layer is electrically connected with the source electrode region. According to the scheme, the grid isolation groove is filled into the structure at least comprising the inner core and the outer layer surrounding the inner core, the overall stress, resistance, electric leakage and other conditions of the device can be improved through the filling of the inner core on the premise of outer layer conduction, and in addition, the grid isolation groove cavity is prepared in the grid isolation groove, so that the stress caused by the material layer can be relieved, the stress of the whole device structure can be relieved, the resistance of the device can be reduced, and the performance of the device can be improved; meanwhile, the grid electrode separation groove of the three-dimensional memory is prepared into a structure comprising at least two sub-grid electrode separation grooves which are communicated up and down, and the arrangement of the plurality of sub-grid electrode separation grooves can enable the preparation of a single sub-grid electrode separation groove to be easy to control, so that the key size (CD) of the single sub-grid electrode separation groove can be reduced, the distance between a channel hole and the grid electrode separation groove is increased, the length of a subsequent grid electrode layer can be increased, the resistance of the grid electrode layer is reduced, the speed of a device is improved, and the performance of the device is optimized. The invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A three-dimensional memory structure, the three-dimensional memory structure comprising:
a semiconductor substrate;
the stacked structure is positioned on the semiconductor substrate and comprises gate layers and insulating medium layers which are alternately arranged;
a channel hole and an array common source structure penetrating through the stacked structure in a direction perpendicular to the semiconductor substrate, the channel hole and the array common source structure having a spacing therebetween;
a source region located within the semiconductor substrate;
the array common source structure includes: an inner core and an outer layer surrounding the inner core, the inner core comprising a polysilicon filler layer; the outer layer includes a metal layer, the outer layer being electrically connected to the source region.
2. The three-dimensional memory structure of claim 1, wherein the array common source structure further comprises an isolation layer surrounding the outer layer.
3. The three-dimensional memory structure of claim 2, wherein the array common source structure further comprises a transition layer between the isolation layer and the outer layer.
4. The three-dimensional memory structure of claim 1, further comprising a high-k dielectric layer, a functional sidewall layer, and a channel layer stacked in sequence, wherein the high-k dielectric layer is formed on an inner wall of the channel hole.
5. The three-dimensional memory structure of claim 1, wherein the metal layer comprises a fluorine-free tungsten layer.
6. The three-dimensional memory structure of claim 1, further comprising a bottom stack structure on the semiconductor substrate, the stack structure being formed on the bottom stack structure.
7. The three-dimensional memory structure of claim 1, further comprising a bottom epitaxial layer formed at the bottom of the channel hole in contact with the bottom stack structure, and a sidewall protection layer formed on an outer wall of the bottom epitaxial layer.
8. A three-dimensional memory structure, the three-dimensional memory structure comprising:
a semiconductor substrate;
the stacked structure is positioned on the semiconductor substrate and comprises gate layers and insulating medium layers which are alternately arranged;
a channel hole and an array common source structure penetrating through the stacked structure in a direction perpendicular to the semiconductor substrate, the channel hole and the array common source structure having a spacing therebetween;
a source region located within the semiconductor substrate;
the array common source structure includes: an inner core and an outer layer surrounding the inner core, the inner core comprising a polysilicon filler layer; the outer layer comprises a metal layer, and the outer layer is electrically connected with the source electrode region;
and the conductive plug is positioned on the upper part of the inner core, and at least part of the conductive plug is in contact with the outer layer.
9. The three-dimensional memory structure of claim 8, wherein the array common source structure further comprises an isolation layer surrounding the outer layer.
10. The three-dimensional memory structure of claim 9, wherein the array common source structure further comprises a transition layer between the isolation layer and the outer layer.
11. The three-dimensional memory structure of claim 8, further comprising a high-k dielectric layer, a functional sidewall layer, and a channel layer stacked in sequence, wherein the high-k dielectric layer is formed on an inner wall of the channel hole.
12. The three-dimensional memory structure of claim 8, wherein the metal layer comprises a fluorine-free tungsten layer.
13. The three-dimensional memory structure of claim 8, further comprising a bottom stack structure on the semiconductor substrate, the stack structure being formed on the bottom stack structure.
14. The three-dimensional memory structure of claim 8, further comprising a bottom epitaxial layer formed at the bottom of the channel hole in contact with the bottom stack structure, and a sidewall protection layer formed on an outer wall of the bottom epitaxial layer.
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