DE102015116579A1 - Superjunction semiconductor device and manufacturing method - Google Patents

Abstract

In one embodiment, a method of manufacturing a semiconductor device is described. A first pattern of first trenches (108) is formed in a semiconductor body (105). The first pattern includes a first center-to-center distance (p1) along a first lateral direction (x). First areas are formed and arranged according to the first pattern. Thereafter, a second pattern of second trenches (114) is formed in the semiconductor body (105). The second pattern includes a second center-to-center distance (p2) along the first lateral direction (x). An offset between the first and second patterns along the first lateral direction (x) is less than each of the first and second center-to-center distances (p1, p2). Second regions are formed and arranged according to the second pattern.

Description

BACKGROUND

Superjunction (SJ) semiconductor devices, for example, SJ insulated gate field effect transistors (SJ IGFETs) or SJ bipolar insulated gate transistors (SJN IGBTs) are based on mutual space charge compensation of n- and p-doped regions in a semiconductor body, to allow an improved balance between low area-specific on-resistance Ron × A and high breakdown voltage Vbr between load terminals, such as source and drain. As SJ semiconductor devices shrunk to smaller center-to-center pitches in combination with substantial depths of charge compensation regions, manufacturing processes become challenging in terms of process stability and reliability.

It is desirable to improve stability and reliability of a manufacturing process of SJ semiconductor devices and to provide respective SJ semiconductor devices.

SUMMARY

The invention is defined in the independent claims. Further embodiments are given in the dependent claims.

The present description relates to a method of manufacturing a superjunction semiconductor device. A first pattern or a first structure of first trenches or trenches is formed in a semiconductor body. The first pattern includes a first center-to-center distance along a first lateral direction. First areas are formed and arranged according to the first pattern. Thereafter, a second pattern of second trenches or trenches is formed in the semiconductor body. The second pattern includes a second center-to-center distance along the first lateral direction. An offset between the first and second patterns along the first lateral direction is less than each of the first and second center-to-center distances. Second regions are formed and arranged according to the second pattern.

The present disclosure also relates to a superjunction semiconductor device. The superjunction semiconductor device includes a superjunction structure. The superjunction structure comprises a contiguous zone in a semiconductor body and a plurality of stripe-shaped areas spaced apart and located in a two-dimensional array with respect to a surface of the semiconductor body. At least some of the plurality of strip-shaped portions include a curved portion.

Those skilled in the art will recognize additional features and advantages after reading the following detailed description and considering the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this disclosure. The drawings illustrate the embodiments of the present invention and, together with the description, serve to explain principles of the invention. Other embodiments of the invention and intended advantages will be readily appreciated as they become better understood by reference to the following detailed description.

1 FIG. 10 is a schematic flowchart for illustrating a method of manufacturing a semiconductor device. FIG.

2A to 2F 10 are schematic sectional views of a semiconductor body for illustrating process features of manufacturing a superjunction semiconductor device.

2G to 2I 12 are schematic cross-sectional views illustrating process features for fabricating superjunction semiconductor transistors including planar gates and turn gates.

3A and 3B FIG. 15 are schematic plan views of a semiconductor body illustrating various geometries and a layout of charge compensation regions. FIG.

4A to 4C 10 are schematic plan views of a semiconductor body illustrating arrays of stripe-shaped charge compensation regions including curved parts at opposite end portions of the stripe-shaped charge compensation regions.

5A to 5C FIG. 15 are schematic plan views of a semiconductor body illustrating arrays of stripe-shaped charge compensation regions including curved parts in one. FIG Middle of the strip-shaped charge compensation areas.

LONG DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which, for purposes of illustration, specific embodiments are shown in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment may be used in or in connection with other embodiments to arrive at yet another embodiment. It is intended that the present invention include such modifications and changes. The examples are described by means of a specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustration purposes only. For clarity, the same elements are indicated by corresponding reference numerals in the various drawings, unless otherwise stated.

The terms "have," "include," "include," "have," and similar terms are open-ended terms, and these terms indicate the presence of the identified structures, elements, or features, but do not exclude the presence of additional elements or features , The indefinite articles and the definite articles are meant to denote both the plural and the singular, unless the context clearly dictates otherwise.

The term "electrically connected" describes a permanent low-resistance connection between electrically connected elements, for example a direct contact between the relevant elements or a low-resistance connection via a metal and / or a heavily doped semiconductor. The term "electrically coupled" includes that one or more intermediate elements suitable for signal transmission may be present between the electrically coupled elements, for example, elements that temporarily comprise a low resistance connection in a first state and a high impedance electrical isolation in one provide second state.

The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n ^- " means a doping concentration lower than the doping concentration of an "n" -doping region, while an "n ⁺ " -doping region has a higher doping concentration than an "n" -doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

The terms "wafer," "substrate," "semiconductor body" or "semiconductor substrate" used in the following description may include any semiconductor-based structure having a semiconductor surface. Wafer and structure are understood to include silicon (Si), silicon on insulator (SOI), silicon on sapphire (SOS), doped and undoped semiconductors, silicon epitaxial layers supported by a base semiconductor pad, and others Semiconductor structures include. The semiconductor does not need to rely on silicon. The semiconductor could also be silicon germanium (SiGe), germanium (Ge) or gallium arsenide (GaAs). In other embodiments, silicon carbide (SiC) or gallium nitride (GaN) may form the semiconductor substrate material.

The term "horizontal" as used in the present specification is intended to describe an orientation substantially parallel to a first or major surface of the semiconductor substrate or body. This may be, for example, the surface of a wafer or of a semiconductor die or of a semiconductor chip.

The term "vertical" as used in the present specification is intended to indicate an orientation substantially perpendicular to the first surface, i. H. is arranged parallel to the normal direction of the first surface of the semiconductor substrate or body.

In this specification, a second surface of the semiconductor substrate or semiconductor body is considered to be formed by the lower or back or rear surface while the first surface is considered to be formed by the upper, front or main surface of the semiconductor substrate. The terms "above" and "below" as used in the present specification therefore indicate a relative position of a structural feature to each other.

In this description, exemplary embodiments are illustrated that include p-type and n-type semiconductor regions. Alternatively, the semiconductor devices may be formed with opposite doping relationships such that the n-doped p-doped regions shown and the n-doped regions shown are p-doped.

The semiconductors may have terminal contacts, such as contact pads (or electrodes), that allow electrical contact with the integrated circuit or a discrete semiconductor device contained in the semiconductor body. The electrodes may include one or more electrode metal layers deposited on the semiconductor material of the semiconductor chips. The electrode metal layers may be fabricated with any desired geometric shape and material composition. For example, the electrode metal layers may be in the form of a layer covering a surface. Any desired metal, for example, Cu, Ni, Sn, Au, Ag, Pt, Pd, Al, Ti and an alloy of one or more of these metals may be used as the material. The electrode metal layer (s) do not need to be homogeneous or straight made of a material, i. That is, various compositions and concentrations of the materials contained in the electrode metal layer and electrode metal layers are possible. As an example, the electrode layers may be sized large enough to be bonded to a wire.

In the exemplary embodiments disclosed here, one or more conductive layers, in particular electrically conductive layers, are applied or applied. It should be emphasized that any such term as "formed" or "applied" or "applied" is intended to literally cover all types and techniques of applying layers. In particular, they are intended to cover techniques in which layers are applied as a whole, such as lamination techniques, and techniques in which layers are applied in a sequential manner, such as sputtering, coating, forming, CVD (chemical vapor deposition), physical vapor deposition (PVD), evaporation, hybrid physico-chemical vapor deposition (HPCVD), etc.

The deposited conductive layer may include, but is not limited to, one or more of a layer of metal such as Al, Cu or Sn or an alloy thereof, a layer of conductive paste and a layer of bonding material. The layer of a metal may be a homogeneous layer. The conductive paste may comprise metal particles dispersed in a volatilizable or curable polymeric material, which paste may be fluid, viscous or waxy. The bonding material can be applied to electrically and mechanically connect the semiconductor chip, for example, to a carrier or, for example, a contact clip or a contact clip. A soft solder material or, in particular, a solder material capable of forming diffusion solder bonds may be used, for example a solder material comprising one or more of Sn, SnAg, SnAu, SnCu, In, InAg, InCu and InAu.

A dicing process can be used to divide the wafer into individual chips. Any technique for dicing may be used, for example, blade sawing, laser dicing, etching, etc. The semiconductor body, for example, a semiconductor wafer, may be diced by attaching the semiconductor wafer on a tape, particularly a dicing tape, a dicing pattern. in particular, a rectangular pattern to which semiconductor wafers are applied, for example, according to one or more of the above-mentioned techniques, and by drawing the tape along, for example, four orthogonal directions in the plane of the tape. By pulling the tape, the semiconductor wafer is divided into a plurality of semiconductor dies (chips).

1 FIG. 10 is a schematic flowchart illustrating a method. FIG 100 for manufacturing a semiconductor device.

It should be emphasized that while the procedure 100 presented as a series of acts or events and described below, the illustrated order of such acts or events should not be interpreted in a limiting sense. For example, some acts may occur in different orders and / or concurrently with other acts or events that are different from the acts or events depicted and / or described herein. In addition, not all acts shown may be necessary to carry out one or more aspects of embodiments of the invention hereof. Also, one or more of the actions specified herein may be performed in one or more separate acts and / or phases.

A process feature S100 includes forming a first pattern of first trenches in a semiconductor body, wherein the first pattern includes a first center-to-center distance along a first lateral direction. The semiconductor body may be a preprocessed single crystal semiconductor substrate, for example a single crystal silicon substrate (Si substrate), a SiC substrate, a GaN substrate, a GaAs substrate or a silicon on insulator substrate. The semiconductor body may be none, one or a plurality of doped and / or have undoped layers on the single crystal semiconductor substrate, for example, epitaxial semiconductor layers. As an example, a thickness of the semiconductor layer (s) formed on the single-crystalline semiconductor substrate and doping of the one or more layers may be appropriately selected in view of a desired voltage blocking capability of the semiconductor device to be formed in the semiconductor body is. In particular, the doping level of the semiconductor body should be chosen such that the charge compensation of the final compensation device is adequate for a desired blocking behavior.

A process feature S110 includes forming first regions, wherein the first regions are arranged according to the first pattern and the first structure, respectively. For example, the first regions may be processed in and / or through sidewalls of the first trenches.

Process features S120 and S130 are executed according to process features S100 and S110.

A process feature S120 includes forming a second pattern of second trenches in the semiconductor body, the second pattern having a second center-to-center distance along the first lateral direction, and an offset between the first and second Patterns along the first lateral direction is less than or less than each of the first and second center-to-center distances.

A process feature S130 includes forming second regions, wherein the second regions are arranged according to the second pattern. The second regions can be processed, for example, in and / or through side walls of the second trenches.

In some embodiments, prior to performing the process feature S100, the semiconductor body is provided by forming one or a plurality of layers on the single crystal semiconductor substrate. The plurality of layers includes dopants of the first and second conductivity types, for example, n-type dopants in silicon, such as one or more of phosphorus (P), arsenic (As), antimony (Sb), and / or p-type dopants in silicon, such as boron (B), aluminum (Al), gallium (Ga), indium (In). A plurality of layers may be formed by repeatedly forming a single layer and doping the single layer in situ or by ion implantation and / or outdiffusion of a diffusion source with n- and / or p-type dopants. In some embodiments, each monolayer is doped with n- or p-type dopants. In some other embodiments, each monolayer is doped with n- or p-type dopants. A thermal process may follow to enhance homogenization of the dopants along a vertical direction perpendicular to a surface of the semiconductor body.

The first and second trenches may be formed by a suitable process, such as dry and / or wet etching. As an example, the first and second trenches may be formed in a silicon body by an anisotropic plasma etching process, such as reactive ion etching (RIE) using a suitable etching gas, for example, at least one of Cl ₂ , Br ₂ , CCl ₄ , CHCl ₃ , CHBr ₃ , BCl ₃ , HBr. According to one embodiment, sidewalls of the first and second trenches may be slightly tapered, for example, including a cone angle between 88 ° and 90 °. Slightly tapered trench sidewalls may be advantageous in avoiding trench cavities as the first and second trenches are filled.

In some embodiments, the first and second trenches are the same in dimensions. Equal dimensions may include, for example, equal lateral dimensions of the first and second trenches on a surface of the semiconductor body from which each of the first and second trenches extend into the semiconductor body. By way of example, identical dimensions can also include identical vertical expansions or depths of the first and second trenches in the semiconductor body. Examples of geometries of the first and second trenches on a surface or in a plane at a vertical distance to the surface of the semiconductor body from which the first and second trenches extend into the semiconductor body include circular, elliptical, polygonal, square, and striped geometries, for example, corners caused by process technology may be rounded. For example, additional trenches having different dimensions than the first and second trenches may be present in an edge termination area surrounding, for example, an active area for changing a charge balance.

In some embodiments, the first and second center-to-center distances are the same. As one example, the offset may be one-half of each one of the first and second center-to-center distances.

In some embodiments, each of the first and second patterns is a two-dimensional array.

Each one of the first and second patterns may be an array of stripe-shaped trenches arranged successively along the first lateral direction, each one of the stripe-shaped trenches extending along a second lateral direction that is different from the first lateral direction. For example, the first and second lateral directions may be perpendicular to each other.

In some embodiments, forming each of the first and second regions includes forming semiconductor material in the corresponding one trench of the first and second trenches. The semiconductor material may be formed by an epitaxial growth process such as chemical vapor deposition (CVD) such as atmospheric pressure (APCVD), sub-atmospheric pressure (SACVD) or low-pressure CVD (LPCVD).

In some embodiments, forming each of the first and second regions includes introducing dopants of the second conductivity type into the semiconductor body through sidewalls of the corresponding one trench of the first and second trenches. In some embodiments, the process of introducing dopants into the semiconductor body comprises plasma doping.

Plasma doping across sidewalls of the first and second trenches permits high dose high energy implantation and is also known as PLAD (plasma doping) or PIII (plasma immersion ion implantation). These methods allow accurate doping of a portion of the semiconductor body at the sidewalls of the first and second trenches. Compliant doping of the portion of the semiconductor body at the sidewalls of the first and second trenches can be accomplished by applying a voltage to a substrate surrounded by a radio frequency (RF) plasma containing a dopant gas. Collisions between ions and neutral atoms as well as biasing of the substrate result in a broad annular distribution of the dopants, allowing for homogeneous doping across the trench sidewalls. Also, a small vertical gradient in the dose of doping in the part of the semiconductor body can be achieved by plasma doping. This allows vertical variation of a degree of charge compensation, which enhances manufacturing stability and / or avalanche robustness. A vertical variation of a doping dose may be less than 20% or less than 10% or less than 5%. When PLAD doping occurs, the semiconductor substrate, such as a semiconductor wafer, is exposed to a plasma containing ions of dopants. These ions are accelerated by an electric field to the substrate and implanted in an exposed surface of the substrate. An implanted dose may be adjusted or controlled via DC pulses, such as negative voltage pulses. A Faraday system allows adjustment or control of the dose. Two sets of coils, d. H. a horizontal coil and a vertical coil, make it possible to generate the plasma and keep it homogeneous. An ion density can be adjusted over a distance between the coils and the substrate. An interaction between the vertical coils and the horizontal coils allows adjustment or control of homogeneity and ion density. A penetration depth of the dopants into the semiconductor body and the implantation dose can be adjusted via a pulsed DC voltage, which lies between the semiconductor substrate and a surrounding shielding ring.

In some embodiments, forming the first and second regions by plasma doping comprises introducing the dopants into a portion of the semiconductor body via the sidewalls at a dose in a range of 5 × 10 ¹¹ cm ^-2 to 5 × 10 ¹² cm ^-2 or in one Range of 7 × 10 ¹¹ cm ^-2 to 2 × 10 ¹² cm ^-2 . This comparatively low dose requires modifications to the pulsed DC voltage typically used. Typical doses exceeding 10 ¹⁵ cm ^-2 are implanted using these techniques. According to one exemplary embodiment, a pulse interval of the DC voltage pulses is set in a range of 100 μs to 10 ms, in particular between 500 μs and 5 ms. For example, a DC pulse rise time may be set to a value less than 0.1 μs. According to one embodiment, a pulse width is between 0.5 μs and 20 μs or between 1 μs and 10 μs.

In some embodiments, further, for plasma doping the portion of the semiconductor on the sidewalls of the first and second trenches, there may be variation of doping along the vertical direction in a silicon semiconductor body by high energy implantation of protons for n-type doping or helium for p-type doping be achieved. This allows an increase in avalanche robustness of the device.

In some embodiments, the semiconductor body comprises a drift zone of the first conductivity type. Doping the portion of the semiconductor body at sidewalls of the first and second trenches by plasma doping comprises doping the portion of the semiconductor body with dopants of a second conductivity type complementary to the first conductivity type. The doped part of the semiconductor body on sidewalls of the first Trenches forms first charge compensation regions, for example a p-doped pillar, between an n-doped drift zone of a superjunction semiconductor device. The doped part of the semiconductor body on sidewalls of the second trenches forms second charge compensation regions, for example a p-doped pillar, between an n-doped drift zone of a superjunction semiconductor device. In some embodiments, the semiconductor device is a power semiconductor device having a breakdown voltage or a voltage blocking capability of at least 100 V or at least 300 V.

In some embodiments, introducing dopants of the second conductivity type into the semiconductor body includes ion implantation, for example, oblique implantation through sidewalls of each of the first and second trenches.

In some embodiments, the method further comprises filling each of the first and second trenches with at least one of a semiconductor and a dielectric material. If the first and second trenches are filled with semiconductor material, the semiconductor material may be undoped or may typically comprise a doping concentration below the doping concentration introduced by the plasma doping described above, or may have a doping concentration similar to the doping of the semiconductor body 210 so that it can contribute to a low resistance current flow. In some embodiments, thermal heating is performed to further expand a lateral doping profile of dopants introduced by plasma doping and / or ion implantation and / or diffusion. When the first and second trenches of intrinsic or lightly doped semiconductor material are filled together with a semiconductor body comprising first dopants of a first conductivity type and second dopants of a second conductivity type, a drift zone and charge compensation regions may be formed by doping the intrinsic or lightly doped semiconductor material into the first and second trenches are formed by a thermal diffusion process that introduces more of the first dopants into the semiconductor material than the second dopants to thereby form net p-doped and n-doped regions. In some embodiments, the drift zone is formed in a region comprising the semiconductor material in the first and second trenches, and a charge compensation region is formed in a region that includes at least a portion of the adjacent semiconductor body surrounding the first and second trenches. In some other embodiments, the charge compensation region is formed in a region comprising the semiconductor material in the first and second trenches, and the drift zone is formed in a region comprising at least a portion of the adjacent semiconductor body surrounding the first and second trenches.

Other processes for fabricating a superjunction semiconductor device may be performed, for example, processes for forming body, source, drain, gate, contact (s), wiring (s), and dielectric (a).

The 2A to 2I are schematic sectional views of a semiconductor body 105 to illustrate processes of a method of manufacturing a superjunction semiconductor device.

With reference to the schematic sectional view 200 from 2A becomes a first pattern or structure of first trenches 108 in the semiconductor body 105 educated. The semiconductor body may be of a first conductivity type, a second conductivity type other than the first conductivity type, or may include first and second conductivity type dopants. The first pattern includes a first center-to-center distance p1 along a first lateral direction x. The first trenches 108 can at a first surface 109 of the semiconductor body 105 be formed by a masked etching process, for example by dry etching. A mask pattern can be formed, for example, by photolithography. The mask pattern may be formed, for example, as a hard mask pattern or as a resist pattern. The first surface 109 of the semiconductor body 105 is opposite to a second surface 110 ,

With reference to the schematic sectional view 201 from 2 B For example, first regions of a second conductivity type different from the first conductivity type are arranged according to the first pattern by filling the first trenches with first semiconductor material 112 , For example, an epitaxial silicon layer formed by epitaxial processes. Excess material on the first surface 109 can be removed by chemical and / or mechanical processes, for example by chemical mechanical polishing (CMP) and / or one or more etching processes. In some embodiments, the first semiconductor material is doped in-situ. In some other embodiments, the first semiconductor material is 112 lightly doped or intrinsic, for example, by forming the first intrinsic material without any intended doping processes.

With reference to the schematic sectional view 202 from 2C becomes a second pattern of second trenches 114 in the semiconductor body 105 educated. The second pattern includes a second center-to-center distance p2 along the first lateral direction x. In the schematic sectional view 202 the first and second center-to-center distances p1, p2 are equal, ie p1 = p2. In other embodiments, the first and second center-to-center distances may also differ. Similar to the first trenches 108 can the second trenches 114 also on the first surface 109 of the semiconductor body 105 be formed by a masked etching process, for example by dry etching. A mask pattern can be formed, for example, by photolithography. In some other embodiments, a common mask, such as a patterned hardmask layer, may be used to form the first and second trenches, respectively. In a first process step, a pattern of openings in the common mask may be covered in accordance with the second pattern to thereby suppress trenching of the second trenches when the first trenches are formed.

With reference to the schematic sectional view 203 from 2D are second regions according to the first pattern by filling the second trenches with second semiconductor material 116 , For example, an epitaxial silicon epitaxial layer formed by epitaxial processes, arranged. Excess material on the first surface 109 can be removed by chemical and / or mechanical processes, for example by chemical mechanical polishing (CMP) and / or one or more etching processes. In some embodiments, the second semiconductor material is 116 doped in situ. In some other embodiments, the second semiconductor material is 116 lightly doped or intrinsic, for example, by forming the intrinsic material without any intended doping processes. Excess material of the first and second semiconductor material 112 . 116 can also be removed by one or more common chemical and / or mechanical processes.

The sectional view 203 from 2E illustrates embodiments for forming patterns of the first and second regions by introducing dopants through a surface, for example, sidewalls and / or a bottom side of each of the first and second trenches 108 . 114 , In some embodiments, the above in 2E are illustrated, the dopants may be introduced by a diffusion process from a diffusion source which is the surface of each of the first and second trenches 108 . 114 lining (see arrow 250 ). As an alternative or in addition, the dopants may be incorporated into the semiconductor body 105 through a surface of each of the first and second trenches 108 . 114 by an oblique ion implantation process and / or by plasma doping. A doped semiconductor region 117 which has a surface of each of the first and second trenches 108 . 114 then forms respectively the first and second areas or a part thereof. The first and second trenches 108 . 114 are filled with a filling structure comprising intrinsic and / or lightly or weakly doped or intrinsic semiconductor material. If the first and second trenches 108 . 114 can be fully or partially filled with lightly doped semiconductor material, a doping concentration of the lightly doped semiconductor material can be suitably chosen, for example, not to affect a charge compensation, which is set by the first and second charge compensation regions.

In some embodiments, in 2E As shown below, the dopants may be removed from the semiconductor body by a diffusion process 105 in the lightly doped or intrinsic first and second semiconductor material 112 . 116 are introduced, respectively in the first and second trenches 108 . 114 is filled (see arrow 251 ). When the semiconductor body 105 doped with p- and n-type dopants at the same or nearly equal doses, the dopant species, which have a larger diffusion coefficient, each with a larger amount in the first and second trenches 108 . 114 introduced, resulting in different conductivity types in the first and second trenches 108 . 114 on the one hand and outside the first and second trenches 108 . 114 in the semiconductor body 105 on the other hand leads.

In the schematic sectional view 205 , in the 2F is illustrated, the first and second trenches comprise 108 . 114 a filling structure 120 doped semiconductor material forming each of the first and second regions, and in some embodiments additionally another material, such as one or more dielectrics and / or one or more intrinsic or lightly doped semiconductor materials. For example, the filling structure 120 a doped semiconductor region 121 comprising a surface of each of the first and second trenches 108 . 114 wherein the doped semiconductor region 121 respectively forms the first and second charge compensation regions. In another example, the fill structure may be formed entirely by doped semiconductor material.

Other processes may follow to make a superjunction semiconductor device. These processes may include processes for fabricating semiconductor regions, such as source, drain, body, collector, emitter, field stop region, auxiliary semiconductor regions for adjusting electrical characteristics, processes for fabricating dielectric layers, such as one or more gate dielectrics, one or more field dielectrics or a plurality of interlayer dielectrics, processes for forming conductive layers, such as one or more contact plugs or one or more contact lines, one or more gate electrodes, one or more field electrodes, one or more load contacts, such as one or more source contacts, one or more drain contacts, one or more a plurality of gate contacts, one or more emitter contacts, one or more collector contacts as an example.

In the schematic sectional view 206 from 2G is processing of the superjunction semiconductor device as shown in FIG 1 to 2F to further develop a vertical superjunction transistor device, including process features for making a p-doped body region 125 , an n ⁺ doped source region 126 , a planar gate with a gate dielectric 127 and a gate electrode 128 , a first load terminal contact L1 on the first surface 109 of the semiconductor body 105 , a control terminal contact C electrically connected to the gate electrode 128 is connected, a doped semiconductor region 129 on the second surface 110 and electrically connected to a second load terminal contact L2 on the second surface 110 , wherein the doped semiconductor region 129 an n ⁺ doped drain region is when the superjunction transistor is an insulated gate field effect transistor (IGFET) such as a metal oxide semiconductor field effect transistor (MOSFET) or a p ⁺ doped backside emitter when the superjunction transistor is an insulated gate bipolar transistor (IGBT).

In the schematic sectional view 207 from 2H is processing of the superjunction semiconductor device as shown in FIG 1 to 2F described further to produce a vertical superjunction transistor device comprising a trench gate including the gate electrode 128 and the gate dielectric 127 in a gate trench 130 and other structural elements, as described in the 2G illustrated embodiment includes.

In the schematic sectional view 208 from 2I is processing of the superjunction semiconductor device as shown in FIG 1 to 2F to produce a vertical superjunction transistor device comprising a split planar gate including the gate electrode portions 1280 . 1281 and the gate dielectric parts 1270 . 1271 and other structural elements, as described in the 2G illustrated embodiment includes.

In the in the 2G to 2I illustrated embodiments, the drift zone in the semiconductor body 105 , respectively the first and second trenches 108 . 114 surrounding, formed. In some other embodiments, the drift zone may be formed in a region including the first and second trenches 108 . 114 and the charge compensation region may include the first and second trenches 108 . 114 surrounding semiconductor body are formed. In this case, a bottom side of the first and second trenches 108 . 114 each adjacent to a semiconductor region of a conductivity type of the drift zone.

In the schematic plan view 301 , in the 3A 3, each of the first and second patterns is an array of stripe-shaped trenches, ie, the first and second trenches 108 . 114 are successively arranged along the first lateral direction x, and each of the first and second trenches 108 . 114 extends along a second lateral direction y, which is different from the first lateral direction x.

In the in 3B shown schematic plan view 302 For example, each of the first and second patterns is a two-dimensional array. Each of the first and second trenches 108 . 114 can be square, circular, polygonal. Examples of quadratic, circular and polygonal trench geometries are in 3B illustrated. However, numerous other trench geometries are suitable for making the superjunction transistor.

The above based on 1 to 3B In the production processes described, manufacturing problems caused by mechanical instability of mesa regions counteract the formation of a charge compensation structure in trenches. Such manufacturing problems can occur when manufacturing trench superjunction transistors having small center-to-center distances, for example center-to-center distances less than 7 μm or less than 4 μm or even less than 2 μm, and / or deep trenches or Mesas, for example Trenchtiefen greater than 20 microns or greater than 40 microns or greater than 60 microns have. By successively processing staggered patterns of regions, the mechanical stability of the mesa regions can be increased during front-end-of-line (FEOL) processing.

In some embodiments, a superjunction semiconductor device includes a superjunction structure with an adjoining zone 150 a first conductivity type in a semiconductor body and a plurality of strip-shaped areas 151 of a second conductivity type spaced apart and located in a two-dimensional array with respect to a surface or plane below the surface of the semiconductor body, at least some of the plurality of stripe-shaped regions having a curved or domed or kinked portion. In the in 4A In the illustrated embodiment, the curved part is a rectangle having a first width w1 larger than a second width w2 around a center of the striped areas 151 ,

In some embodiments, each of the plurality of stripe-shaped regions extends along a longitudinal direction x1, and a center-to-center distance p3 of the two-dimensional array along a transverse direction x2 of the plurality of stripe-shaped regions is in a range of 1 μm and 15 μm.

In some embodiments, a vertical distance is between a bottom side of each of the strip-shaped areas 151 and a surface of the semiconductor body larger than 20 μm. Examples of a sectional view along a line AA 'of 4A are in 2G to 2H illustrated.

In the in 4A shown embodiment of a superjunction transistor is the warped or curved part 152 in end portions of the strip-shaped parts 151 located opposite each other along the longitudinal direction x1.

The warped or curved parts 152 intended to compensate for a charge imbalance by breaking the strip-shaped areas 151 along the longitudinal direction x1 is caused. A charge imbalance due to an absence of p-type doping in an interruption region 153 and the additional n-type doping in the region 153 For example, by additional p-doping in projecting parts 154 the warped parts 152 be compensated. The interruption areas 153 allow improved mechanical stability of a fabrication process of trench superjunction transistors having small center-to-center spacings.

In some embodiments, the strip-shaped regions are arranged successively along the longitudinal direction x1 151 spaced apart from each other in a range of 0.3 microns and 3 microns.

A shape of the warped or curved or curved parts 152 may also differ from the specific shape, based on 43 is illustrated. Further examples of circular and polygonal shapes of the warped or curved parts 152 are each in the schematic plan views 402 . 403 , in the 48 and 4C are shown illustrated.

In some embodiments, an extension of each of the plurality of stripe-shaped regions along the longitudinal direction is in a range of 10 μm to 500 μm.

In some embodiments, which in the schematic plan views of 5A . 5B . 5C are shown, the warped or curved or curved part 152 along the longitudinal direction x1 in a center of the striped areas 151 located. In some embodiments, corners of the strip-shaped regions 151 for example beveled or rounded. In the in 5A . 5B . 5C The exemplary embodiments shown are the strip-shaped regions arranged successively along the transverse direction 151 offset with respect to their position along the longitudinal direction x1. In some embodiments, a warped or curved part is 152 from one of the strip-shaped areas 151 along a first line 405 are arranged along the transverse direction opposite to an interruption area 153 between two other areas of the strip-shaped areas 151 along a second line 406 parallel to the first line 405 are arranged.

Although specific embodiments are illustrated and described herein, it will be understood by those skilled in the art that a variety of alternatives and / or equivalent configurations may be utilized for the embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or modifications of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims (24)

A method of manufacturing a superjunction semiconductor device, comprising: Forming a first pattern of first trenches ( 108 ) in a semiconductor body ( 105 ), the first pattern having a first center-to-center distance (p1) along a first lateral direction (x), forming first regions arranged according to the first pattern, and then forming a second pattern of second trenches (p1) 114 ) in the semiconductor body ( 105 ), wherein the second pattern has a second center-to-center distance (p2) along the first lateral direction (x), and wherein an offset between the first and second patterns along the first lateral direction (x) is less than each of the first and second center-to-center distances, and forming second regions arranged according to the second pattern. Method according to claim 1, wherein the first and second trenches ( 108 . 114 ) are the same in terms of dimensions. A method according to any one of the preceding claims, wherein the first and second center-to-center distances (p1, p2) are equal. A method according to any one of the preceding claims, wherein each of the first and second patterns is a two-dimensional array. A method according to any one of claims 1 to 3, wherein each of the first and second patterns is an array of stripe-shaped trenches arranged successively along the first lateral direction (x) and in which each of the stripe-shaped trenches extends along a second lateral direction (y) which is different from the first lateral direction (x). The method of any one of the preceding claims, wherein forming each of the first and second regions comprises forming semiconductor material ( 112 . 116 ) in the corresponding trench of the first and second trenches ( 108 . 114 ). Method according to Claim 6, in which the semiconductor material ( 112 . 116 ) is formed by an epitaxial growth process. The method of claim 7, wherein the semiconductor body is of a first conductivity type and wherein the material is doped in-situ with dopants of a second conductivity type different from the first conductivity type. The method of claim 7, wherein the semiconductor body comprises first dopants of a first conductivity type and second dopants of a second conductivity type different from the first conductivity type, and wherein the method further comprises doping the semiconductor material by a thermal diffusion process comprising more of introducing the first dopants into the semiconductor material as from the second dopants. The method of claim 1, wherein forming each of the first and second regions comprises introducing dopants into the semiconductor body through sidewalls of the corresponding trench of the first and second trenches. 108 . 114 ). Method according to Claim 10, in which an introduction of the dopants into the semiconductor body ( 105 ) comprises a plasma doping. Method according to Claim 10 or 11, in which an introduction of the dopants into the semiconductor body ( 105 ) comprises an ion implantation. The method of any one of claims 8 to 12, further comprising filling each of said first and second trenches ( 108 . 114 ) with at least one material of a semiconductor material and a dielectric material. The method of any one of the preceding claims, further comprising forming body, source, drain and gate. A superjunction semiconductor device comprising: a superjunction structure having a contiguous zone ( 150 ) of a first conductivity type in a semiconductor body ( 105 ) and a plurality of strip-shaped areas ( 151 ) of a second conductivity type which are spaced apart and arranged in a two-dimensional array with respect to a surface of the semiconductor body ( 105 ), wherein at least some of the plurality of strip-shaped areas ( 151 ) a kinked part ( 152 ) exhibit. A superjunction semiconductor device according to claim 15, wherein each of said plurality of stripe-shaped regions (FIG. 151 ) extends along a longitudinal direction (x1) and a center-to-center distance (p3) of the two-dimensional array along a transverse direction (x2) of the plurality of stripe-shaped regions (x1) 151 ) in a range of 1 μm and 15 μm. A superjunction semiconductor device according to any one of claims 15 and 16, wherein a vertical distance between a bottom side of each of the strip-shaped regions (Fig. 151 ) and a surface of the semiconductor body ( 105 ) is greater than 20 microns. Superjunction device according to one of Claims 15 to 17, in which the kinked part ( 152 ) in end portions of the strip-shaped regions ( 151 ) located opposite each other along the longitudinal direction (x1). Superjunction device according to one of Claims 15 to 18, in which the strip-shaped regions ( 151 ) are arranged successively along the longitudinal direction (x1) apart from each other in a range of 0.3 μm and 3 μm. A superjunction device according to any one of claims 15 to 18, wherein an extension of each of said plurality of strip-shaped regions (Fig. 151 ) along the longitudinal direction in a range of 10 μm to 500 μm. Superjunction device according to one of Claims 15 to 19, in which the strip-shaped regions ( 151 ) arranged successively along the transverse direction, offset with respect to their position along the longitudinal direction (x1). A superjunction device according to claim 21, wherein a kinked part of one of the strip-shaped regions ( 151 ) arranged along a first line, along the transverse direction opposite to an interruption area between two other areas of the strip-shaped areas (FIG. 151 ) arranged along a second line which is parallel to the first line. Superjunction device according to one of Claims 15 to 22, in which the contiguous zone ( 150 ) is a drift zone. Superjunction device according to one of Claims 15 to 22, in which the contiguous zone ( 150 ) is a charge compensation region.

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