US5930179A - Program circuit - Google Patents

Program circuit Download PDF

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Publication number
US5930179A
US5930179A US08/882,835 US88283597A US5930179A US 5930179 A US5930179 A US 5930179A US 88283597 A US88283597 A US 88283597A US 5930179 A US5930179 A US 5930179A
Authority
US
United States
Prior art keywords
data
program
output data
output
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
US08/882,835
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English (en)
Inventor
Byoung Kwon Cha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Assigned to HYUNDAI ELECTRONCIS INDUSTRIES CO., LTD. reassignment HYUNDAI ELECTRONCIS INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHA, BYOUNG KWON
Application granted granted Critical
Publication of US5930179A publication Critical patent/US5930179A/en
Priority to US09/915,906 priority Critical patent/USRE40076E1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches

Definitions

  • the present invention relates to a program circuit and, more particularly, to a program circuit which can prevent a lowering of reliability occurring during the process of verifying the programmed data.
  • a flash memory device has functions of electrical program and erasure.
  • the flash memory device also performs a verification operation so as to confirm whether the memory cell has been programmed or erased or not after completion of the programming or the erasure operation. At this time, if there are memory cells in which a programming or erasure operation has not completed, re-programming or re-erasure operation is performed again.
  • a program circuit comprises a comparator for comparing output data of a data input buffer with output data of a sense amplifier bit by bit and for outputting a re-program operation signal if the data are different each other, a data latch circuit for latching the comparing results of the output data of the data input buffer and the output data of the sense amplifier, and a control circuit for generating a high voltage for receiving the output data of the data input buffer and the data latched at the data latch circuit, respectively and for outputting a signal for applying a program bias voltage to a memory cell which has not been programmed in response to a power-up reset signal and program state signal.
  • the comparator includes a plurality of exclusive gates to which output data of the data input buffer and output data of the sense amplifier, respectively, and a NOR gate for logically combining the output signals of the exclusive NOR gates.
  • the data latch circuit has a plurality of flip-flops, each flip-flop has a data input terminal to which comparing results of the output data of the data input buffer and the output data of the sense amplifier, a clock signal input terminal to which a program state signal, and a reset signal input signal to which power-up reset signal/program state signal/read mode signals are inputted.
  • the control circuit for generating a high voltage includes a plurality of NOR gates to which output data of the data latch circuit and a power-up reset signal are inputted, respectively, a plurality of inverters to which output data of the data input buffer is inputted; and a plurality of NAND gates to which the output signals of the NOR gates, the output signals of the inverters and the program state signal are inputted, respectively.
  • FIGURE is a circuit diagram for explaining a program circuit according to the present invention.
  • the accompanying drawing is a circuit diagram for explaining a program circuit according to the present invention.
  • the program circuit according to the present invention is consisted of a comparator 1, a data latch circuit 2, and a control circuit for generating a high voltage 3, and added to the flash memory device.
  • the comparator 1 comprises of a plurality of exclusive NOR gates EG1 through EG8 to which output data LDIN0 through LDIN7 of a data input buffer and output data SA0 through SA7 of a sense amplifier are inputted, respectively. Also, the comparator 1 comprises a NOR gate NG to which output signals of the exclusive NOR gates EG1 through EG8 are inputted. The NOR gate NG outputs logical combination signals via an output terminal DATA COMP.
  • the data latch circuit 2 is consisted of a plurality of flip-flops F1 through F8.
  • Each of flip-flops F1 through F8 comprises a data input terminal D to which an output signal of one of the exclusive NOR gates EG1 through EG8, a clock signal input terminal CL to which a program state signal PGM4 is inputted, and a reset signal input terminal R to which a power-up reset signal/program state signal/read mode signals PURST/PGM3/READ are inputted.
  • the control circuit for generating a high voltage 3 comprises a plurality of NOR gates N1 through N8 to which output data Q0 through Q7 of the flip-flops F1 through F8 and the power-up reset signal PURST are inputted, respectively, a plurality of inverters I1 through I8 to which the output data LDIN0 through LDIN7 of data input buffer are inputted, respectively, and a plurality of NAND gates NG1 through NG8 to which output signals of the NOR gates N1 through N8, output signals of the inverters I1 through I8 and the program state signal PGM1, respectively.
  • the plurality of NAND gates NG1 through NG2 output signals VCVPB0 through VCVPB7, respectively.
  • the data "10011000” is inputted to the exclusive NOR gates EG1 through EG8 via one input terminal, respectively, and the data read from the memory cell, that is, the data SA0 through SA7 outputted from the sense amplifier are inputted to the exclusive NOR gates EG1 through EG8 via other input terminal, respectively.
  • the data "101111011” outputted via the output terminals of the exclusive NOR gates EG1 through EG8 is latched to the flip-flops F1 through F8 respectively depending on the input of the program state signal PGM4, and the output signals Q0 through Q7 of the flip-flops F1 through F8 are inputted to the NOR gates N1 through N8, respectively.
  • the flip-flops F1 through F8 are maintained at the state in which the data of "0" is latched by the input of the power-up reset signal PURST.
  • the data "10011000” outputted from the flip-flops F1 through F8 are inputted to the NOR gates N1 through N8 of the control circuit for generating high voltage 3 respectively, and the output data "1001100” of the data input buffer is inputted to the inverters I1 and I8, respectively.
  • signals at a low level are outputted from only the output terminals VCVPB1 and VCVPB5 of the NAND gates NG2 and NG6 by the power-up reset signal PURST inputted with a low level and the program state signal PGM1 inputted with a high level. Therefore, a programming bias voltage is again applied to only the memory cells which are corresponded to the second and the sixth bits, respectively.
  • the program circuit according to the present invention can apply a program voltage to only the memory cells which are not programmed during a re-programming operation. Therefore, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a program bias voltage.
US08/882,835 1996-06-29 1997-06-26 Program circuit Ceased US5930179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/915,906 USRE40076E1 (en) 1996-06-29 2001-07-25 Program circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019960025547A KR100193898B1 (ko) 1996-06-29 1996-06-29 플래쉬 메모리 장치
KR96-25547 1996-06-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/915,906 Reissue USRE40076E1 (en) 1996-06-29 2001-07-25 Program circuit

Publications (1)

Publication Number Publication Date
US5930179A true US5930179A (en) 1999-07-27

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Family Applications (2)

Application Number Title Priority Date Filing Date
US08/882,835 Ceased US5930179A (en) 1996-06-29 1997-06-26 Program circuit
US09/915,906 Expired - Lifetime USRE40076E1 (en) 1996-06-29 2001-07-25 Program circuit

Family Applications After (1)

Application Number Title Priority Date Filing Date
US09/915,906 Expired - Lifetime USRE40076E1 (en) 1996-06-29 2001-07-25 Program circuit

Country Status (4)

Country Link
US (2) US5930179A (ko)
KR (1) KR100193898B1 (ko)
GB (1) GB2314953B (ko)
TW (1) TW367502B (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1437743A2 (en) * 2002-11-22 2004-07-14 Texas Instruments Inc. Adaptive algorithm for electrical fuse programming
FR2894710A1 (fr) * 2005-12-14 2007-06-15 St Microelectronics Sa Procede et dispositif de verification de l'execution d'une commande d'ecriture dans une memoire
US8248848B1 (en) * 2007-10-01 2012-08-21 Marvell International Ltd. System and methods for multi-level nonvolatile memory read, program and erase

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100322018B1 (ko) * 1999-01-23 2002-02-04 윤종용 음성대역 잡음 보상장치
KR102651590B1 (ko) 2022-04-05 2024-03-25 한국타이어앤테크놀로지 주식회사 에어 포켓을 구비한 타이어

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811294A (en) * 1985-06-21 1989-03-07 Mitsubishi Denki Kabushiki Kaisha Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM)
US5299162A (en) * 1992-02-21 1994-03-29 Samsung Electronics Co., Ltd. Nonvolatile semiconductor memory device and an optimizing programming method thereof
US5629890A (en) * 1994-09-14 1997-05-13 Information Storage Devices, Inc. Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5163021A (en) * 1989-04-13 1992-11-10 Sundisk Corporation Multi-state EEprom read and write circuits and techniques
JP3448051B2 (ja) * 1990-03-31 2003-09-16 株式会社東芝 不揮発性半導体記憶装置
JPH0757484A (ja) * 1993-08-11 1995-03-03 Sony Corp Ｎｏｒ型不揮発性メモリ制御回路
KR0169267B1 (ko) * 1993-09-21 1999-02-01 사토 후미오 불휘발성 반도체 기억장치
JP3176008B2 (ja) * 1994-03-30 2001-06-11 株式会社東芝 半導体メモリ回路
JPH08190796A (ja) * 1995-01-09 1996-07-23 Mitsubishi Denki Semiconductor Software Kk データリフレッシュ機能を有するフラッシュメモリ及びフラッシュメモリのデータリフレッシュ方法
KR100208433B1 (ko) * 1995-12-27 1999-07-15 김영환 플래쉬 메모리 소자 및 그를 이용한 프로그램 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811294A (en) * 1985-06-21 1989-03-07 Mitsubishi Denki Kabushiki Kaisha Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM)
US5299162A (en) * 1992-02-21 1994-03-29 Samsung Electronics Co., Ltd. Nonvolatile semiconductor memory device and an optimizing programming method thereof
US5629890A (en) * 1994-09-14 1997-05-13 Information Storage Devices, Inc. Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1437743A2 (en) * 2002-11-22 2004-07-14 Texas Instruments Inc. Adaptive algorithm for electrical fuse programming
EP1437743A3 (en) * 2002-11-22 2009-03-11 Texas Instruments Inc. Adaptive algorithm for electrical fuse programming
FR2894710A1 (fr) * 2005-12-14 2007-06-15 St Microelectronics Sa Procede et dispositif de verification de l'execution d'une commande d'ecriture dans une memoire
EP1798733A1 (fr) * 2005-12-14 2007-06-20 Stmicroelectronics Sa Procédé et dispositif de vérification de l'éxécution d'une commande d'écriture dans une mémoire
US20070153581A1 (en) * 2005-12-14 2007-07-05 Stmicroelectronics Sa Method and device for checking the execution of a write command for writing in a memory
US7447080B2 (en) 2005-12-14 2008-11-04 Stmicroelectronics Sa Method and device for checking the execution of a write command for writing in a memory
US8248848B1 (en) * 2007-10-01 2012-08-21 Marvell International Ltd. System and methods for multi-level nonvolatile memory read, program and erase
US8792274B1 (en) 2007-10-01 2014-07-29 Marvell International Ltd. Multi-level memory cell read, program, and erase techniques

Also Published As

Publication number Publication date
TW367502B (en) 1999-08-21
GB9712951D0 (en) 1997-08-20
USRE40076E1 (en) 2008-02-19
KR100193898B1 (ko) 1999-06-15
GB2314953B (en) 2000-07-05
KR980005026A (ko) 1998-03-30
GB2314953A (en) 1998-01-14

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