US5881063A - Half-message based multiplex communication interface circuit which uses a main microcontroller to detect a match in addresses and generate a qualified signal - Google Patents

Half-message based multiplex communication interface circuit which uses a main microcontroller to detect a match in addresses and generate a qualified signal Download PDF

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US5881063A
US5881063A US08/629,252 US62925296A US5881063A US 5881063 A US5881063 A US 5881063A US 62925296 A US62925296 A US 62925296A US 5881063 A US5881063 A US 5881063A
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receiving
microcontroller
bytes
responsive
signal
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US08/629,252
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English (en)
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Bradley Earl BeMent
Robert Dennis Crawford
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Visteon Global Technologies Inc
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Ford Motor Co
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Assigned to FORD MOTOR COMPANY reassignment FORD MOTOR COMPANY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BEMENT, BRADLEY EARL, CRAWFORD, ROBERT DENNIS
Priority to DE69727921T priority patent/DE69727921T2/de
Priority to KR1019980707968A priority patent/KR20000005265A/ko
Priority to EP97915577A priority patent/EP0893019B1/en
Priority to ES97915577T priority patent/ES2213212T3/es
Priority to JP09535952A priority patent/JP2000513516A/ja
Priority to PCT/GB1997/000927 priority patent/WO1997038512A1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/20—Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Definitions

  • This invention relates to a multiplex transmission system of the type used in automotive applications for transmitting serial data message formats among a plurality of multiplex nodes connected to a common multiplex transmission line, and more particularly to a pulse width modulation multiplex transmission system operated in accordance with Society of Automotive Engineers standard J1850.
  • Messages transmitted from an originating node in a multiplex communication system normally include priority/type bytes describing the group or function of the nodes that should receive the message, in addition to target bytes that may define the specific address or addresses nodes to receive the message.
  • the transmitting node must receive confirmation or acknowledgment that the addressed node has received the message.
  • a typical received node includes interface circuitry that includes programmable memory for storing the address of the node as well as the priority and/or type functions for which the node is responsible. These stored type and target bytes must then be compared by the interface circuitry with the type and target bytes of all incoming messages in order to determine if the message should be received and processed. Since programmable memory within the interface circuit represents an added cost that increases complexity without increasing functionality, it is desirable to provide a node interface circuit that offloads this function to the host microprocessor at the node that already includes programmable memory and comparators capable of performing this function.
  • the present invention includes a method and circuit for receiving frame messages connected to one or more nodes, each controlled by a microcontroller, along a common transmission line of a multiplex communication system.
  • the method includes the steps of: (a) receiving the type and target bytes, and responsive thereto generating a first interrupt signal to the microcontroller at the node; (b) commanding the microcontroller, responsive to receiving the first interrupt signal, for qualifying the frame message by retrieving and matching one or more of the type and target bytes with corresponding bytes stored in memory within the microcontroller, and responsive thereto generating a qualified signal; and (c) receiving data bytes from the frame message only responsive to receiving the qualified signal from the microcontroller.
  • FIG. 1 is a schematic block diagram of a node interface circuit in accordance with the present invention.
  • FIG. 2 is a schematic block diagram of the node interface circuit and the host microcontroller that cooperate at the node of the multiplex communication system.
  • FIG. 3 illustrates the frame message bytes and the interrupt and chip select signals processed within the interface circuit for the case where the message is not directed for the node processing the signal.
  • FIG. 4 illustrates the frame message bytes and the interrupt and chip select signals processed within the interface circuit for the case where the host microcontroller has received and examined the priority/type and target bytes and has determined that the frame message should be processed at the node, and has generated an acknowledgment to the originating node.
  • FIG. 5 illustrates the frame message bytes and the interrupt and chip select signals processed within the interface circuit for the case where the host microcontroller has commanded a message transmission, and has received and examined the transmitted priority/type and target bytes to determine whether receipt and acknowledgment of the message will be required if arbitration is lost.
  • FIG. 6 illustrates a block diagram of the steps in accordance with the method of the present invention.
  • FIG. 2 A circuit diagram for a typical node in a multiplex communication system is illustrated generally in FIG. 2. and includes a host microprocessor 10, typically a Motorola 68HC11 or a Texas Instrument TMS370, which is coupled through a standard 5 line SPI interface 12 to the interface integrated circuit, hereinafter referenced as the network interface circuit 20 in accordance with the present invention.
  • the network interface circuit 20 is Ford part number N7100070FTCFCA that includes host interface digital circuitry, transceiver digital logic circuitry and analog receive comparators, together with miscellaneous oscillators and buffer circuitry.
  • a 4 megahertz resonator 22 is coupled to the network interface integrated circuit 20 in order to provide a stable frequency standard.
  • the network interface circuit 20 includes a pair of receive input signal lines 24, and a pair of transmit signal output lines 26 that are connected to transmit driver circuitry 30.
  • the transmit driver circuitry 30 generates the appropriate voltage levels required to interface with the main communications network bus 40, which in the preferred embodiment of the present invention operates in accordance with, an automobile industrial standard for data communications network interfaces, SAE Recommended Practice J1850 class B Data Communications Network Interface, dated May 5, 1993.
  • SAE Recommended Practice J1850 class B Data Communications Network Interface dated May 5, 1993.
  • the signal format used in the present invention and in SAE standard J1850 is explained more fully in U.S. Pat. Nos. 4,715,0311 and 5,418,526.
  • Receiver filter elements 28, comprising series resistors and parallel capacitors, provide input protection and noise filtering functions on the receive input PWM signals from the network bus 40.
  • a schematic block diagram for the network interface circuit 20 is illustrated as including receive input signal lines 24 and transmit signal output lines 26 as previously described.
  • the input lines 24 are coupled to a receiver analog comparator 102 that includes two single ended comparators for comparing each of the input lines to a voltage threshold and also includes a differential comparator for comparing the difference in the potential between the two input signal lines 24.
  • Three digital output lines 104 from receive analog comparator 102 are coupled to an input of fault tolerant switchover logic and bit decoders 106. These logic circuits select between the input lines in order to minimize bit error rates and the effect of network faults.
  • a single output 108 from the bit decoders 106 is coupled to the input of a serial to parallel converter 110.
  • the serial bit rate at the input 108 is approximately 41.7 kilobits per second, while the output of the serial to parallel converter 110 includes 8 parallel bits clocked at one-eighth of the input frequency.
  • the output signal of the serial to parallel converter 110 is coupled to an internal signal data bus 112 that feeds other elements of the network interface circuit 20.
  • the internal signal data bus 112 is coupled to message qualification registers 120, which store the first 2 bytes of the incoming message frame from the communication network bus 40.
  • the outputs of the message qualification registers 122 are coupled to a host interface bus 130, which in turn is coupled to the host microcontroller 10 (not illustrated in FIG. 1) through host interface control logic 140 and standard SPI interface 12.
  • Transceiver control logic 250 is responsible for controlling the reception and transmission of message frames on the network. During data reception, it controls the movement of data from the output of the serial to parallel converter 110, to the message qualification registers 120, to a receive FIFO 150, and to a TX ACK FIFO 260. During message transmission, it controls the movement of data to a parallel to serial converter 190 from a TX buffer 230 and a node address register 160.
  • the transceiver control logic 250 instructs the host interface control logic 140 to generate an interrupt request to the host microcontroller 10.
  • the host interface control logic 140 accomplishes this by pulling the interrupt request host interface line (INT) 300 from high to low. This interrupt request is referred to as the qualification interrupt request or first interrupt signal.
  • the host microcontroller 10 responds to this interrupt request by asserting the chip select (CS) signal 400 and commanding the host interface control logic 140 to fetch the contents of the message qualification registers 120 using a predetermined sequence of byte transfers across the SPI interface 12.
  • CS chip select
  • the host microcontroller 10 compares the contents of the message qualification registers 120 with pre-determined lists of values for the type and target bytes stored in internal programmable memory, and determines whether the network interface circuit should continue the reception and acknowledgment of message frame.
  • the host microcontroller 10 transmits the desired response to the network interface circuit 20 through a predetermined command sequence across the host interface 12.
  • the internal signal data bus 112 is coupled to an input of a receiver FIFO 150 that includes 8 bytes of storage for the remainder of the incoming message data.
  • the receiver FIFO 150 is used to store data for message types that contain data intended for the host microcontroller 10.
  • the 8 bytes of data typically include a source/transmit ID byte, 0-7 data bytes, a CRC byte and an EOD (End of Data) bit as illustrated in FIG. 3.
  • the transceiver control logic 250 begins transmission of the message acknowledgment byte(s) and instructs the host interface control logic 140 to generate an interrupt request to the host microcontroller 10. This interrupt request is referred to as the receive complete interrupt request or the second interrupt signal.
  • the host microcontroller 10 responds to the receive complete interrupt request by asserting the chip select signal and commanding the host interface control logic 140 to provide it with the contents of the receive FIFO 150.
  • the host interface control logic 140 accomplishes this by moving data from the receive FIFO output 152 across interface bus 120 and across the SPI interface 12.
  • the type of message acknowledgment returned by the network interface circuit 20 depends upon the type of message frame that is received.
  • the transceiver control logic 250 determines the appropriate acknowledgment format by examining the type of the received message, which is stored in the message qualification registers 120. Most message types are acknowledged by transmitting the contents of the node address register 160. Other message types are acknowledged by transmitting the contents of the ACK data register 170 followed by a CRC byte from the CRC generator 180.
  • the ACK acknowledgment bytes are processed in a converter 190 from a parallel to a serial bit stream, which is then fed to a pulse width modulated (PWM) generator 200.
  • PWM pulse width modulated
  • the output of the PWM generator 200 is coupled to transmitter drive circuitry 210, which in turn is coupled to the transmit signal output line 26 as previously discussed.
  • the PWM generator 200 encodes the bits from the parallel to serial converter 190 in accordance with the pulse width modulation scheme of SAE standard J1850.
  • Watchdog circuitry 220 limits the length of the pulse width modulation signal and also limits the length of the data frame which can be transmitted, both in accordance with requirements of SAE standard J1850.
  • the host microcontroller 10 sends a transmit command followed by the data to be transmitted to the network interface circuit 20 through the SPI interface 12.
  • the host interface logic 140 decodes the transmit command, and then routes the data to be transmitted across the host interface bus 130 to transmit buffer 230.
  • the transmit buffer 230 comprises digital storage for up to nine bytes of data.
  • An output of the transmit buffer 230 is coupled to an internal transmit data bus 240, that is then coupled to the input of the parallel to serial converter 190, the function of which has been previously discussed.
  • the transceiver controller 250 monitors the outputs from the switchover logic and bit decoders 106, and determines when a valid transmission opportunity exists on the communications network bus 40 at the receiver input 24.
  • the transceiver controller 250 moves data from the transmit buffer 230, as well as the node address register 160, to the parallel to serial converter 190. This data is then converted to PWM format by the PWM generator 200 and transmitted by the transmit drivers 210 over the transmit output lines 26 to the main communications network bus 40.
  • the transceiver controller 250 commands a CRC checker/generator 180 to transfer the contents of the generated CRC byte over the internal transmit data bus 240 to the parallel to serial converter 190.
  • the CRC byte is then transmitted over the transmit output lines 26.
  • the transceiver controller 250 waits for the end of the data field, and then any acknowledgment bytes that appear on the network at the receiver inputs 24 are received and stored in a seven byte transmit acknowledgment FIFO 260.
  • the transceiver control logic 250 instructs the host interface control logic 140 to generate an interrupt request to the host microcontroller 10 in the manner previously described. This interrupt request is referred to as the transmit complete interrupt request or third interrupt signal.
  • the host microcontroller 10 responds to the interrupt request by asserting the chip select line 400 and commanding the host interface control logic 140 to fetch the transmission completion status, and optionally the contents of the transmit acknowledgment FIFO, using a predetermined sequence of byte transfers across the SPI interface 12.
  • An oscillator circuit 270 is coupled to the three terminal resonator 22 (illustrated in FIG. 2), and provides a stable clock signal for driving the internal logic of the system.
  • Various control and status registers 280 are provided for conducting housekeeping duties and detecting network faults.
  • FIGS. 3, 4 and 5 illustrate how the interrupt request signals 300 are generated in relationship to various types of messages on the main communications network bus 40.
  • the message frame 280 comprises an SAE standard J1850 message frame and includes a start of frame network element 282, a priority/type byte 284, a target byte 286, a source address byte 288 and a CRC byte 290.
  • the End of Data network element 292 follows the CRC byte 290, and in turn is followed by any required acknowledgment bytes 294 to be transmitted before the End Of Frame (EFO) byte (an in-frame acknowledgment) as illustrated at the top of page 3.
  • EFO End Of Frame
  • the interrupt signal 300 from the host interface logic 140 remains high until the end of the target byte 286, at which time it transitions to low 310.
  • This interrupt request is passed to the host microcontroller 10 from the host interface logic 140 as previously explained.
  • the chip select signal 400 and the system clock signal 500 are shown to illustrate the processing of the interrupt request by the host microcontroller 10.
  • the host microcontroller 10 asserts the chip select signal 400 at transition 420, processes the qualification interrupt request, and then deasserts the chip select signal 400 at transition 430 following the completion of the interrupt processing.
  • the host microcontroller 10 must complete the processing of the qualification interrupt request transmitted at the end of the target byte 286 before the completion of the EOD byte 292. In this manner, the host microcontroller 10 must determine within the specified time if the remainder of the message frame is to be received and if the message frame is to be acknowledged. In the example illustrated in FIG. 3, the host microcontroller 10 has determined, by comparing the priority/type and target bytes of the message frame as stored in the qualification registers 120, that the remainder of the message frame is not to be received and an acknowledgment signal will not be transmitted. The host microcontroller 10 also has commanded the network interface circuit 20 not to generate a receive complete interrupt request following the EOD byte and not to acknowledge the message.
  • the acknowledgment byte 294 shown in FIG. 3 is not transmitted by the network interface circuit in this example. It is used to illustrate that some other network node may acknowledge a message that is not acknowledged by this network interface circuit.
  • the network interface circuit 20 returns the interrupt signal 300 to high at transition 330 after the host microcontroller 10 has responded to the interrupt request.
  • the interrupt signal 300 remains high until the next interrupt request in the next message frame.
  • FIG. 4 illustrates the case where the host microcontroller 10 has received and examined the priority/type bytes 284 and target bytes 286, and thereby has determined that the frame message should be processed at the node.
  • the network interface device asserts the interrupt line to notify the microcontroller 10 that the type and target of the message are available.
  • the microcontroller 10 responds to the interrupt request by asserting the chip select signal line 400 at transition 415, and reading the type and target data bytes 284 and 286 from the message qualification registers 120.
  • the microcontroller 10 initiates an acknowledge command and deasserts chip select signal 400 at transition 420 to complete the message qualification processing.
  • the network interface device 20 Following the reception of the End of Data bit 292 in the message frame, the network interface device 20 begins transmission of the message acknowledgment byte 294 and reasserts interrupt line 300 at transition 325 to notify the microcontroller 10 that the remainder of the message frame is available in the receive FIFO 150.
  • the microcontroller 10 responds to this interrupt signal by asserting chip select 400 at transition 440, reads any required data from the receive FIFO 150, and then deasserts chip select at transition 450 to notify the network interface device 20 that the processing is complete.
  • FIG. 5 illustrates the process whereby a message transmission is initiated.
  • the microcontroller 10 must first transfer the data to be transmitted to the network interface device 20 by asserting chip select signal 400 at transition 460.
  • the transmit command is then followed by the data to be transmitted over the SPI lines 12 from the microcontroller 10 to the host interface logic 140.
  • the end of the transmit command is designated by the deassertion of the chip select signal 400 at transition 470.
  • the network interface device 20 then waits for 3 idle bit periods on the main communications network bus 40 or for a start of frame signal to be detected, at which time the microcontroller 10 begins the transmission of the data stored in the transmit buffer 230 in the manner previously discussed.
  • interrupt signal 300 is asserted at transition 310 following the reception of the priority/type and target bytes, 284 and 286 respectively.
  • the microcontroller 10 must then perform the message qualification function as previously described. All messages that are transmitted must also go through the message qualification procedure to protect against the possibility that arbitration will be lost on the network requiring the remainder of the message frame to be processed as a reception.
  • the network interface device 20 changes from being a transmitter to a receiver of the message frame, and must determine if the message frame is to be received or ignored.
  • another interrupt request is generated at transition 370 to notify the host microcontroller 10 that a transmission of the frame has been completed.
  • a flow chart for the process described above is illustrated with reference to FIG. 6.
  • the network interface device 20 receives the priority/type 284 and target 286 bytes and stores these signals in qualification registers 120.
  • the network interface circuit 20 generates an interrupt request to the microcontroller 10 in response to receipt of the priority/type and target bytes.
  • the microcontroller 10 examines the qualification registers 120 to determine if the message is directed toward the node by comparing the contents of the registers to data stored in tables within the microcontroller 10.
  • the network interface device 20 continues the reception and storage of the message frame, specifically the source and data bytes, in the receive FIFO 150.
  • step 650 the microcontroller 10 transmits the qualification command to the host interface circuit 20 indicating that the message is either qualified or not qualified. If the message is not qualified, processing of the message frame terminates and the process moves to step 700 which requires waiting for the next message frame. If the message is qualified, then the process moves to step 660 wherein the loading of the received message into the receive FIFO 150 continues until the EOD byte is received. At step 664, if the message data bytes are received through EOD without error, then the process moves to steps 668 and 690. Otherwise the process moves to step 700. At step 668, if the message is of a type that contains data to be received by the host, then the process moves to step 670. Otherwise, the process moves to step 682.
  • the network interface circuit 20 generates a receive complete interrupt request to the host microcontroller 10.
  • the microcontroller 10 responds to the receive complete interrupt request and retrieves the contents of the receive FIFO 150 and continues processing the received data.
  • any required host processing of any received data is complete.
  • the network interface device 20 transmits the acknowledgment byte(s) to the transmitting node at step 690 indicating that the message has been received and is being processed. Following step 690 the network interface device 20 waits for the next message at step 700.
  • the contents of the qualification registers 120 are transmitted to the host microcontroller 10 for comparison with previously stored values corresponding to message identifiers that are addressed for receipt and processing at a node.
  • the network interface device 20 does not need to program, store and compare the priority/type and target bytes in the process of determining if the message is intended for receipt and processing at the node.
US08/629,252 1996-04-08 1996-04-08 Half-message based multiplex communication interface circuit which uses a main microcontroller to detect a match in addresses and generate a qualified signal Expired - Fee Related US5881063A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US08/629,252 US5881063A (en) 1996-04-08 1996-04-08 Half-message based multiplex communication interface circuit which uses a main microcontroller to detect a match in addresses and generate a qualified signal
PCT/GB1997/000927 WO1997038512A1 (en) 1996-04-08 1997-04-02 Multiplex communication interface circuit and method
KR1019980707968A KR20000005265A (ko) 1996-04-08 1997-04-02 다중 통신 인터페이스 회로 및 그 방법
EP97915577A EP0893019B1 (en) 1996-04-08 1997-04-02 Multiplex communication interface circuit and method
ES97915577T ES2213212T3 (es) 1996-04-08 1997-04-02 Procedimiento y circuito interfaz para conexiones multiplex.
JP09535952A JP2000513516A (ja) 1996-04-08 1997-04-02 多重通信インターフェース回路及び方法
DE69727921T DE69727921T2 (de) 1996-04-08 1997-04-02 Verfahren und schnittsstellenschaltung für multiplex-kommunikation

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US08/629,252 US5881063A (en) 1996-04-08 1996-04-08 Half-message based multiplex communication interface circuit which uses a main microcontroller to detect a match in addresses and generate a qualified signal

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US (1) US5881063A (ko)
EP (1) EP0893019B1 (ko)
JP (1) JP2000513516A (ko)
KR (1) KR20000005265A (ko)
DE (1) DE69727921T2 (ko)
ES (1) ES2213212T3 (ko)
WO (1) WO1997038512A1 (ko)

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US20060227736A1 (en) * 2005-03-31 2006-10-12 Adc Telecommunications, Inc. Dynamic reallocation of bandwidth and modulation protocols
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US7574234B2 (en) 2005-03-31 2009-08-11 Adc Telecommunications, Inc. Dynamic readjustment of power
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US7640019B2 (en) 2005-03-31 2009-12-29 Adc Telecommunications, Inc. Dynamic reallocation of bandwidth and modulation protocols
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DE69727921T2 (de) 2005-02-10
EP0893019B1 (en) 2004-03-03
WO1997038512A1 (en) 1997-10-16
ES2213212T3 (es) 2004-08-16
DE69727921D1 (de) 2004-04-08
EP0893019A1 (en) 1999-01-27
KR20000005265A (ko) 2000-01-25
JP2000513516A (ja) 2000-10-10

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