US5851868A - Methods of forming integrated decoupling capacitors - Google Patents

Methods of forming integrated decoupling capacitors Download PDF

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US5851868A
US5851868A US08/699,945 US69994596A US5851868A US 5851868 A US5851868 A US 5851868A US 69994596 A US69994596 A US 69994596A US 5851868 A US5851868 A US 5851868A
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forming
capacitor electrode
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capacitor
conductivity type
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Sung-Bong Kim
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • the present invention relates to semiconductor devices and methods of fabrication, and more particularly to decoupling capacitors and methods of forming decoupling capacitors.
  • FIG. 1 illustrates a prior art on-chip decoupling capacitor having an insulated capacitor electrode 7 which is separated from a P-type well region 3 by a dielectric layer 5.
  • the well region 3 may be provided in an N-type or P-type semiconductor substrate 1.
  • the insulated capacitor electrode 7 is electrically connected to the power supply signal line (VCC) and the well region 3 and P-type contact region 10 are electrically connected to the on-chip ground line 11 (GND).
  • N-type charge source regions 9 are also provided to facilitate the formation of an inversion-layer of electrons at the face of the well region 3, opposite the insulated capacitor electrode 7.
  • an insulated first capacitor electrode is provided on a face of the substrate and is preferably electrically insulated therefrom by a first dielectric layer.
  • a first electrically insulating layer is provided on an upper surface of the first capacitor electrode and a second capacitor electrode is provided on the first electrically insulating layer, opposite the first capacitor electrode.
  • a third capacitor electrode is also patterned opposite the second capacitor electrode and is separated therefrom by a second dielectric layer of predetermined dielectric material.
  • the third capacitor electrode is electrically insulated from upper levels of metallization by a second electrically insulating layer.
  • a first capacitor contact (e.g., VCC) is also formed by patterning metallization in a first via which extends through the second electrically insulating layer, second dielectric layer and first electrically insulating layer to expose an upper surface of the first capacitor electrode.
  • a fourth via is also provided so that the first and third capacitor electrodes can be connected together via the first capacitor contact.
  • a second capacitor contact is also provided by patterning metallization in second and third vias.
  • the third via extends through the second electrically insulating layer and second dielectric layer to expose an upper surface of the second capacitor electrode and the third via extends through the second electrically insulating layer, the second dielectric layer and the first electrically insulating layer to expose inversion-layer charge source regions of second conductivity type in the substrate. These charge source regions provide second conductivity type charge carriers to the portions of the substrate extending opposite the first capacitor electrode.
  • the decoupling capacitor includes a first dielectric layer, an insulated first capacitor electrode thereon, a second dielectric layer on an upper surface of the first capacitor electrode and a second capacitor electrode on the second dielectric layer.
  • the second capacitor electrode is electrically insulated from upper levels of metallization by an electrically insulating layer.
  • a first capacitor contact is also provided by patterning metallization in a via which extends through the electrically insulating layer and exposes an upper surface of the first capacitor electrode.
  • a second capacitor contact is also provided by patterning metallization in a via which exposes an upper surface of the second capacitor electrode and in a via which exposes charge source regions.
  • the application of a predetermined potential bias to the first capacitor electrode causes (i) the formation of an inversion-layer channel of second conductivity type charge carriers (e.g., electrons) in the substrate and the formation of a density of second conductivity type charge carriers on the second capacitor electrode.
  • second conductivity type charge carriers e.g., electrons
  • a preferred method of forming the above described decoupling capacitors includes the steps of forming an insulated first capacitor electrode on a first portion of a face of a semiconductor substrate containing a region of first conductivity type therein extending to the first portion of the face.
  • a second capacitor electrode is then formed on the insulated first capacitor electrode, opposite the region of first conductivity type.
  • Inversion-layer charge source regions of second conductivity type are then formed in the region of first conductivity type, so that second conductivity type charges carriers can be supplied to the first portion of the face when the first capacitor electrode is appropriately biased.
  • a first capacitor contact is then formed to electrically contact the insulated first capacitor electrode and a second capacitor contact is also formed to electrically connect the second capacitor electrode to the inversion-layer charge source regions.
  • FIG. 1 illustrates a schematic cross-sectional view of a decoupling capacitor according to the prior art.
  • FIG. 2 illustrates a schematic cross-sectional view of an integrated decoupling capacitor according to a first embodiment of the present invention.
  • FIGS. 3-9 illustrate schematic cross-sectional views of intermediate structures illustrating a method of forming the integrated decoupling capacitor of FIG. 2 and a static random-access memory cell.
  • FIG. 10 illustrates a schematic cross-sectional view of an integrated decoupling capacitor according to a second embodiment of the present invention.
  • FIG. 11 illustrates a schematic cross-sectional view of an integrated decoupling capacitor according to a third embodiment of the present invention.
  • FIGS. 12-16 illustrate schematic cross-sectional views of intermediate structures illustrating a method of forming the integrated decoupling capacitor of FIG. 11 and a static random-access memory cell.
  • first conductivity type and “second conductivity type” refer to opposite conductivity types such as P or N-type and each embodiment described and illustrated herein includes its complementary embodiment as well.
  • an integrated decoupling capacitor comprises a semiconductor substrate 21 of first or second conductivity type and a diffused well region 23 of first conductivity type (e.g., P-type) therein extending to a first portion of a face of the semiconductor substrate 21, defined by an opening in a field oxide isolation region.
  • An insulated first capacitor electrode 27 is provided on the first portion of the face.
  • the first capacitor electrode 27 is preferably electrically insulated from the face by a first dielectric layer 25 of predetermined dielectric material.
  • Exposed edges or ends of the first capacitor electrode 27 are also electrically insulated by sidewall spacers, as illustrated, and a first electrically insulating layer 31 is provided on an upper surface of the first capacitor electrode 27.
  • a predetermined potential bias to the first capacitor electrode 27 will cause the formation of an inversion-layer channel of second conductivity type charge carriers (e.g., electrons) in the region 23 of first conductivity type at the face, opposite the first capacitor electrode 27.
  • second conductivity type charge carriers are provided to the region 23 of first conductivity type by inversion-layer charge source regions 29 of second conductivity type.
  • These inversion-layer charge source regions 29 are preferably self-aligned to the first capacitor electrode 27 by implanting and diffusing second conductivity type dopants into the face, using the first capacitor electrode 27 and sidewall spacers as an implant mask, as explained more fully hereinbelow.
  • a second capacitor electrode 35 is also provided on the first electrically insulating layer 31.
  • the second capacitor electrode 35 is patterned opposite the first capacitor electrode 27 and is electrically connected thereto through a first via or contact hole 33 therein.
  • a third capacitor electrode 39 is also patterned opposite the second capacitor electrode 35 and is separated therefrom by a second dielectric layer 37 of predetermined dielectric material (e.g., SiO 2 , Si 3 N 4 ).
  • the third capacitor electrode 39 is electrically insulated from upper levels of metallization by a second electrically insulating layer 41.
  • a first capacitor contact 47 (e.g., VCC) is also provided by patterning metallization in a second via which extends through the second electrically insulating layer 41 and exposes an upper surface of the second capacitor electrode 35.
  • a second capacitor contact 45 (e.g., GND) is also provided by patterning metallization in third and fourth vias 43 and 44, respectively.
  • the third via 43 extends through the second electrically insulating layer 41 to expose an upper surface of the third capacitor electrode 39 and the fourth via 44 extends through the second electrically insulating layer 41, the second dielectric layer 37 of predetermined dielectric material and the first electrically insulating layer 31 to expose the inversion-layer charge source regions 29 of second conductivity type.
  • a first conductivity type contact region 30 is also provided therein. As illustrated, metallization is also patterned in the fourth via 44 to electrically connect the first conductivity type contact region 30 to the second capacitor contact 45.
  • the application of a predetermined potential bias to the first and second capacitor electrodes 27 and 35 will cause (i) the formation of an inversion-layer channel of second conductivity type charge carriers (e.g., electrons) in the region 23 of first conductivity type at the face, opposite the first capacitor electrode 27; and (ii) the formation of a density of second conductivity type charge carriers on the third capacitor electrode 39, if the second capacitor contact 45 is maintained at ground potential (GND), as illustrated.
  • the formation of the first, second and third capacitor electrodes in stacked vertical relationship, as illustrated essentially doubles the area and effective capacitance of the integrated decoupling capacitor, relative to the prior art decoupling capacitor of FIG. 1.
  • the decoupling capacitor of FIG. 2 can be formed simultaneously with the formation of active devices of an integrated circuit such as a memory cell, without requiring additional process steps.
  • FIG. 3 illustrates the steps of forming diffused well regions 54, 54a of first conductivity type at separate spaced locations in a semiconductor substrate 51 of first or second conductivity type.
  • These well regions 54, 54a may be formed by implanting and diffusing first conductivity type dopants into a face of the semiconductor substrate 51, using a previously formed field oxide isolation region as an implant mask.
  • the diffused well region 54a of first conductivity type may be formed by implanting and diffusing dopants of first conductivity type into a well region 53 of second conductivity type, at an exposed portion of the face of the substrate 51.
  • a first dielectric layer of predetermined dielectric material (e.g., SiO 2 ) is then formed on the well regions 54, 54a of first conductivity type, by deposition of the dielectric material onto the face or thermal oxidation of the face, for example. Then, a first layer of conductive material such as doped polycrystalline silicon is deposited on the first dielectric layer. The layers of conductive material and dielectric material are then patterned using conventional techniques to form an insulated first capacitor electrode 59, on a first capacitor electrode insulating region 55 and form a gate electrode 61 of an insulated-gate field effect transistor, on a gate insulating region 57.
  • predetermined dielectric material e.g., SiO 2
  • sidewall insulating spacers 60 are then formed on edges of the patterned first capacitor electrode 59 and opposing ends of the insulated gate electrode 61.
  • Self-aligned source and drain regions 62 for the insulated-gate field effect transistor and inversion-layer charge source regions 63 for the decoupling capacitor are then preferably formed in the well regions 54, 54a of first conductivity type by implanting second conductivity type dopants (e.g., N-type), using the insulating spacers as a mask.
  • a first conductivity type contact region 64 (e.g., P+) may also be formed in the well region 54 to facilitate maintaining the well region 54 at a predetermined potential.
  • An electrically insulating layer (e.g., SiO 2 ) and patterned word line 65 for the memory cell are then formed, using conventional techniques.
  • Another electrically insulating layer (e.g., SiO 2 ) is then deposited conformally across the surface of the substrate 51 to form a first isolation region 67.
  • the first isolation region 67 is then selectively etched back using conventional photolithographic patterning techniques to form a first electrically insulating layer 69 on the insulated first capacitor electrode 59 and on the well region 54.
  • a first via or contact hole 71 is then formed in the first electrically insulating layer 69 to expose a portion of the upper surface of the first capacitor electrode 59.
  • a second contact hole 72 is formed in the first isolation region 67 to expose the source/drain region 62 of the insulated-gate field effect transistor.
  • a second conductive layer such as a doped polycrystalline silicon layer, is then deposited on the first electrically insulating layer 69 and in the first and second contact holes 71 and 72.
  • the second conductive layer is then patterned using conventional techniques to form a second capacitor electrode 73 and gate electrode 75 of a thin-film transistor (TFT), which is connected to the drain/source region 62 of the insulated-gate field effect transistor.
  • TFT thin-film transistor
  • a second dielectric layer 77 of predetermined dielectric material (e.g., SiO 2 , Si 3 N 4 ) is then deposited on the first electrically insulating layer 69, second capacitor electrode 73, thin-film transistor gate electrode 75 and first isolation region 67, as illustrated.
  • a contact opening 78 is then formed in the second dielectric layer 77 to expose the gate electrode 75 of the thin-film transistor.
  • a third conductive layer, such as doped polycrystalline or amorphous silicon (a-Si) is then deposited and patterned as a third capacitor electrode 79 and source/drain region 80 of the thin-film transistor.
  • a blanket second electrically insulating layer 81 (e.g., SiO 2 ) is then deposited, and patterned to form openings 84, 85 to the inversion-layer charge source regions 63, third capacitor electrode 79 and first conductivity type contact region 64, as illustrated.
  • the second electrically insulating layer 81 is also patterned to form openings 83, 86 to the second capacitor electrode 73 and source/drain region 62 of the insulated-gate field effect transistor, respectively.
  • Metallization is then deposited on the second electrically insulating layer 81 and in the openings and then patterned to form a first capacitor contact 87, second capacitor contact 89 and source/drain contact 91 to the insulated-gate field effect transistor in the static random-access memory cell.
  • an integrated decoupling capacitor comprises a semiconductor substrate 21 of first or second conductivity type and a diffused well region 23 of first conductivity type (e.g., P-type) therein extending to a first portion of a face of the semiconductor substrate 21, defined by an opening in a field oxide isolation region.
  • An insulated first capacitor electrode 27a is provided on the first portion of the face.
  • the first capacitor electrode 27a is preferably electrically insulated from the face by a first dielectric layer 25 of predetermined dielectric material.
  • a first electrically insulating layer 31 is provided on an upper surface of the first capacitor electrode 27a.
  • a second capacitor electrode 35a is also provided on the first electrically insulating layer 31, opposite the first capacitor electrode 27a.
  • a third capacitor electrode 39a is also patterned opposite the second capacitor electrode 35a and is separated therefrom by a second dielectric layer 37 of predetermined dielectric material (e.g., SiO 2 , Si 3 N 4 ).
  • the third capacitor electrode 39a is electrically insulated from upper levels of metallization by a second electrically insulating layer 41.
  • a first capacitor contact 47a (e.g., VCC) is also provided by patterning metallization in a first via which extends through the second electrically insulating layer 41, second dielectric layer 37 and first electrically insulating layer 31 to expose an upper surface of the first capacitor electrode 27a.
  • a fourth via which extends through the second electrically insulating layer 41 to expose an upper surface of the third capacitor electrode 39a is also provided to electrically connect the first and third capacitor electrodes 27a, 39a together, via the first capacitor contact 47a.
  • a second capacitor contact 45a (e.g., GND) is also provided by patterning metallization in third and fourth vias 43 and 44, respectively.
  • the third via 43 extends through the second electrically insulating layer 41 and second dielectric layer 37 to expose an upper surface of the second capacitor electrode 35a
  • the fourth via 44 extends through the second electrically insulating layer 41, the second dielectric layer 37 and the first electrically insulating layer 31 to expose the inversion-layer charge source regions 29 of second conductivity type.
  • metallization is also patterned in the fourth via 44 to electrically connect the first conductivity type contact region 30 to the second capacitor contact 45a.
  • the method of forming the integrated decoupling capacitor of FIG. 10 is essentially identical to the method illustrated by FIGS. 3-9. However, the step of opening a first via 71 (33) in the first electrically insulating layer 69 (31), as illustrated best by FIG. 5, is eliminated. Instead, the second insulating layer 41 is patterned to define first and fourth vias so that the first capacitor contact 47a electrically connects the first and third capacitor electrodes 27a, 39a. The second insulating layer 41 is also patterned to define second and third vias so that the second capacitor contact 45a electrically connects the second capacitor electrode 35a to the inversion-layer channel source regions 29.
  • an integrated decoupling capacitor comprises a semiconductor substrate 101 of first or second conductivity type and a diffused well region 103 of first conductivity type (e.g., P-type) therein extending to a first portion of a face of the semiconductor substrate 101, defined by an opening in a field oxide isolation region.
  • An insulated first capacitor electrode 107 is provided on the first portion of the face.
  • the first capacitor electrode 107 is preferably electrically insulated from the face by a first dielectric layer 105 of predetermined dielectric material.
  • a second dielectric layer 109 is provided on an upper surface of the first capacitor electrode 107.
  • a second capacitor electrode 111 is also provided on the second dielectric layer 109. To achieve high levels of integration, the second capacitor electrode 111 is patterned opposite the first capacitor electrode 107. The second capacitor electrode 111 is electrically insulated from upper levels of metallization by an electrically insulating layer 117.
  • a first capacitor contact 115 e.g., VCC
  • a second capacitor contact 113 is also provided by patterning metallization in vias which expose an upper surface of the second capacitor electrode 111, the inversion-layer charge source region and first conductivity type contact region.
  • the application of a predetermined potential bias to the first capacitor electrode 107 will cause (i) the formation of an inversion-layer channel of second conductivity type charge carriers (e.g., electrons) in the region 103 of first conductivity type at the face, opposite the first capacitor electrode 107; and (ii) the formation of a density of second conductivity type charge carriers on the second capacitor electrode 111, if the second capacitor contact 113 is maintained at ground potential (GND), as illustrated.
  • the formation of the first and second capacitor electrodes in stacked vertical relationship, as illustrated essentially doubles the area and effective capacitance of the integrated decoupling capacitor, relative to the prior art decoupling capacitor of FIG. 1.
  • the decoupling capacitor of FIG. 11 can also be formed simultaneously with the formation of active devices of an integrated circuit such as a memory cell, without requiring additional process steps.
  • FIG. 12 illustrates the steps of forming diffused well regions 124, 124a of first conductivity type at separate spaced locations in a semiconductor substrate 121 of first or second conductivity type.
  • These well regions 124, 124a may be formed by implanting and diffusing first conductivity type dopants into a face of the semiconductor substrate 121, using a previously formed field oxide isolation region as an implant mask.
  • the diffused well region 124a of first conductivity type may be formed by implanting and diffusing dopants of first conductivity type into a well region 123 of second conductivity type, at an exposed portion of the face of the substrate 121.
  • a first dielectric layer of predetermined dielectric material (e.g., SiO 2 ) is then formed on the well regions 124, 124a of first conductivity type, by deposition of the dielectric material onto the face or thermal oxidation of the face, for example. Then, a first layer of conductive material such as doped polycrystalline silicon is deposited on the first dielectric layer. The layers of conductive material and dielectric material are then patterned using conventional techniques to form an insulated first capacitor electrode 129, on a first capacitor electrode insulating region 125 and form a gate electrode 131 of an insulated-gate field effect transistor, on a gate insulating region 127.
  • predetermined dielectric material e.g., SiO 2
  • self-aligned source and drain regions 132 for the insulated-gate field effect transistor and inversion-layer charge source regions 133 for the decoupling capacitor are then preferably formed by implanting second conductivity type dopants into the well regions 124, 124a of first conductivity type.
  • a first conductivity type contact region 134 (e.g., P+) may also be formed in the well region 124 to facilitate maintaining the well region 124 at a predetermined potential.
  • An electrically insulating layer e.g., SiO 2
  • patterned word line 135 for the memory cell are then formed, using conventional techniques.
  • Another electrically insulating layer (e.g., SiO 2 ) is then deposited conformally across the surface of the substrate 121 to form a first isolation region 137.
  • the first isolation region 137 is then selectively removed using conventional techniques to form a substrate insulating layer 139 and expose an upper surface of the first capacitor electrode 129.
  • a contact hole 140 is then formed in the first isolation region 137.
  • a second conductive layer such as a doped polycrystalline silicon layer, is then deposited and patterned on the first isolation region 137 and in the contact hole 140, to form a gate electrode 141 of a thin-film transistor (TFT), which is connected to the drain/source region 132 of the insulated-gate field effect transistor.
  • TFT thin-film transistor
  • a first dielectric layer 143 of predetermined dielectric material (e.g., SiO 2 , Si 3 N 4 ) is then deposited, as illustrated.
  • a contact opening 145 is then formed in the second dielectric layer 143 to expose the gate electrode 141 of the thin-film transistor.
  • a third conductive layer, such as doped polycrystalline or amorphous silicon (a-Si) is then deposited and patterned as a second capacitor electrode 147 and source/drain region 148 of the thin-film transistor.
  • a blanket electrically insulating layer 151 (e.g., SiO 2 ) is then deposited, and patterned to form openings 153-156 to the first capacitor electrode 129, second capacitor electrode 147, inversion-layer charge source regions 133, first conductivity type contact region 64 and source/drain region 132 of the insulated-gate field effect transistor, as illustrated by FIG. 15.
  • Metallization is then deposited on the electrically insulating layer 151 and in the openings and patterned to form a first capacitor contact 159, second capacitor contact 161 and source/drain contact 163 to the insulated-gate field effect transistor in the static random-access memory cell, as illustrated by FIG. 16.

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KR1019950030681A KR0183739B1 (ko) 1995-09-19 1995-09-19 감결합 커패시터를 포함하는 반도체 장치 및 그 제조방법
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US6124163A (en) * 1995-10-06 2000-09-26 Micron Technology, Inc. Integrated chip multiplayer decoupling capacitors
WO2001037320A3 (en) * 1999-11-18 2001-12-06 Infineon Technologies Corp Optimized decoupling capacitor using lithographic dummy filler
US6674632B2 (en) * 2000-07-21 2004-01-06 Koninklijke Philips Electronics N.V. Mobile telephone device with passive integrated module
US20040195694A1 (en) * 1999-01-04 2004-10-07 International Business Machines Corporation BEOL decoupling capacitor
US20050064673A1 (en) * 2003-09-24 2005-03-24 Texas Instruments Incorporated High capacitive density stacked decoupling capacitor structure
US20050247968A1 (en) * 2002-12-11 2005-11-10 Oh Byung-Jun Integrated circuit devices including a capacitor
US20060208299A1 (en) * 2005-03-21 2006-09-21 Samsung Electronics Co., Ltd. Semiconductor device having stacked decoupling capacitors
US20070079488A1 (en) * 2003-09-23 2007-04-12 Daehwan Kim On-chip bypass capacitor and method of manufacturing the same
US20110037144A1 (en) * 2009-08-13 2011-02-17 Broadcom Corporation Method for fabricating a decoupling composite capacitor in a wafer and related structure
US20110070718A1 (en) * 2006-06-08 2011-03-24 Kim Yoon-Hae Semiconductor device and method of fabricating the same
US20190131385A1 (en) * 2017-10-26 2019-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Metal-insulator-metal (mim) capacitor structure and method for forming the same
US10943973B2 (en) * 2018-05-02 2021-03-09 Stmicroelectronics (Rousset) Sas Integrated circuit comprising low voltage capacitive elements

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KR100442144B1 (ko) * 2001-12-20 2004-07-27 동부전자 주식회사 반도체 장치의 다층 커패시터 제조 방법
KR100437617B1 (ko) * 2002-05-03 2004-06-30 주식회사 하이닉스반도체 반도체 소자의 디커플링 캐피시터 형성방법
KR100479823B1 (ko) * 2002-07-19 2005-03-30 주식회사 하이닉스반도체 반도체소자의 디커플링 캐패시터 및 그 형성방법
KR100480603B1 (ko) * 2002-07-19 2005-04-06 삼성전자주식회사 일정한 커패시턴스를 갖는 금속-절연체-금속 커패시터를 포함하는 반도체 소자
JP2005057254A (ja) * 2003-07-18 2005-03-03 Yamaha Corp 半導体装置
JP4908006B2 (ja) * 2006-02-03 2012-04-04 株式会社東芝 半導体装置
JP6445374B2 (ja) * 2015-04-01 2018-12-26 ローム株式会社 コンデンサ構造

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US20070145452A1 (en) * 2002-12-11 2007-06-28 Oh Byung-Jun Integrated Circuit Devices Including A Capacitor
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US6969880B2 (en) * 2003-09-24 2005-11-29 Texas Instruments Incorporated High capacitive density stacked decoupling capacitor structure
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US7999297B2 (en) 2005-03-21 2011-08-16 Samsung Electronics Co., Ltd. Semiconductor device having stacked decoupling capacitors
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US8497564B2 (en) * 2009-08-13 2013-07-30 Broadcom Corporation Method for fabricating a decoupling composite capacitor in a wafer and related structure
US20190131385A1 (en) * 2017-10-26 2019-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Metal-insulator-metal (mim) capacitor structure and method for forming the same
US10468478B2 (en) * 2017-10-26 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Metal-insulator-metal (MIM) capacitor structure and method for forming the same
US11031458B2 (en) 2017-10-26 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd Metal-insulator-metal (MIM) capacitor structure and method for forming the same
US11362170B2 (en) 2017-10-26 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insulator-metal (MIM) capacitor structure and method for forming the same
US11728375B2 (en) 2017-10-26 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insulator-metal (MIM) capacitor structure
US10943973B2 (en) * 2018-05-02 2021-03-09 Stmicroelectronics (Rousset) Sas Integrated circuit comprising low voltage capacitive elements
US11605702B2 (en) 2018-05-02 2023-03-14 Stmicroelectronics (Rousset) Sas Method of manufacturing an integrated circuit comprising a capacitive element

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