US5780354A - Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material glued on a support wafer - Google Patents

Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material glued on a support wafer Download PDF

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US5780354A
US5780354A US08/576,538 US57653895A US5780354A US 5780354 A US5780354 A US 5780354A US 57653895 A US57653895 A US 57653895A US 5780354 A US5780354 A US 5780354A
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layer
wafer
semiconductor
passivating
sub
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Ronald Dekker
Henricus G.R. Maas
Steffen Wilhelm Hahn
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Adeia Semiconductor Technologies LLC
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US Philips Corp
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Definitions

  • the invention relates to a method of manufacturing a semiconductor device, which method starts with a semiconductor wafer which at a first side is provided with a top layer of semiconductor material situated on an insulating layer, after which semiconductor elements and conductor tracks are formed on this first side of the semiconductor wafer, the semiconductor wafer is glued with this first side to a support wafer, and material is removed from the semiconductor wafer from the other, second side until the insulating layer has been exposed.
  • the support wafer with the layer comprising semiconductor elements glued thereto may subsequently be subdivided into individual semiconductor devices in usual manner, which devices may comprise one or several semiconductor elements such as bipolar or field effect transistors.
  • the semiconductor elements in semiconductor devices thus manufactured are formed in the comparatively thin top layer of semiconductor material which is in an insulated position. Detrimental capacitances are absent, so that these devices can process signals of very high frequencies.
  • EP-A-570 224 discloses a method of the kind mentioned in the opening paragraph wherein the basic semiconductor wafer is a silicon wafer whose top layer situated at the first side consists of monocrystalline silicon, while the insulating layer is made of silicon oxide.
  • This semiconductor wafer is formed by wafer bonding. In this process, two wafers of silicon are first provided with a layer of thermal oxide at one side. Then these wafers are bonded together with their oxidized surfaces under pressure and at a high temperature. Finally, one of the wafers thus bonded is subjected to a polishing and etching treatment whereby so much silicon is removed that the desired semiconductor wafer is formed.
  • the insulating silicon oxide layer serves as a layer at which the material-removing treatment from the second side of the semiconductor wafer stops automatically when the method mentioned in the opening paragraph is being carried out.
  • the insulating layer which itself is not removed during this, may then be used as an insulation for the semiconductor elements.
  • Windows may be provided in this layer for external contacting of the semiconductor device.
  • a usual passivating layer of a scratch-proof material which is practically impermeable to moisture, to alkali atoms such as sodium, and to other mobile metallic impurities, should be provided on the silicon oxide layer.
  • the semiconductor wafer While such a passivating layer is being provided, the semiconductor wafer must be heated to a temperature of between 300° and 400° C. in practice. After the semiconductor wafer has been glued to the support wafer, however, a treatment at a temperature higher than 200° C. may damage the glue connection.
  • the invention has for its object inter alia to improve the method mentioned in the opening paragraph to such an extent that the second side of the semiconductor wafer is provided with a usual passivating layer without the necessity of heating the semiconductor wafer to a temperature higher than 200° C. after it has been glued on the support wafer.
  • the method is for this purpose characterized in that the insulating layer of the semiconductor wafer with which the method starts is an insulating as well as a passivating layer.
  • This insulating and passivating layer which is exposed, insulates and protects the semiconductor elements and conductor tracks present in the semiconductor device after the method has been completed. Since this layer has been present right from the start of the method, however, the semiconductor wafer need not be heated any more for the formation of a passivating layer after the glue connection has been effected.
  • the semiconductor wafer may accordingly be fastened on the support wafer by means of a synthetic resin glue such as an epoxy or acrylate glue.
  • the insulating and passivating layer may be formed by a layer of a material which is both insulating and passivating. This layer is in direct contact with the layer of semiconductor material and serves as a stopper layer in the removal of material from the semiconductor wafer.
  • the material of the insulating and passivating layer should accordingly not only have good insulating and passivating properties, but it also must not interfere with the manufacture and the operation of semiconductor elements in the layer of semiconductor material, while it should perform satisfactorily as a stopper layer. It is difficult to choose a suitable material for this layer if all these requirements are to be met. This choice is made easier when an insulating and passivating layer is used which comprises a sub-layer of a passivating material and a sub-layer of an insulating material.
  • a passivating and insulating layer is even used of which the sub-layer of passivating material is bounded on either side by a sub-layer of insulating material.
  • a sub-layer need comply with part of the requirements mentioned above only, which renders the choice of material easier.
  • the sub-layer of passivating material is bounded on either side by a sub-layer of silicon oxide.
  • the sub-layer of passivating material is then preferably formed by a layer of silicon nitride or a layer of phosphorus glass, or by a dual layer comprising a layer of silicon nitride and a layer of phosphorus glass.
  • a usual layer of silicon nitride or phosphorus glass forms a layer which is practically impermeable to moisture, alkali atoms such as sodium, and other mobile metallic impurities.
  • the one layer of silicon oxide present below the layer of semiconductor material ensures that the manufacture and operation of semiconductor elements in the layer of semiconductor material is not interfered with.
  • the silicon oxide sub-layer prevents this phosphorus from diffusing towards the layer of semiconductor material.
  • the other silicon oxide sub-layer acts as a stopper layer, for example as an etching stopper layer when silicon is etched in a KOH etching bath during the removal of material from the semiconductor wafer.
  • the semiconductor wafer with which the method starts may be formed, for example, by ion implantation. Ions may be implanted, for example, into a layer situated at some distance from the surface, which ions together with silicon form an insulating and passivating material. It is only possible in practice to realise insulating and passivating layers of small thickness in this manner, which thickness may be insufficient for some applications if the above requirements are to be met.
  • the method starts with a semiconductor wafer which is obtained by wafer bonding.
  • a first silicon wafer is provided at one of its sides consecutively with a layer of silicon oxide, a layer of a passivating material, and a layer of silicon oxide, after which a second wafer is provided with a layer of silicon oxide at one of its sides. Then the two wafers are bonded together with their sides on which the layers were provided.
  • the thicknesses of the layers formed on the two wafers may be chosen substantially freely then.
  • the layer of passivating material on the first silicon wafer is formed by a layer of silicon nitride or a layer of phosphorus glass, or by a dual layer comprising a layer of silicon nitride and a layer of phosphorus glass.
  • FIGS. 1 to 6 diagrammatically and in cross-section show a portion of a semiconductor device in a few stages of its manufacture by the method according to the invention
  • FIGS. 7 to 9 diagrammatically and in cross-section show a few stages in the manufacture of a semiconductor wafer with which the method shown in FIGS. 1 to 6 starts.
  • FIGS. 1 to 6 diagrammatically and in cross-section show a portion of a semiconductor device in a few stages of its manufacture by the method according to the invention.
  • the method starts with a semiconductor wafer 1 which has at its first side 2 an approximately 1 ⁇ m thick top layer of semiconductor material 4, in this example a top layer of monocrystalline silicon, disposed on an insulating layer 3.
  • Semiconductor elements are formed on the first side 2 in usual manner. These may be various elements such as field effect transistors and bipolar transistors. The provision of a single element in the form of a field effect transistor is shown in this example for the sake of clarity.
  • the top layer 4 is for this purpose provided with a p-type doping in usual manner and subsequently subdivided into mutually insulated islands 5, in this example in that the top layer 4 of silicon is etched away from between the islands 5 of the insulating layer 3. A field effect transistor is formed in each of these islands.
  • the silicon top layer 4 is provided with a layer of gate dielectric 6 through a usual thermal oxidation of the silicon top layer 4.
  • a layer of polycrystalline silicon 7 is deposited in which a gate electrode 8 is formed. With the gate electrode 8 as a mask, source 9 and drain 10 are subsequently formed through implantation of an n-type dopant.
  • the transistor thus formed is covered with an insulating silicon oxide layer 11.
  • Contact windows 12 are provided in the silicon oxide layer 11, after which conductor tracks 14 are formed in a conducting layer 13 on the first side 2 of the semiconductor wafer 1 in usual manner.
  • the semiconductor wafer 1 is fastened with its first side 2 to a support wafer 15.
  • the semiconductor wafer 1 is fastened on an approximately 1.5 mm thick glass support wafer 15 by means of a layer of acrylate glue 16.
  • material 18 is removed from the semiconductor wafer from the other, second side 17 until the insulating layer 3 has become exposed.
  • the second side 17 is first subjected to a usual chemical mechanical polishing treatment until the insulating layer 3 has been approached up to a few tens of ⁇ m, after which this layer 3 is exposed in a KOH etching bath.
  • the etching treatment stops automatically the moment the layer 3 is reached, this layer acting as an etching stopper layer.
  • the insulating layer 3 is provided with contact windows 19 in which conductive elements 20 are provided which are connected to the semiconductor elements, in the drawing to the source 9 of the transistor.
  • the contact windows 19 and the conductive elements 20 are formed from the first side 2 of the semiconductor wafer 1 before the latter was fastened to the support wafer 15.
  • the contact windows 19 are formed in the insulating silicon oxide layer 3 in the same photolithographical process step in which also the contact windows 12 are formed in the silicon oxide layer 11.
  • the conductor tracks 14 and the conductive elements 20 may also be formed by means of a single photolithographical process step.
  • the conductive elements 20 provided in the contact windows 19 have also been exposed.
  • the semiconductor elements, in the example the field effect transistor, may then be contacted by means of these exposed conductive elements 20. This is effected in the example by means of a contact wire 21 provided by a usual bonding technique. It is also possible to provide an external contact on the exposed conductive elements 19 by an electroplating method.
  • the support wafer is subdivided into individual parts in a usual manner, for example by sawing, so that individual semiconductor devices are formed which each may comprise one or several semiconductor elements.
  • All process steps preceding the fastening of the semiconductor wafer 1 on the support wafer 15 may be performed in a space different from the space in which the remaining process steps are carried out.
  • the former steps are carried out in a dust-free room or clean room, the remaining steps in a room in which the absence of dust particles is subject to less stringent requirements.
  • the method according to the invention can be carried out comparatively inexpensively.
  • the insulating layer 3 of the semiconductor wafer 1 of the method is an insulating as well as a passivating layer.
  • This insulating and passivating layer 3 which is exposed insulates and protects the semiconductor elements 5 and conductor tracks 14 present in the semiconductor device after the method has been completed. Since this layer 3 has been present right from the start of the method, however, the construction manufactured, comprising the support wafer 15, the glue layer 16 and the insulating and passivating layer 3, need not be heated any more for the formation of a passivating layer.
  • the semiconductor wafer 1 can be fastened on the support wafer 15 with a synthetic resin glue such as an epoxy or acrylate glue.
  • the insulating and passivating layer 3 may be formed by a layer of a material which is both insulating and passivating. This layer is in direct contact with the layer of semiconductor material 4 and serves as a stopper layer in the removal of material 18 from the semiconductor wafer 1. This means that the material of the insulating and passivating layer must not only have good insulating and passivating properties, but also must not interfere with the manufacture and the operation of the semiconductor elements in the layer of semiconductor material, while it should perform satisfactorily as a stopper layer. It is difficult to find a suitable material for this layer 3 which complies with all these requirements.
  • an insulating and passivating layer 3 which comprises a sub-layer 22 of a usual passivating material and a sub-layer of an insulating material.
  • a passivating and insulating layer 3 is even used whose sub-layer 22 of passivating material is bounded on either side by a sub-layer 23, 24 of insulating material. In these cases, it is sufficient for a sub-layer 22, 23 or 24 to comply with only part of the above requirements, which renders the choice of material easier.
  • the sub-layer 22 of passivating material is bounded on either side by a sub-layer 23, 24 of silicon oxide.
  • the sub-layer 22 of passivating material is then preferably formed by a usual silicon nitride layer or a layer of phosphorus glass, or by a dual layer comprising a silicon nitride layer and a phosphorus glass layer.
  • a layer of silicon nitride or phosphorous glass is practically impermeable to moisture, alkali atoms such as sodium, and other mobile metallic impurities.
  • the one sub-layer 23 of silicon oxide which lies below the layer of semiconductor material ensures that the manufacture and the operation of semiconductor elements in the layer of semiconductor material are interfered with.
  • the sub-layer 23 of silicon oxide prevents this phosphorus from diffusing into the layer 4 of semiconductor material.
  • the other sub-layer 24 of silicon oxide acts as a stopper layer, for example as an etching stopper layer when silicon is etched in a KOH etching bath during the removal of material 18 from the silicon semiconductor wafer.
  • the semiconductor wafer 1 on which the method is based may be formed, for example, through ion implantation. Ions forming an insulating and passivating material with silicon may be implanted, for example, into a silicon slice into a layer situated at some distance from the surface. It is possible in practice to realise insulating and passivating layers of a small thickness only in this way, which thickness may be insufficient in some applications for meeting the above requirements.
  • the method preferably starts, therefore, with a semiconductor wafer which is obtained by wafer bonding, see FIGS. 7 to 9.
  • a first silicon wafer 25 is then provided at one of its sides in that order with a layer of silicon oxide 26, a layer of a passivating material 27, and a layer of silicon oxide 28, and a second wafer 29 is provided at one of its sides with a layer of silicon oxide 30.
  • the two wafers 25 and 29 are subsequently bonded together with their sides on which the layers 26, 27, 28 and 30 were provided.
  • the silicon oxide layers 28 and 30 form a joint silicon oxide layer 31 after that.
  • the thicknesses of the layers formed on the two wafers may be chosen practically freely when the semiconductor wafer 1 is manufactured in this way.
  • the layer of passivating material 27 on the first silicon wafer 25 is formed by a usual layer of silicon nitride or a layer of phosphorus glass, or by a dual layer comprising a silicon nitride layer and a phosphorus glass layer.
  • the silicon oxide layers 28 and 30 have a thickness, for example, of approximately 0.2 gm, the silicon oxide layer 26 a thickness of approximately 0.4 ⁇ m, while the passivating layer 27 is an approximately 0.1 gm thick layer of silicon nitride.
  • one of these wafers 29 is subjected to a suitable and usual polishing treatment whereby silicon is removed until a silicon layer 32 of a desired thickness, for example of 1 ⁇ m, remains on the insulating and passivating layer 26, 27, 31.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
US08/576,538 1994-12-23 1995-12-21 Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material glued on a support wafer Expired - Lifetime US5780354A (en)

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US09/080,784 US6104081A (en) 1994-12-23 1998-05-18 Semiconductor device with semiconductor elements formed in a layer of semiconductor material glued on a support wafer

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EP94203751 1994-12-23
EP94203751 1994-12-23

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5993677A (en) * 1996-01-25 1999-11-30 Commissariat A L'energie Atomique Process for transferring a thin film from an initial substrate onto a final substrate
FR2871291A1 (fr) * 2004-06-02 2005-12-09 Tracit Technologies Procede de transfert de plaques
US20060046350A1 (en) * 2004-08-31 2006-03-02 Tongbi Jiang Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
DE102007034306B3 (de) * 2007-07-24 2009-04-02 Austriamicrosystems Ag Halbleitersubstrat mit Durchkontaktierung und Verfahren zur Herstellung eines Halbleitersubstrates mit Durchkontaktierung

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997034317A1 (fr) * 1996-03-12 1997-09-18 Philips Electronics N.V. Procede de fabrication d'un circuit integre hybride
JP3565090B2 (ja) * 1998-07-06 2004-09-15 セイコーエプソン株式会社 半導体装置の製造方法
WO2000065655A1 (fr) 1999-04-23 2000-11-02 Koninklijke Philips Electronics N.V. Dispositif semi-conducteur a frequence de fonctionnement superieure a 50 mhz comportant un corps constitue d'un materiau de ferrite doux
DE19918671B4 (de) * 1999-04-23 2006-03-02 Giesecke & Devrient Gmbh Vertikal integrierbare Schaltung und Verfahren zu ihrer Herstellung
TW455964B (en) * 2000-07-18 2001-09-21 Siliconware Precision Industries Co Ltd Multi-chip module package structure with stacked chips
JP2003023141A (ja) * 2001-07-09 2003-01-24 Tokyo Electron Ltd 半導体基板の製造方法および半導体基板
JP2003291343A (ja) * 2001-10-26 2003-10-14 Seiko Epson Corp 液体噴射ヘッド及びその製造方法並びに液体噴射装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980308A (en) * 1987-01-30 1990-12-25 Sony Corporation Method of making a thin film transistor
EP0570224A2 (fr) * 1992-05-14 1993-11-18 Seiko Instruments Inc. Dispositif à semi-conducteur
US5324678A (en) * 1989-09-22 1994-06-28 Mitsubishi Denki Kabushiki Kaisha Method of forming a multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules
US5403729A (en) * 1992-05-27 1995-04-04 Micro Technology Partners Fabricating a semiconductor with an insulative coating
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5520297A (en) * 1993-06-23 1996-05-28 Hitachi, Ltd. Aperture plate and a method of manufacturing the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468857A (en) * 1983-06-27 1984-09-04 Teletype Corporation Method of manufacturing an integrated circuit device
US4870475A (en) * 1985-11-01 1989-09-26 Nec Corporation Semiconductor device and method of manufacturing the same
US5065222A (en) * 1987-11-11 1991-11-12 Seiko Instruments Inc. Semiconductor device having two-layered passivation film
JPH0344067A (ja) * 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US5362667A (en) * 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
US5289031A (en) * 1990-08-21 1994-02-22 Kabushiki Kaisha Toshiba Semiconductor device capable of blocking contaminants
WO1993026041A1 (fr) * 1992-06-17 1993-12-23 Harris Corporation Traitement de tranches soudees
US5270221A (en) * 1992-11-05 1993-12-14 Hughes Aircraft Company Method of fabricating high quantum efficiency solid state sensors
JP3158749B2 (ja) * 1992-12-16 2001-04-23 ヤマハ株式会社 半導体装置
JPH06296023A (ja) * 1993-02-10 1994-10-21 Semiconductor Energy Lab Co Ltd 薄膜状半導体装置およびその作製方法
JP4060882B2 (ja) * 1995-05-10 2008-03-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子装置の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980308A (en) * 1987-01-30 1990-12-25 Sony Corporation Method of making a thin film transistor
US5324678A (en) * 1989-09-22 1994-06-28 Mitsubishi Denki Kabushiki Kaisha Method of forming a multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules
EP0570224A2 (fr) * 1992-05-14 1993-11-18 Seiko Instruments Inc. Dispositif à semi-conducteur
US5403729A (en) * 1992-05-27 1995-04-04 Micro Technology Partners Fabricating a semiconductor with an insulative coating
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5520297A (en) * 1993-06-23 1996-05-28 Hitachi, Ltd. Aperture plate and a method of manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5993677A (en) * 1996-01-25 1999-11-30 Commissariat A L'energie Atomique Process for transferring a thin film from an initial substrate onto a final substrate
FR2871291A1 (fr) * 2004-06-02 2005-12-09 Tracit Technologies Procede de transfert de plaques
WO2005124826A1 (fr) * 2004-06-02 2005-12-29 Tracit Technologies Procede de transfert de plaques
US20080254596A1 (en) * 2004-06-02 2008-10-16 Tracit Technologies Method for Transferring Wafers
US7807482B2 (en) 2004-06-02 2010-10-05 S.O.I.Tec Silicon On Insulator Technologies Method for transferring wafers
US20060046350A1 (en) * 2004-08-31 2006-03-02 Tongbi Jiang Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
US7268012B2 (en) 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
US7589426B2 (en) 2004-08-31 2009-09-15 Micron Technology, Inc. Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom
DE102007034306B3 (de) * 2007-07-24 2009-04-02 Austriamicrosystems Ag Halbleitersubstrat mit Durchkontaktierung und Verfahren zur Herstellung eines Halbleitersubstrates mit Durchkontaktierung
US20100314762A1 (en) * 2007-07-24 2010-12-16 Austriamicrosystems Ag Semiconductor Substrate with Through-Contact and Method for Production Thereof
US8378496B2 (en) 2007-07-24 2013-02-19 Austriamicrosystems Ag Semiconductor substrate with interlayer connection and method for production of a semiconductor substrate with interlayer connection

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US6104081A (en) 2000-08-15
JPH09509792A (ja) 1997-09-30
EP0746875B1 (fr) 2002-03-06
DE69525739D1 (de) 2002-04-11
EP0746875A1 (fr) 1996-12-11
WO1996020497A1 (fr) 1996-07-04
DE69525739T2 (de) 2002-10-02

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