US5235694A - Multi i/o device system using temporary store of ram data when associated communicating i/o devices are operating at various clocking phases - Google Patents

Multi i/o device system using temporary store of ram data when associated communicating i/o devices are operating at various clocking phases Download PDF

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Publication number
US5235694A
US5235694A US07/605,356 US60535690A US5235694A US 5235694 A US5235694 A US 5235694A US 60535690 A US60535690 A US 60535690A US 5235694 A US5235694 A US 5235694A
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data
memory
clock
memory means
read
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US07/605,356
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Akira Umeda
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Toshiba Corp
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Toshiba Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

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  • the present invention relates to control of a memory apparatus including a CPU (Central Processing Unit), a DMAC (Direct Memory Access Controller), and a DRAM (Dynamic Random Access Memory), and to an optical filing system using this memory control.
  • a memory apparatus including a CPU (Central Processing Unit), a DMAC (Direct Memory Access Controller), and a DRAM (Dynamic Random Access Memory), and to an optical filing system using this memory control.
  • CPU Central Processing Unit
  • DMAC Direct Memory Access Controller
  • DRAM Dynamic Random Access Memory
  • a circuit design of a memory apparatus can be made easy by designing an output timing of data read out from a DRAM to be matched with a transit point of an operation clock of the DRAM.
  • Another object of the present invention is to provide an optical data filing system employing the above memory control.
  • a memory control system of the present invention comprises a memory means for storing data and operating by a predetermined operation clock, a first read means for operating by a processor clock having a period which is an even multiple of a period of the operation clock of the memory means, a second read means for operating by a processor clock having a period which is an even multiple of the period of the operation clock of the memory means, a register means for temporarily storing data read out from the memory means when an output timing of the data read out from the memory means falls in the middle of the processor clock of the first or second read means, means for detecting a transit point of the processor clock of the first or second read means, and a control means for outputting the data stored in the register means to the first or second read means in synchronism with the transit point of the processor clock detected by the detecting means.
  • the control means can immediately transit to the next memory access cycle.
  • FIG. 1 is a block diagram showing an arrangement of a memory apparatus according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing an arrangement of a memory controller
  • FIGS. 3A to 3R are timing charts showing an operation performed when a clock phase of a DRAM is not matched with a clock phase of a DMAC;
  • FIG. 4 is a timing chart showing an operation performed when an operation timing of the DRAM matches a bus timing of the DMAC:
  • FIG. 5 is a block diagram showing an arrangement of a memory apparatus according to another embodiment of the present invention.
  • FIG. 6 is a block diagram showing an arrangement of an optical filing system incorporating the memory apparatus of the present invention.
  • FIG. 1 shows an arrangement of a memory apparatus according to the present invention.
  • This memory apparatus can be used in an optical data filing system in which data recording and data reproducing on and from a recording medium (such as MO disks and hard disk drives) are performed according to given program instruction data.
  • a recording medium such as MO disks and hard disk drives
  • reference numeral 1 denotes a DRAM (Dynamic Random Access Memory); 2, a CPU (Central Processing Unit); 3, a DMAC (Direct Memory Access Controller); 4, a dual port buffer arranged between DRAM 1 and CPU 2; 5, a dual port buffer arranged between DRAM 1 and DMAC 3; 6, a read register arranged between DRAM 1 and DMAC 3 in parallel with buffer 5; 7, a memory controller for controlling the above parts; and 8, a clock oscillator for generating various types of clocks.
  • DRAM Dynamic Random Access Memory
  • CPU Central Processing Unit
  • DMAC Direct Memory Access Controller
  • a combination of the CPU and the DMAC is not limited to the above combination.
  • two CPUs which operate by different processor clocks (having a period which is 2 n times that of an operation clock of a DRAM) may be used in combination with each other.
  • DRAM 1 may be used in combination with or replaced by an SRAM or a ROM.
  • FIG. 2 shows an internal arrangement of memory controller 7.
  • Memory controller 7 comprises arbiter 7a, timing pulse generator 7b, and phase detector 7c.
  • Arbiter 7a receives a status from CPU 2 or DMAC 3 and supplies a start signal to timing pulse generator 7b. During an operation, arbiter 7a holds the request.
  • Timing pulse generator 7b receives the start signal from arbiter 7a and generates various types of signals corresponding to the status.
  • timing pulse generator 7b Examples of the signal generated by timing pulse generator 7b are a ready signal (CRDY) for CPU 2, a ready signal (DRDY) for DMAC 3, an output enable signal (COE) for buffer 4, an output enable signal (DOE) for buffer 5, a read clock pulse signal (RCLK) for register 6, a row address strobe signal (RAS), a column address strobe signal (CAS), and a write enable signal (WE) for DRAM 1, and a read/write switch signal (R/W) for buffers 4 and 5.
  • Timing pulse generator 7b also generates a ready signal (RDY) for phase detector 7c.
  • Phase detector 7c receives the status and a phase signal (DPHS) from DMAC 3 and RDY from timing pulse generator 7b and generates an output enable signal (ROE) for register 6 in accordance with CLK.
  • DPHS phase signal
  • ROE output enable signal
  • phase detector 7c detects a timing at which signal S 0 ⁇ S 1 (FIG. 3D) as a status output from DMAC 3 changes to LOW, thereby determining the phase of the processor clock of DMAC 3.
  • signal DS (FIG. 3E) indicating a state of signal S 0 ⁇ S 1 obtained one clock after signal CLK (FIG. 3A) is made from above signal S 0 ⁇ S 1
  • signal DPHS takes a logic value opposite to that of previous DPHS.
  • signal DPHS is changed like "0, 1, 0, 1, . . .” at each leading edge of signal CLK (FIG. 3A), and this value directly indicates the phase of the processor clock of DMAC 3 at each leading edge of signal CLK. That is, the phases of signal DPHS and the processor clock of DMAC 3 are matched with each other.
  • phase of the processor clock of DMAC 3 can be determined from only signal S 0 ⁇ S 1 (FIG. 3D).
  • phase of phase signal DPHS can be used in determination.
  • This signal RDY indicates the end of an operation of DRAM 1.
  • register 6 is used to hold data until a timing at which DMAC 3 fetches the data.
  • signal RCLK (FIG. 3N) for fetching the read data in register 6
  • signal ROE (FIG. 3M) for enabling the output from register 6 are prepared. This signal RCLK is obtained by a logical OR of signals CLK and RDY.
  • the data is fetched by register 6 at the leading edge (time t3) of signal RCLK.
  • signal RDY (FIG. 3Q) is activated even when DMAC 3 does not access
  • signal RCLK (INSIGNIFICANT indicated in FIG. 3N) is output regardless of the operation state. Since, however, DMAC 3 always fetches data in a cycle (times t3 to t4) of signal CLK after signal RCLK is output, no problem is posed.
  • the memory read operation from DMAC 3 is ended as described above when the transit point of the operation state of DRAM 1 is not matched with the transit point of the bus status of DMAC 3.
  • Signal DRDY (FIG. 3R) is output to command DMAC 3 to end an instruction execution cycle which is currently being executed.
  • FIG. 4 shows a memory read operation performed by DMAC 3 when the transit point of the operation state of DRAM 1 is matched with the transit point of the bus status of DMAC 3.
  • FIG. 4 illustrates that readout data is fetched in DMAC 3 at the end timing of memory access processing. That is, when the phase of the processor clock of DMAC 3 is matched with the phase of the operation clock of DRAM 1, read data is fetched directly in DMAC 3 via buffer 5 without being temporarily held in register 6.
  • FIG. 5 shows a modification of the memory apparatus shown in FIG. 1.
  • An arrangement shown in FIG. 5 includes second DMAC (or a co-processor such as a digital signal processor) 3A, and dual port buffer 5A and register 6A for interfacing between DMAC 3A and DRAM 1 in addition to the arrangement shown in FIG. 1.
  • second DMAC or a co-processor such as a digital signal processor
  • dual port buffer 5A and register 6A for interfacing between DMAC 3A and DRAM 1 in addition to the arrangement shown in FIG. 1.
  • the present invention is not limited to the combination of one CPU and one DMAC but can be applied to an apparatus including a plurality of CPUs and a plurality of peripheral chips (such as a DMAC and a digital signal processor).
  • FIG. 6 shows an arrangement in which memory apparatus 100 shown in FIG. 1 is incorporated in an optical filing system.
  • CPU 2 and DMAC 3 coupled to memory 1 via buffer 4 and buffer 5, respectively, are connected to first bus 11 via arbiter 10 and to second bus 21 via arbiter 20.
  • Bus 11 is connected to optical disk unit 12, hard disk drive 13, floppy disk drive 14, keyboard 15, mouse 16, and communication unit 17.
  • Bus 21 is connected to page memory 22, display memory 23 connected to CRT 24, and CODEC 25 connected to scanner 26 and printer 27.
  • memory apparatus 100 having register 6 can access memory 1 at a high speed regardless of a state of clock phases of CPU 2 and CMAC 3 having different operation speeds.
  • the readout data is held in the register until the data read timing of the DMAC.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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US07/605,356 1989-10-31 1990-10-30 Multi i/o device system using temporary store of ram data when associated communicating i/o devices are operating at various clocking phases Expired - Fee Related US5235694A (en)

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JP1283744A JPH03144990A (ja) 1989-10-31 1989-10-31 メモリ装置
JP1-283744 1989-10-31

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313627A (en) * 1992-01-02 1994-05-17 International Business Machines Corp. Parity error detection and recovery
US5412488A (en) * 1991-05-24 1995-05-02 Canon Kabushiki Kaisha Data processing apparatus dual-bus data processing with reduced cpu and memory requirements
US5623622A (en) * 1991-10-08 1997-04-22 Fujitsu Limited Memory access control system which prohibits a memory access request to allow a central control unit to perform software operations
US6079001A (en) * 1994-08-31 2000-06-20 Motorola Inc. Method for accessing memory using overlapping accesses and early synchronous data transfer control
US6453399B2 (en) * 1994-01-20 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and computer having a synchronization signal indicating that the memory data output is valid

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030022493A (ko) * 2001-09-10 2003-03-17 주식회사 텔루션 통신 시스템의 메모리 억세스 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4545014A (en) * 1980-11-26 1985-10-01 Nippon Electric Co., Inc. Information processing apparatus
US4792929A (en) * 1987-03-23 1988-12-20 Zenith Electronics Corporation Data processing system with extended memory access
US4912632A (en) * 1987-04-22 1990-03-27 International Business Machines Corp. Memory control subsystem

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2053537B (en) * 1979-07-10 1983-08-10 Lucas Industries Ltd Digital computing apparatus
US4633434A (en) * 1984-04-02 1986-12-30 Sperry Corporation High performance storage unit
EP0321628B1 (en) * 1987-12-23 1992-11-04 International Business Machines Corporation Shared memory interface for a data processing system
JP2700552B2 (ja) * 1988-03-11 1998-01-21 株式会社リコー 画像ファイリングシステム

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4545014A (en) * 1980-11-26 1985-10-01 Nippon Electric Co., Inc. Information processing apparatus
US4792929A (en) * 1987-03-23 1988-12-20 Zenith Electronics Corporation Data processing system with extended memory access
US4912632A (en) * 1987-04-22 1990-03-27 International Business Machines Corp. Memory control subsystem

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5412488A (en) * 1991-05-24 1995-05-02 Canon Kabushiki Kaisha Data processing apparatus dual-bus data processing with reduced cpu and memory requirements
US5623622A (en) * 1991-10-08 1997-04-22 Fujitsu Limited Memory access control system which prohibits a memory access request to allow a central control unit to perform software operations
US5313627A (en) * 1992-01-02 1994-05-17 International Business Machines Corp. Parity error detection and recovery
US6453399B2 (en) * 1994-01-20 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and computer having a synchronization signal indicating that the memory data output is valid
US6079001A (en) * 1994-08-31 2000-06-20 Motorola Inc. Method for accessing memory using overlapping accesses and early synchronous data transfer control

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JPH03144990A (ja) 1991-06-20
EP0426169A2 (en) 1991-05-08
EP0426169A3 (en) 1994-05-18

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