US5233608A - Method of and a device for receiving data packet form - Google Patents

Method of and a device for receiving data packet form Download PDF

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Publication number
US5233608A
US5233608A US07/741,046 US74104691A US5233608A US 5233608 A US5233608 A US 5233608A US 74104691 A US74104691 A US 74104691A US 5233608 A US5233608 A US 5233608A
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United States
Prior art keywords
clock pulses
data
synchronized
packet
circuit system
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Expired - Fee Related
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US07/741,046
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English (en)
Inventor
Juha Savolainen
Rauno Stylman
Jukka Lamminmaki
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APLICOM Oy
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Computec Oy
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Application granted granted Critical
Publication of US5233608A publication Critical patent/US5233608A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S370/00—Multiplex communications
    • Y10S370/912—Packet communications

Definitions

  • the invention relates to a method of and a device for receiving data in packet form.
  • a synchronization with incoming data is searched for by means of a receiving modem and clock pulses in correct synchronization with the data are generated and the synchronized clock pulses are supplied to a receiver circuit system to ascertain the synchronization and to start receiving.
  • the device according to the invention comprises a modem for searching for a synchronization with incoming data and for generating clock pulses in correct synchronization with the data and a receiver circuit system connected to the modem to ascertain the synchronization and to start receiving.
  • the solution provided by the invention is especially suitable for radiotelephone systems, but it can also be applied to cable systems.
  • the receiving modem If there occurs a break in the data flow to be received during a data packet, the receiving modem begins to search for a new synchronization point at once, due to which it may be synchronized with noise, for instance, or with some other wrong point after the break. That is why the synchronization is often lost during a data break in present receiving systems, which leads to the eventuality that the receiving devices have to request for a retransmission of the whole data packet. Such a break can occur, e.g., due to a fading radio signal.
  • the object of the present invention is thus to get rid of the problem described above, and to provide a new type of a method of and a device for receiving data in packet form, by means of which method and device unnecessary repetitions of this kind can be avoided.
  • this can be achieved in such a way that, after the data reception has started, outer clock pulses generated by an outer circuit are synchronized substantially to the same frequency and the same phase as the synchronized clock pulses and the clock pulses to be supplied to the receiver circuit system are, for the time of the latter part of the data packet, replaced by the clock pulses generated by the outer circuit.
  • the basic idea of the invention is to replace the clock pulses generated by the modem after the synchronization achieved at the beginning of a data packet by another train of clock pulses which are independent of the modem and are with a sufficient accuracy synchronized to the frequency and the phase of the clock pulses generated by the modem, and to synchronize the reception by means of this other train of clock pulses until the end of the packet.
  • the synchronization achieved at the beginning of the data packet can be preserved at the data reception during the whole incoming packet, even if the data flow broke during transmission of the packet due to some interference, such as a fading radio signal, for instance. In such a way, the efficiency of the data transmission can be made better, because a great part of the repetitions required earlier can be avoided.
  • FIG. 1 shows a typical structure of a data packet to be received
  • FIG. 2 shows a block diagram of receiver devices according to the invention.
  • FIG. 1 shows a typical structure of a data packet DP to be received by means of devices according to the invention.
  • the packet comprises a frame header FH to be used for generating a synchronization and including, e.g., an identifier of a base station, a primary block PB including, e.g., the address of a mobile station and an information of the length of the whole data packet, and n successive data blocks DB, the number of which depends on the amount of the data to be transmitted.
  • the receiving devices according to the invention shown in FIG. 2 primarily comprise a modem 1 receiving incoming data 2 being in packet form and having a frame structure of the same type as the data packet DP shown, for instance, in FIG. 1.
  • the data to be received can be, for instance a FFSK (Fast Frequency Shift Keying) -modulated signal generally used in radiotelephone systems.
  • FFSK Frequency Shift Keying
  • a data output 3 of the modem 1 is connected to a data terminal D of a serial data input/output circuit SIO, and the input/output circuit again is connected to a control logic circuit 5 of the receiver in a manner known per se.
  • the connection between the input/output circuit and the control logic circuit is indicated by two bidirectional busses 15 and 16. There is a common term for the input/output circuit and the control logic circuit, viz. receiver circuit system.
  • the devices comprise an outer timing circuit 6 controlled by means of the control logic circuit 5 through bidirectional busses 17 and 18, a clock output 7 of the timing circuit being connected to a terminal 9 of a switch 8.
  • a clock output 13 of the modem 1 To the other terminal 10 of the switch 8 is connected a clock output 13 of the modem 1. In its rest position, the switch 8 is in the position according to FIG. 1, in which the clock output 13 of the modem is connected to a clock input CL of the input/output circuit SIO.
  • the modem 1 When the reception starts, the modem 1 is automatically synchronized with the incoming data, clock pulses CKI generated thereby being in exactly correct synchronization with the incoming data.
  • the clock pulses CKI are through the switch 8 connected to the clock input CL of the input/output circuit SIO, due to which the control logic circuit 5 ascertains that a synchronization (bit synchron) has been achieved and the input/output circuit SIO can start receiving data. All the phases described above are known per se, and therefore, they are not explained more closely in this connection.
  • clock pulses CK2 generated by the outer timing circuit 6 are synchronized by means of the control logic circuit 5 with a sufficient accuracy to the same frequency and the same phase as the clock pulses Ck1 generated by the modem 1.
  • the clock pulses received by the input/output circuit SIO are switched by the switch 8 to come from the outer timing circuit 6.
  • the switch is controlled by means of the control logic circuit 5 through a control bus 12 connected to the switch.
  • master clock pulses MCK controlling the timing circuit 6 and the rest of the system come from the same source, e.g.
  • CMOS-CD 4066 CMOS-CD 4066
  • timing circuit 6 Intel 82C54.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
US07/741,046 1990-08-15 1991-08-06 Method of and a device for receiving data packet form Expired - Fee Related US5233608A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI904042 1990-08-15
FI904042A FI85084C (fi) 1990-08-15 1990-08-15 Foerfarande och anordning foer mottagning av paketformigt data.

Publications (1)

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US5233608A true US5233608A (en) 1993-08-03

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US07/741,046 Expired - Fee Related US5233608A (en) 1990-08-15 1991-08-06 Method of and a device for receiving data packet form

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US (1) US5233608A (de)
EP (1) EP0471432A3 (de)
FI (1) FI85084C (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7434106B2 (en) 2002-07-31 2008-10-07 Seagate Technology Llc Reference clock failure detection on serial interfaces

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2731309A1 (fr) * 1995-03-01 1996-09-06 Trt Telecom Radio Electr Systeme de controle d'une chaine de transmission

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4596025A (en) * 1982-07-29 1986-06-17 Fuji Xerox Co., Ltd. Timing synchronization circuit
JPS61216541A (ja) * 1985-03-22 1986-09-26 Hitachi Ltd デ−タ伝送装置
JPS62242435A (ja) * 1986-04-15 1987-10-23 Fuji Xerox Co Ltd 非同期デ−タの読取装置
US4849993A (en) * 1987-12-10 1989-07-18 Silicon General, Inc. Clock holdover circuit
EP0333196A2 (de) * 1988-03-16 1989-09-20 Fujitsu Limited Verstärker zur Regenerierung eines rahmenmultiplexierten Signals
JPH01309540A (ja) * 1988-06-08 1989-12-13 Matsushita Electric Ind Co Ltd 網同期装置および網同期方法
US5050193A (en) * 1987-11-25 1991-09-17 Electronique Serge Dassault Device for synchronizing a clock in relation to an incident digital signal, in particular at high transmission rates

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2059797B1 (de) * 1970-12-04 1972-05-25 Siemens Ag Taktversorgungsanlage

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4596025A (en) * 1982-07-29 1986-06-17 Fuji Xerox Co., Ltd. Timing synchronization circuit
JPS61216541A (ja) * 1985-03-22 1986-09-26 Hitachi Ltd デ−タ伝送装置
JPS62242435A (ja) * 1986-04-15 1987-10-23 Fuji Xerox Co Ltd 非同期デ−タの読取装置
US5050193A (en) * 1987-11-25 1991-09-17 Electronique Serge Dassault Device for synchronizing a clock in relation to an incident digital signal, in particular at high transmission rates
US4849993A (en) * 1987-12-10 1989-07-18 Silicon General, Inc. Clock holdover circuit
EP0333196A2 (de) * 1988-03-16 1989-09-20 Fujitsu Limited Verstärker zur Regenerierung eines rahmenmultiplexierten Signals
JPH01309540A (ja) * 1988-06-08 1989-12-13 Matsushita Electric Ind Co Ltd 網同期装置および網同期方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, "External Clock Failure Detection in Communication Networks", vol. 26, No. No. 10B, Mar. 1984, p. 5686.
IBM Technical Disclosure Bulletin, External Clock Failure Detection in Communication Networks , vol. 26, No. No. 10B, Mar. 1984, p. 5686. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7434106B2 (en) 2002-07-31 2008-10-07 Seagate Technology Llc Reference clock failure detection on serial interfaces

Also Published As

Publication number Publication date
FI85084C (fi) 1992-02-25
FI904042A7 (fi) 1991-11-15
FI85084B (fi) 1991-11-15
EP0471432A2 (de) 1992-02-19
EP0471432A3 (en) 1992-07-08
FI904042A0 (fi) 1990-08-15

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