US5192908A - Semiconductor device testing apparatus with positioning mechanism - Google Patents

Semiconductor device testing apparatus with positioning mechanism Download PDF

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Publication number
US5192908A
US5192908A US07/814,787 US81478791A US5192908A US 5192908 A US5192908 A US 5192908A US 81478791 A US81478791 A US 81478791A US 5192908 A US5192908 A US 5192908A
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United States
Prior art keywords
semiconductor device
test table
test
testing
support surface
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Expired - Fee Related
Application number
US07/814,787
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English (en)
Inventor
Junichirou Shibata
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SHIBATA, JUNICHIROU
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals

Definitions

  • the present invention relates to an apparatus for testing a semiconductor device and, more particularly, to positioning of a packed semiconductor device in a test apparatus
  • an IC chip as a target test object is inserted into a socket manufactured in correspondence with electrode terminals of the IC chip, thereby electrically connecting the IC chip to a tester.
  • a testing method is used, in which the IC chip is electrically connected to the tester through test terminals called probe pins.
  • electrode terminals of an IC chip placed on a test table are graphically recognized using, e.g., a camera, and positioning is performed on the basis of this image information.
  • the operation time including an image recognition time is prolonged.
  • image recognition must be performed for each of the IC chips, a long positioning time is required and test efficiency of IC chips is degraded, resulting in inconvenience.
  • test efficiency of IC chips is intended to be improved using probe pins, a test efficiency improvement effect using the probe pins cannot be sufficiently enhanced.
  • the apparatus itself becomes expensive, and degradation of versatility may be caused.
  • the present invention has been made to solve the conventional problems described above, and has as its object to provide a method and apparatus for testing a semiconductor device with high test precision at a high apparatus throughput and a low apparatus cost.
  • test apparatus for a semiconductor device having first and second adjacent sides which form an angle therebetween, comprising:
  • testing means arranged at a test position
  • test table having a support surface for the semiconductor device, the test table having a reference position for testing the semiconductor device by the testing means and having a chucking position of the semiconductor device on the support surface;
  • fixing means arranged on the test table, for fixing the semiconductor device placed at the chucking position
  • driving means for accelerating and moving the test table within a plane parallel to the support surface, the driving means sliding the semiconductor device on the support surface by an inertia force during movement of the test table and positioning the semiconductor device at the chucking position by causing the first and second sides of the semiconductor element to abut against the first and second guide plates, respectively.
  • a testing method using the test apparatus of the first aspect comprising the steps of:
  • the driving means to move the test table so as to slide the semiconductor device on the support surface by the inertia force during movement, and causing the first and second sides of the semiconductor device to abut against the first and second guide plates, respectively, thereby positioning the semiconductor device at the chucking position;
  • testing the semiconductor device using the testing means is performed using the testing means.
  • the semiconductor device when the test table is moved while the semiconductor device is kept placed on the test table, the semiconductor device can be urged against the guide plates by the inertia force. The semiconductor device is thus positioned by the guide plates located at the predetermined positions. While the test table is moved and the semiconductor device is kept positioned, the semiconductor device is fixed, thereby accurate positioning is performed at high speed.
  • test apparatus In the test apparatus according to the present invention, high-precision positioning of a plurality of semiconductor devices can be simultaneously performed at high speed. Test precision can be improved, and the apparatus throughput can be increased. In addition, since no special positioning mechanism is required, an inexpensive apparatus can be obtained.
  • FIG. 1 is a schematic view showing an arrangement of a semiconductor test apparatus according to an embodiment of the present invention
  • FIG. 2 is a plan view of a test table used in the semiconductor test apparatus shown in FIG. 1;
  • FIG. 3 is a seotional side view of the test table shown in FIG. 2,
  • FIG. 4 is a view showing movement positions of the test table in positioning of the semiconductor device in a test method according to an embodiment of the present invention
  • FIG. 5 is a flow chart showing a semiconductor device test process together with the movement positions of FIG. 4 according to the test method of the present invention
  • FIG. 6 is a view showing one semiconductor device before positioning is performed in the test method of the present invention.
  • FIG. 7 is a view showing one semiconductor device after positioning is performed in the test method of the present invention.
  • FIG. 8 is a perspective view showing a movable stage in the apparatus shown in FIG. 1;
  • FIG. 9 is a plan view showing a test table as a whole after positioning according to the test method of the present invention.
  • FIG. 10 is a plan view showing a test table as a whole after positioning in a test method according to another embodiment of the present invention.
  • a semiconductor test apparatus of this embodiment has a test table 2 for supporting and holding a semiconductor device serving as a test object, e.g., a rectangular flat package semiconductor device or IC chip 1.
  • the test table 2 is placed on a stage 3 movable in the X-Y plane and is vertically movable and rotatable.
  • the test table 2 is movable in the X-Y-Z- ⁇ directions, in which movement of the test table 2 between the load/unload position and the test position of the IC chip 1 is performed in the X-Y plane.
  • the stage 3 comprises first to third bases 32, 36, and 42.
  • a pair of rails 34 are installed on the first base 32, and the second base 36 is supported on the rails 34 to be movable in the Y direction.
  • a pair of rails 38 are installed on the second base 36, and the third base 42 is supported on the rails 38 to be movable in the X direction.
  • a shaft 44 is arranged on the third base 42 to be vertically movable (Z direction) and rotatable ( ⁇ direction).
  • the test table 2 is fixed on an upper portion of the shaft 44.
  • a probe head 4 having test terminals such as probe pins 4a is arranged at a predetermined position above the test table 2.
  • the probe pins 4a are arranged in accordance with the layout of electrode terminals 1a of the IC chip 1 as a target object.
  • the probe head 4 is connected to a test head (not shown), and various electrical characteristics of the IC chip 1 are tested.
  • the test table 2 has a plurality (four) of chip holders 5.
  • Each chip holder 5 has a guide 6 corresponding to the shape of the IC chip 1.
  • This guide 6 has an internal size slightly larger than the outer size of the IC chip 1 and is constituted by four guide plates 6a to 6d respectively corresponding to the four sides of the IC chip 1.
  • the guide plates 6a and 6b of the four guide plates 6a to 6d define a chucking position for testing the IC chip 1.
  • a fixing means such as a vacuum pad 7 is formed inside the guide 6 of each chip holder 5.
  • a vacuum suction mechanism (not shown) is connected to the vacuum pad 7 to chuck and hold the IC chip 1.
  • the vacuum pad 7 is made of, for example, stainless steel, and its upper surface is finished with a mirror surface. By this mirror surface finishing, when the IC chip 1 is to be chucked, no gap is formed between the lower surface of the IC chip 1 and the upper surface of the vacuum pad. At the same time, sliding movement of the IC chip 1 on the vacuum pad 7 is facilitated.
  • the stage 3 is driven to move the test table 2 to the load/unload position (a position A) of the IC chip 1.
  • Each IC chip 1 is moved to a corresponding chip holder 5 on the test table 2 (step S101).
  • the vacuum suction mechanism is temporarily operated at this position, and each IC chip 1 is chucked and held (S102). Mounting of the IC chip 1 on each chip holder 5 is checked by a sensor (not shown) (S103).
  • the test table 2 is moved from the load/unload position (the position A) to the test position (a position D) below the probe head 4.
  • the following chip positioning is performed in this movement process.
  • test table 2 is moved (from the position A to a position B) in a negative direction with respect to a virtual corner constituted by the two adjacent guide plates 6a and 6b of the four guide plates 6a to 6d (S105).
  • the IC chips 1 When the IC chips 1 are initially mounted on the test table 2, the IC chips 1 are simply stored in the guides 6, respectively. Therefore, as shown in FIG. 6, the IC chips 1 are mounted at arbitrary positions within the guides 6, respectively.
  • the test table 2 is moved in the 45° direction (i.e., a direction indicated by an arrow M) at a predetermined speed, e.g., 0.1 m/sec to 1 m/sec while the IC chips 1 are simply placed (i.e., suction and holding are released), the IC chips 1 are slid on the corresponding vacuum pads 7 by an inertia force.
  • Each IC chip 1 is urged by the inertia force (i.e., the direction indicated by an arrow N) against the guide plates 6a and 6b which are located in a direction opposite to the movement direction and which form a right angle. Since in this state the two sides of each IC chip 1 are urged against the guide plates 6a and 6b defining the chucking position, the IC chip 1 is positioned at the chucking position, as shown in FIG. 7.
  • each IC chip 1 After each IC chip 1 is moved by a distance enough to perform the above positioning operation by the inertia force, the vacuum suction mechanism is operated during the movement (a position C), and the IC chip 1 is chucked and held by the corresponding vacuum pad 7 (S106). Positioning of each IC chip 1 is completed by the chucking and holding operations of the IC chip.
  • Suction of the IC chip 1 in step S106 can be performed during acceleration or during constant-speed movement after the acceleration as long as it is before the test table 2 is decelerated.
  • the IC chip 1 is preferably chucked during acceleration of the test table 2 because the IC chip 1 is firmly kept urged against the two guide plates 6a and 6b in this period.
  • the stage 3 is then temporarily stopped (S107) and the test table 2 is moved to a predetermined test position (i.e., from the position B to the position D) (S108).
  • a predetermined test position i.e., from the position B to the position D
  • the stage 3 is stopped (S109).
  • the test table 2 is moved upward at the position D, and the probe pins 4a of the probe head 4 are brought into contact with the corresponding electrode terminals 1a of the IC chip 1, and a predetermined test is performed (S110).
  • the plurality of IC chips 1 are sequentially tested by lifting the test table 2 each time the test table 2 is moved.
  • the IC chip 1 since the IC chip 1 is positioned such that the IC chip 1 is urged against the guide plates 6a and 6b by utilizing the inertia force generated by movement of the test table 2, a special positioning unit need not be arranged to perform high-speed positioning. Since positioning is performed using the inertia force, positioning can be simultaneously performed for the plurality of chip holders 5 arranged on the test table 2, as shown in FIG. 9. Therefore, the plurality of IC chips 1 can be accurately positioned with an inexpensive, simple arrangement, and the apparatus throughput can be increased with high testing precision.
  • the test table 2 is linearly moved substantially in a 45° direction to urge the IC chip 1 against the two guide plates 6a and 6b, thereby achieving positioning of the IC chip 1.
  • the moving direction of the IC chip is determined to generate vector components of a force for urging two sides of the IC chip against two guide plates.
  • the moving direction may be a 10° or 80° direction in the X-Y coordinate system of the stage 3.
  • the IC chip 1 can be positioned utilizing only rotation ( ⁇ direction) of the test table 2. In this case, as shown in FIG. 10, simultaneous positioning can be performed while the four IC chips 1 are urged against two outer guide plates by a centrifugal force.
  • a test method according to the present invention is not limited to a type in which probe pins are brought into contact with the electrode terminals of an IC chip.
  • the present invention is applicable to a test method of a type in which after an IC chip is positioned, the outer appearance of the chip is inspected using a camera.
  • a target test object according to the present invention is not limited to a packed IC chip. If a semiconductor device has two adjacent sides which form an angle and which can be utilized for positioning the semiconductor device, for example, a chip before packaging can be used as a target test object.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
US07/814,787 1991-01-16 1991-12-31 Semiconductor device testing apparatus with positioning mechanism Expired - Fee Related US5192908A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3003317A JPH04330753A (ja) 1991-01-16 1991-01-16 半導体検査装置及び半導体検査方法
JP3-3317 1991-01-16

Publications (1)

Publication Number Publication Date
US5192908A true US5192908A (en) 1993-03-09

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US07/814,787 Expired - Fee Related US5192908A (en) 1991-01-16 1991-12-31 Semiconductor device testing apparatus with positioning mechanism

Country Status (3)

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US (1) US5192908A (ko)
JP (1) JPH04330753A (ko)
KR (1) KR0155392B1 (ko)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629632A (en) * 1995-03-14 1997-05-13 Tokyo Electron Limited System for testing electric properties of an object
US5801527A (en) * 1994-07-26 1998-09-01 Tokyo Electron Limited Apparatus and method for testing semiconductor device
US6590406B2 (en) * 2000-10-16 2003-07-08 Soshotech Co., Ltd Apparatus for inspecting display board or circuit board
US20040205883A1 (en) * 2002-01-03 2004-10-21 Euclide Cecchin Method of molding a toilet seat assembly
US6864678B2 (en) 2002-07-17 2005-03-08 Delta Design, Inc. Nestless plunge mechanism for semiconductor testing
US20060220667A1 (en) * 2005-03-31 2006-10-05 Fujitsu Limited Testing device and testing method of a semiconductor device
US20100233964A1 (en) * 2006-02-09 2010-09-16 Rohde & Schwarz Gmbh & Co. Kg Test system for a circuit carrier
US20120311858A1 (en) * 2009-10-02 2012-12-13 Ers Electronic Gmbh Apparatus for conditioning semiconductor chips and test method using the apparatus
CN106705507A (zh) * 2015-11-17 2017-05-24 谢德音 冷媒配管装置
US20190056430A1 (en) * 2017-08-21 2019-02-21 Hermes-Epitek Corp. Plane correcting device and semiconductor testing apparatus including the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990086301A (ko) * 1998-05-27 1999-12-15 윤종용 고체 촬상 소자의 이물 검사영역 설정방법 및 설정장치
JP3388462B2 (ja) 1999-09-13 2003-03-24 日本電気株式会社 半導体チップ解析用プローバ及び半導体チップ解析装置
KR100756175B1 (ko) * 2006-01-25 2007-09-05 엘에스전선 주식회사 전자부품 이송장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936743A (en) * 1974-03-05 1976-02-03 Electroglas, Inc. High speed precision chuck assembly
US4758785A (en) * 1986-09-03 1988-07-19 Tektronix, Inc. Pressure control apparatus for use in an integrated circuit testing station
US4955590A (en) * 1988-12-08 1990-09-11 Tokyo Electron Limited Plate-like member receiving apparatus
US5010296A (en) * 1989-12-13 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Wafer prober
US5042421A (en) * 1989-07-25 1991-08-27 Manhattan R&D, Inc. Rotatable vacuum chuck with magnetic means

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936743A (en) * 1974-03-05 1976-02-03 Electroglas, Inc. High speed precision chuck assembly
US4066943A (en) * 1974-03-05 1978-01-03 Electroglas, Inc. High speed precision chuck assembly
US4758785A (en) * 1986-09-03 1988-07-19 Tektronix, Inc. Pressure control apparatus for use in an integrated circuit testing station
US4955590A (en) * 1988-12-08 1990-09-11 Tokyo Electron Limited Plate-like member receiving apparatus
US5042421A (en) * 1989-07-25 1991-08-27 Manhattan R&D, Inc. Rotatable vacuum chuck with magnetic means
US5010296A (en) * 1989-12-13 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Wafer prober

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5801527A (en) * 1994-07-26 1998-09-01 Tokyo Electron Limited Apparatus and method for testing semiconductor device
US5629632A (en) * 1995-03-14 1997-05-13 Tokyo Electron Limited System for testing electric properties of an object
US6590406B2 (en) * 2000-10-16 2003-07-08 Soshotech Co., Ltd Apparatus for inspecting display board or circuit board
US20040205883A1 (en) * 2002-01-03 2004-10-21 Euclide Cecchin Method of molding a toilet seat assembly
US6864678B2 (en) 2002-07-17 2005-03-08 Delta Design, Inc. Nestless plunge mechanism for semiconductor testing
US7129726B2 (en) * 2005-03-31 2006-10-31 Fujitsu Limited Testing device and testing method of a semiconductor device
US20060220667A1 (en) * 2005-03-31 2006-10-05 Fujitsu Limited Testing device and testing method of a semiconductor device
CN100388454C (zh) * 2005-03-31 2008-05-14 富士通株式会社 半导体器件的测试装置以及测试方法
US20100233964A1 (en) * 2006-02-09 2010-09-16 Rohde & Schwarz Gmbh & Co. Kg Test system for a circuit carrier
US9075085B2 (en) * 2006-02-09 2015-07-07 Rohde & Schwarz Gmbh & Co. Kg Test system for analyzing a circuit carrier
US20120311858A1 (en) * 2009-10-02 2012-12-13 Ers Electronic Gmbh Apparatus for conditioning semiconductor chips and test method using the apparatus
US9599662B2 (en) * 2009-10-02 2017-03-21 Ers Electronic Gmbh Apparatus for conditioning semiconductor chips and test method using the apparatus
CN106705507A (zh) * 2015-11-17 2017-05-24 谢德音 冷媒配管装置
US20190056430A1 (en) * 2017-08-21 2019-02-21 Hermes-Epitek Corp. Plane correcting device and semiconductor testing apparatus including the same

Also Published As

Publication number Publication date
KR0155392B1 (ko) 1998-12-01
JPH04330753A (ja) 1992-11-18
KR920015498A (ko) 1992-08-27

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