US4700114A - Vertical deflection circuit - Google Patents

Vertical deflection circuit Download PDF

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Publication number
US4700114A
US4700114A US06/852,358 US85235886A US4700114A US 4700114 A US4700114 A US 4700114A US 85235886 A US85235886 A US 85235886A US 4700114 A US4700114 A US 4700114A
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US
United States
Prior art keywords
deflection
voltage
capacitance
current
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06/852,358
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English (en)
Inventor
II Hugh F. Sutherland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Licensing Corp
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RCA Corp
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Filing date
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Application filed by RCA Corp filed Critical RCA Corp
Assigned to RCA CORPORATION reassignment RCA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SUTHERLAND, HUGH F. II
Priority to US06/852,358 priority Critical patent/US4700114A/en
Priority to FI871534A priority patent/FI83011C/fi
Priority to CA000534229A priority patent/CA1279724C/en
Priority to PT84644A priority patent/PT84644B/pt
Priority to EP87303081A priority patent/EP0242124B1/en
Priority to DE8787303081T priority patent/DE3772609D1/de
Priority to ES87303081T priority patent/ES2024506B3/es
Priority to AT90122496T priority patent/ATE111285T1/de
Priority to EP90122496A priority patent/EP0424982B1/en
Priority to ES90122496T priority patent/ES2059961T3/es
Priority to AT87303081T priority patent/ATE67054T1/de
Priority to AU71357/87A priority patent/AU597959B2/en
Priority to DE3750512T priority patent/DE3750512T2/de
Priority to KR1019870003543A priority patent/KR950005595B1/ko
Priority to DD87301855A priority patent/DD256220A5/de
Priority to JP62094243A priority patent/JP2872668B2/ja
Publication of US4700114A publication Critical patent/US4700114A/en
Application granted granted Critical
Assigned to RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP. OF DE reassignment RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP. OF DE ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: RCA CORPORATION, A CORP. OF DE
Priority to AU52055/90A priority patent/AU627003B2/en
Priority to CA000615748A priority patent/CA1290446C/en
Priority to CA000615747A priority patent/CA1290445C/en
Priority to SG122694A priority patent/SG122694G/en
Priority to HK173396A priority patent/HK173396A/xx
Priority to JP8247843A priority patent/JP2937888B2/ja
Priority to HK98103030A priority patent/HK1004045A1/xx
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/60—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth current is produced through an inductor
    • H03K4/69—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth current is produced through an inductor using a semiconductor device operating as an amplifier
    • H03K4/696—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth current is produced through an inductor using a semiconductor device operating as an amplifier using means for reducing power dissipation or for shortening the flyback time, e.g. applying a higher voltage during flyback time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
    • H04N3/23—Distortion correction, e.g. for pincushion distortion correction, S-correction
    • H04N3/233—Distortion correction, e.g. for pincushion distortion correction, S-correction using active elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/16—Picture reproducers using cathode ray tubes
    • H04N9/29—Picture reproducers using cathode ray tubes using demagnetisation or compensation of external magnetic fields

Definitions

  • This invention relates to deflection amplifier circuitry.
  • first and second output transistors are coupled together in a push-pull configuration at a deflection amplifier output terminal.
  • a vertical deflection winding in series with an S-shaping capacitor, is coupled to the output terminal.
  • a vertical rate, sawtooth input signal is coupled to the deflection amplifier to generate a sawtooth vertical deflection current in the deflection winding.
  • the top output transistor is conducting to generate the first half of the vertical deflection current and to charge the S-shaping capacitor from a DC voltage source.
  • the bottom output transistor is conducting to apply the S-capacitor voltage to the deflection winding for generating the second half of the vertical deflection current.
  • the S-shaping capacitor is discharged by the vertical deflection current through the bottom transistor. Except for a small overlap interval at the center of trace, the top output transistor is nonconductive when the bottom transistor is conductive.
  • DC negative feedback of the amplifier output voltage or of the S-capacitor voltage establishes correct DC biasing of the deflection amplifier.
  • the DC feedback increases conduction of the top output transistor to increase the charging current to the S-capacitor from the DC voltage source, thereby maintaining the proper DC operating point.
  • a fault operating condition may arise where the S-capacitor becomes short-circuited, decreasing the DC voltage at the amplifier output terminal to very low values.
  • the DC negative feedback loop tries to restore the DC output voltage by turning on the top output transistor to full or near full conduction in an attempt to recharge the S-capacitor from the DC voltage source via the vertical deflection winding.
  • Such fault mode operation may be undesirable in that excessive power dissipation may result in the top output device and in any current limiting resistor in series with the DC voltage source.
  • the large unidirectional current flowing in the deflection winding during fault mode operation may deflect the electron beams to such an extreme angle that they strike the picture tube neck, causing neck heating and possible tube breakage.
  • a feature of the invention is a vertical deflection circuit with amplifier drive circuitry that avoids such undesirable operation in a fault operating mode.
  • a deflection amplifier includes first and second transistor amplifier output stages.
  • a deflection winding is coupled to the first and second transistor amplifier output stages at a deflection amplifier output terminal.
  • An S-shaping capacitance is coupled to the deflection winding.
  • a source of deflection rate signals is coupled to the deflection amplifier for generating a deflection current in the deflection winding.
  • a base current generating circuit is coupled to one of the transistor amplifier output stages for providing base current thereto.
  • the base current generating circuit is coupled to the second terminal and has an S-capacitance voltage applied thereto for enabling the conduction of the base current.
  • a main charging path of the S-capacitance is provided via the top output stage of a deflection amplifier arranged in a push-pull configuration.
  • a second, slower charging path for the S-capacitance is also provided which bypasses the top output stage. Conduction of base current to the top output stage is enabled only when the S-capacitance voltage is greater than a predetermined magnitude.
  • the main charging path is disabled.
  • the second charging path charges the S-capacitor to the voltage level needed to enable operation of the top output device.
  • a start-up delay is provided to operation of the vertical deflection circuit. The start-up delay enables picture tube degaussing to be completed before vertical deflection current is generated. This prevents the vertical deflection magnet field from undesirably affecting the degaussing process.
  • a degaussing circuit is responsive to an on-off switch for providing degaussing action during a degaussing interval initiated when the on-off switch is switched to an on position.
  • a vertical deflection circuit includes a vertical deflection winding and a capacitor in which capacitor there is developed a vertical rate voltage during steady-state operation that controls the generation of vertical deflection current in the vertical deflection winding.
  • a DC power supply generates a DC supply voltage that energizes the deflection circuit. The DC power supply is responsive to the on-off switch to generate the DC supply voltage after the on-off switch is switched to the on position.
  • the DC supply voltage attains a level adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval.
  • a means for charging the capacitor from the DC power supply is provided that charges the capacitor after the on-off switch is switched to the on position at a sufficiently slow rate to delay the generation of vertical deflection current pass the conclusion of the degaussing interval.
  • FIGS. 1 and 2 illustrate two different inventive embodiments of a vertical deflection circuit
  • FIG. 3 illustrates a video display apparatus, embodying the invention, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing.
  • a vertical deflection amplifier 30 comprises output transistor stages Q1 and Q2 coupled together in a push-pull configuration at an amplifier output terminal 22.
  • a vertical deflection winding L V is coupled to terminal 22.
  • An S-capacitor C1 is coupled to deflection winding L V at a second terminal 21 remote from output terminal 22.
  • a current sampling resistor R12 is coupled between the lower terminal of capacitor C1 and ground.
  • the collector of bottom output transistor Q2 is coupled to the base of top output transistor Q1 via a resistor R4 and a diode D4 to form a totem-pole configuration, wherein base drive for top transistor Q1 is shunted through bottom transistor Q2.
  • a resistor R8 is coupled between output terminal 22 and the collector of transistor Q2 to reduce crossover distortion.
  • a diode D3 parallels resistor R8 and becomes conductive during the second half of vertical trace to shunt current away from resistor R8 at large deflection current amplitudes during the second half of trace. This reduces overall power dissipation during the second half of vertical trace and enables a lower DC operating point to be selected for output terminal 22.
  • a +24 V supply source is coupled to the collector of transistor Q1 via a small current limiting resistor R6 and a diode D5.
  • the control circuitry for deflection amplifier 30 includes a vertical sawtooth generator 23 that develops a vertical rate sawtooth voltage V3 that is AC coupled to the noninverting input terminal of a driver amplifier U1 via a capacitor C4 and a resistor R13.
  • a reference voltage V REF is coupled to the inverting input terminal.
  • the output of driver U1 is coupled to the base of bottom transistor Q2 via resistor R9 of biasing resistors R9 and R14.
  • a base current generating circuit 40 generates a base current i1 for top output transistor Q1.
  • Base current generating circuit 40 includes a bootstrap capacitor C2 having a lower terminal coupled to amplifier output terminal 22 at the emitter of transistor Q1 and an upper terminal coupled to the junction of a diode D1 and a resistor R3. Resistor R3 is coupled to the base of transistor Q1.
  • Bootstrap capacitor C2 is charged by a current i c2 flowing from terminal 21 via a relatively small valued resistor R2 and diode D1.
  • the value of current i c2 is established in accordance with the S-capacitor voltage V1 established at terminal 21.
  • voltage V1 is a vertical rate parabola voltage, skewed downwardly by the superimposed sawtooth voltage V s developed across sampling resistor R12.
  • output transistor Q1 is conducting a positive vertical deflection current i V to charge S-capacitor C1 from the +24 V supply via resistor R6 and diode D5.
  • Bootstrap capacitor C2 provides the forward base current for transistor Q1 during the early portions of vertical trace.
  • deflection amplifier output voltage V2 developed at terminal 22 is sufficiently greater than S-capacitance voltage V1 to reverse bias diode D1 and prevent the recharging of bootstrap capacitor C2.
  • the decreasing, positive sawtooth portion of vertical deflection current i V during the first half of vertical trace is produced as a result of the decreasing conduction of top output transistor Q1.
  • the upwardly ramping sawtooth input voltage V3 is amplified by driver U1 to increase the conduction of bottom output transistor Q2, thereby increasing the amount of current shunted away from the base of transistor Q1 via resistor R4 and diode D4.
  • transistor Q2 shunts enough base current i1 to cutoff conduction in output transistor Q1.
  • S-capacitor voltage V1 drives vertical deflection current i V in the negative direction via transistor Q2.
  • Amplifier U1 increases the conduction of transistor Q2 as the second half of vertical trace progresses to generate the negative portion of the downwardly ramping vertical deflection current.
  • output voltage V2 is a downwardly ramping voltage.
  • S-capacitor voltage V1 has increased and output voltage V2 has decreased to values which enable diode D1 to become forward biased.
  • bootstrap capacitor C2 is recharged by current i c2 to the S-capacitor voltage V1.
  • S-capacitor terminal 21 sources currents i c2 and i1.
  • deflection current i V flows into terminal 21 and is large enough to be the main source for current i c2 .
  • S-capacitor C1 becomes the main source for current i c2 .
  • the AC sawtooth sampling voltage V s developed across current sampling resistor R12, is summed via a resistor R11 with the 180° out-of-phase sawtooth input voltage V3 at the noninverting input terminal of amplifier U1.
  • S-capacitor voltage V1 developed at terminal 21, is DC coupled to the noninverting input terminal of driver U1 via a resistor R10.
  • a negative feedback loop is formed from output terminal 22 that includes deflection winding L v , terminal 21, driver amplifier U1 and bottom output transistor Q2. Should, for example, S-capacitor voltage V1 tend to decrease, this decrease in voltage is applied to driver U1 to decease conduction of transistor Q2. Conduction in transistor Q1 is increased to recharge capacitor C1 to its stabilized average value.
  • sawtooth input voltage V3 abruptly decreases, producing the cutoff of bottom output transistor Q2 at the end of trace.
  • a resonant retrace interval is initiated that charges a transistor Q2 becomes cutoff, output voltage V2 begins to increase due to the inductive kick provided by deflection winding L V .
  • Voltage V2 forward biases a retrace diode D2 coupled between the base and emitter electrodes of transistor Q1, and forward biases the base-collector diode of transistor Q1.
  • Deflection current i V flows via retrace diode D2 and reverse base-collector conduction into retrace capacitor C3 and the +24 volt supply. Deflection current i V begins to rapidly ramp up during retrace.
  • bootstrap capacitor C2 is discharged by deflection current i V via reverse collector conduction of transistor Q1.
  • deflection current i V ramps up during retrace through its zero current value, the inductive action of deflection winding L V decreases output voltage V2 at the emitter of transistor Q1 by an amount that enables diode D2 to become reverse biased.
  • Bootstrap capacitor C2 begins to discharge into the base of top output transistor Q1, maintaining the transistor in saturated conduction throughout the remainder of the retrace interval.
  • the positive retrace deflection current i V has increased to a value that enables sawtooth sampling voltage V s to reestablish drive to bottom output transistor Q2, thereby initiating the subsequent vertical trace interval.
  • bottom device Q2 With bottom device Q2 conducting, a shunt path is established for current i1 that bypasses the base of transistor Q1, bringing the transistor out of saturation into the linear mode of operation.
  • Capacitor C3 becomes discharged very early within trace by conduction of transistor Q1, after which time diode D5 becomes forward biased.
  • resistor R7 One terminal of a resistor R7 is coupled to a +131 V DC voltage supply of value greater than the +24 V supply.
  • the other terminal of resistor R7 is coupled to the junction of the collector of transistor Q1 and retrace capacitor C3.
  • a resistor R5 is coupled across retrace capacitor C3.
  • capacitor C3 is precharged to a voltage level that is established by voltage dividing resistors R7 and R5, coupled between the +131 V voltage source and the +24 V voltage source, in accordance with the RC time constant associated with the resistors and capacitor C3.
  • the precharged voltage on retrace capacitor C3 at the end of trace provides a more rapid retrace of vertical deflection current i V , thereby shortening the duration of retrace interval T r .
  • S-capacitor voltage V1 is applied to base current generating circuit 40 independently of the DC stabilizing negative feedback loop, to enable the generation of current i1 when the S-capacitor voltage V1 exceeds a predetermined magnitude.
  • Base current generating circuit 40 is dependent on S-capacitance voltage V1 as a DC voltage supply source. Should the magnitude of S-capacitance voltage V1 decrease below the predetermined magnitude, base current generating circuit 40 will be unable to generate adequate current i1 to maintain top output transistor Q1 in conduction. The main charging path for S-capacitor C1 is via top output transistor Q1. When base current generating circuit 40 is unable to supply base current to maintain transistor Q1 conductive, this main charging path will be disabled.
  • an auxiliary or second charging path for capacitor C1 is provided directly to a DC voltage supply, bypassing the main charging path of top output transistor Q1 and the vertical deflection winding L V .
  • a relatively large valued resistor R1 is coupled from a +30 V supply to S-capacitor terminal 21.
  • An auxiliary charging current i 0 flows from the +30 V supply via resistor R1 to S-capacitor terminal 21.
  • S-capacitor C1 When the television receiver is first turned on, S-capacitor C1 is initially in a discharged state. When the power supply for the television receiver generates the DC supply voltages such as the +24 V, +30 V and +131 V voltages, S-capacitor C1 begins to charge with current i 0 from the +30 V supply via resistor R1. Due to the relatively large value of S-capacitor C1, voltage V1 remains below the predetermined magnitude required during start-up for enabling base current generating circuit 40. During this substantial start-up delay interval, transistor Q1 remains essentially cutoff, disabling the main charging path for capacitor C1 via deflection winding L V .
  • auxiliary charging current i 0 is determined by the difference in voltage between the +30 V supply and the steady-state value of S-capacitor voltage V1.
  • the DC component of current i 0 flows into terminal 21 from the +30 V supply.
  • component values such as the value of resistor R3, the DC component of the current flowing in the current path (R2, D1, R3) equals the DC component of current i 0 .
  • no net DC current flows in deflection winding L V from resistor R1.
  • the difference current will flow as a DC component in vertical deflection current i V .
  • This difference current is of relatively small value and may be eliminated, if so desired, by proper adjustment of a DC centering control circuit for deflection winding L V , not illustrated in FIG. 1.
  • the start-up delay time for the generation of vertical deflection current is approximately one to two seconds.
  • the start-up delay advantageously permits completion of picture tube degaussing before the generation of vertical deflection current, thereby avoiding any undesirable interaction between the vertical deflection magnetic field and the degaussing process.
  • FIG. 3 illustrates a portion of a video display apparatus 60, embodying an aspect of the invention, that includes a picture tube degaussing circuit 10 and vertical deflection circuit 20 of FIG. 1, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing.
  • Vertical deflection circuit 20 of FIG. 1 is shown in FIG. 3 in partial detail only.
  • an AC mains supply developing a voltage V AC , energizes a DC power supply 16 when an on-off switch 15 is closed, or switched to the on-position.
  • DC power supply 16 develops various DC supply voltages for the circuitry of video display apparatus 60 including a +DC1, a +DC2, a +DC3 and a +DC4 voltage.
  • Voltage +DC4 for example, energizes a horizontal deflection circuit 17 to generate horizontal deflection current in a horizontal deflection winding L H .
  • Degaussing circuit 10 includes a degaussing coil DG located adjacent a picture tube 50 of video display apparatus 60.
  • Degaussing coil DG is coupled in series with a positive temperature coefficient thermistor 13, AC mains supply 14 and the mechanical switch portion of an electro-mechanical relay 11.
  • the mechanical switch portion of relay 11 is normally open when the relay coil is deengerized.
  • on-off switch 15 is closed to permit DC power supply 16 to develop the DC supply voltages, including the +DC1 supply voltage.
  • the +DC1 supply voltage is coupled via a charging capacitor 12 to the coil of relay 11.
  • thermistor 13 self-heats by the degaussing current, its resistance increases producing a decaying alternating degaussing current that reaches a very low residual amplitude, bringing the degaussing interval to a conclusion.
  • the decaying alternating degaussing current produces a decaying alternating degaussing magnetic field that degausses the shadow mask, magnetic shield and other magnetizable material associated with picture tube 50, but not illustrated in FIG. 3.
  • series capacitor 12 charges to the +DC1 supply level, preventing current from flowing in the coil of relay 11.
  • the mechanical switch portion of relay 11 returns to its normally opened position to eliminate the flow of even a residual current in degaussing coil DG after conclusion of the degaussing interval.
  • the DC supply voltages developed by power supply 16 are rapidly developed from a zero voltage level after on-off switch 15 is closed.
  • the DC supply voltages developed for vertical deflection circuit 20 attain levels adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval.
  • capacitor C1 whose voltage V1 controls operation of vertical deflection circuit 20, disables base current generator 40 to prevent the generation of vertical deflection current in vertical deflection winding L V immediately after on-off switch 15 is closed.
  • Capacitor C1 is slowly charged from the +DC3 supply via resistor R1 to delay the enablement of base current generator 40 and thus to delay the generation of vertical deflection current until after conclusion of the degaussing interval. This delay avoids any undesirable interaction between the vertical deflection magnetic field and the degaussing process.
  • FIG. 2 illustrates a vertical deflection circuit 120, embodying the invention, similar to the vertical deflection circuit of FIG. 1, but modified to reduce any net DC current that may flow through deflection winding L V from auxiliary charging current i 0 .
  • Items in FIGS. 1 and 2 similarly identified represent similar elements or quantities.
  • a controllable impedance a transistor Q3, is interposed between base current generating circuit 40 and the +30 V supply, with the collector of the transistor coupled to the +30 V supply and the emitter coupled to resistor R2.
  • the base of transistor Q3 is coupled to S-capacitor terminal 21 at the junction of charging resistor R1 and S-capacitor C1.
  • the S-capacitor voltage V1 controls the conductivity of transistor Q3 and the amount of current flowing in the collector circuit of transistor Q3 to base generating circuit 40.
  • transistor Q3 becomes cutoff, disconnecting the +30 V supply from base current generating circuit 40, and disabling the generation of current i1 into the base of top output transistor Q1.
  • transistor Q3 is cutoff to disable top output transistor Q1.
  • the auxiliary charging current i 0 charges capacitor C1 after a start-up delay to the value needed to turn on transistor Q3 for enabling base current generating circuit 40. Because of the gain provided by transistor Q3, charging current i 0 may be relatively small, and the net DC current component introduced into deflection winding L V by current i 0 is negligible.

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  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Engineering & Computer Science (AREA)
  • Video Image Reproduction Devices For Color Tv Systems (AREA)
  • Details Of Television Scanning (AREA)
  • Professional, Industrial, Or Sporting Protective Garments (AREA)
  • Golf Clubs (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
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US06/852,358 1986-04-15 1986-04-15 Vertical deflection circuit Expired - Lifetime US4700114A (en)

Priority Applications (23)

Application Number Priority Date Filing Date Title
US06/852,358 US4700114A (en) 1986-04-15 1986-04-15 Vertical deflection circuit
FI871534A FI83011C (fi) 1986-04-15 1987-04-08 Vertikal avlaenkningskrets.
CA000534229A CA1279724C (en) 1986-04-15 1987-04-08 Vertical deflection circuit
PT84644A PT84644B (pt) 1986-04-15 1987-04-08 Circuito de deflexao vertical
DE3750512T DE3750512T2 (de) 1986-04-15 1987-04-09 Vertikalablenkschaltung.
DE8787303081T DE3772609D1 (de) 1986-04-15 1987-04-09 Vertikal-ablenkschaltung.
ES87303081T ES2024506B3 (es) 1986-04-15 1987-04-09 Circuito de deflexion vertical.
AT90122496T ATE111285T1 (de) 1986-04-15 1987-04-09 Vertikalablenkschaltung.
EP90122496A EP0424982B1 (en) 1986-04-15 1987-04-09 Vertical deflection circuit
ES90122496T ES2059961T3 (es) 1986-04-15 1987-04-09 Circuito de deflexion vertical.
AT87303081T ATE67054T1 (de) 1986-04-15 1987-04-09 Vertikal-ablenkschaltung.
AU71357/87A AU597959B2 (en) 1986-04-15 1987-04-09 Deflection circuit
EP87303081A EP0242124B1 (en) 1986-04-15 1987-04-09 Vertical deflection circuit
KR1019870003543A KR950005595B1 (ko) 1986-04-15 1987-04-14 편향회로 및 이를 이용한 비데오표시장치의 수직편향회로
JP62094243A JP2872668B2 (ja) 1986-04-15 1987-04-15 偏向回路
DD87301855A DD256220A5 (de) 1986-04-15 1987-04-15 Vertikalablenkschaltung
AU52055/90A AU627003B2 (en) 1986-04-15 1990-03-20 Deflection and degaussing circuit
CA000615747A CA1290445C (en) 1986-04-15 1990-05-24 Vertical deflection circuit
CA000615748A CA1290446C (en) 1986-04-15 1990-05-24 Vertical deflection circuit
SG122694A SG122694G (en) 1986-04-15 1994-08-24 Vertical deflection circuit
HK173396A HK173396A (en) 1986-04-15 1996-09-12 Vertical deflection circuit
JP8247843A JP2937888B2 (ja) 1986-04-15 1996-09-19 偏向回路
HK98103030A HK1004045A1 (en) 1986-04-15 1998-04-14 Vertical deflection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/852,358 US4700114A (en) 1986-04-15 1986-04-15 Vertical deflection circuit

Publications (1)

Publication Number Publication Date
US4700114A true US4700114A (en) 1987-10-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
US06/852,358 Expired - Lifetime US4700114A (en) 1986-04-15 1986-04-15 Vertical deflection circuit

Country Status (14)

Country Link
US (1) US4700114A (es)
EP (2) EP0242124B1 (es)
JP (2) JP2872668B2 (es)
KR (1) KR950005595B1 (es)
AT (2) ATE67054T1 (es)
AU (2) AU597959B2 (es)
CA (1) CA1279724C (es)
DD (1) DD256220A5 (es)
DE (2) DE3772609D1 (es)
ES (2) ES2059961T3 (es)
FI (1) FI83011C (es)
HK (2) HK173396A (es)
PT (1) PT84644B (es)
SG (1) SG122694G (es)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857805A (en) * 1987-05-11 1989-08-15 U.S. Philips Corporation Picture display device with stray field compensation means
US5276782A (en) * 1989-06-29 1994-01-04 Hughes Aircraft Company Display corrector
US5526221A (en) * 1992-10-16 1996-06-11 Goldstar Electron Co., Ltd. Degaussing circuit
US5541805A (en) * 1993-01-15 1996-07-30 Philips Electronics North America Corporation Time delay control switch for vertical deflection in television receiver
US5629696A (en) * 1992-06-05 1997-05-13 Canon Kabushiki Kaisha Parallel to serial data converter

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JPH0583720A (ja) * 1991-09-20 1993-04-02 Sony Corp Ｃｒｔ装置
DE4138493A1 (de) * 1991-11-23 1993-05-27 Thomson Brandt Gmbh Schaltung zur entmagnetisierung der bildroehre in einen fernsehempfaenger

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US4857805A (en) * 1987-05-11 1989-08-15 U.S. Philips Corporation Picture display device with stray field compensation means
US5276782A (en) * 1989-06-29 1994-01-04 Hughes Aircraft Company Display corrector
US5629696A (en) * 1992-06-05 1997-05-13 Canon Kabushiki Kaisha Parallel to serial data converter
US5526221A (en) * 1992-10-16 1996-06-11 Goldstar Electron Co., Ltd. Degaussing circuit
US5541805A (en) * 1993-01-15 1996-07-30 Philips Electronics North America Corporation Time delay control switch for vertical deflection in television receiver

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KR870010727A (ko) 1987-11-30
FI871534A (fi) 1987-10-16
CA1279724C (en) 1991-01-29
FI83011B (fi) 1991-01-31
HK1004045A1 (en) 1998-11-13
FI871534A0 (fi) 1987-04-08
EP0424982B1 (en) 1994-09-07
EP0424982A3 (en) 1992-05-13
JPH09130821A (ja) 1997-05-16
ES2024506B3 (es) 1992-03-01
AU627003B2 (en) 1992-08-13
AU5205590A (en) 1990-07-19
DE3750512T2 (de) 1995-04-13
JP2937888B2 (ja) 1999-08-23
AU597959B2 (en) 1990-06-14
DE3750512D1 (de) 1994-10-13
DD256220A5 (de) 1988-04-27
ATE67054T1 (de) 1991-09-15
PT84644B (pt) 1989-11-30
FI83011C (fi) 1991-05-10
ATE111285T1 (de) 1994-09-15
DE3772609D1 (de) 1991-10-10
JP2872668B2 (ja) 1999-03-17
JPS62250771A (ja) 1987-10-31
AU7135787A (en) 1987-10-22
EP0424982A2 (en) 1991-05-02
KR950005595B1 (ko) 1995-05-27
EP0242124A1 (en) 1987-10-21
SG122694G (en) 1995-01-13
HK173396A (en) 1996-09-20
PT84644A (en) 1987-05-01
ES2059961T3 (es) 1994-11-16
EP0242124B1 (en) 1991-09-04

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