CA1290445C - Vertical deflection circuit - Google Patents
Vertical deflection circuitInfo
- Publication number
- CA1290445C CA1290445C CA000615747A CA615747A CA1290445C CA 1290445 C CA1290445 C CA 1290445C CA 000615747 A CA000615747 A CA 000615747A CA 615747 A CA615747 A CA 615747A CA 1290445 C CA1290445 C CA 1290445C
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- capacitor
- deflection
- current
- voltage
- vertical deflection
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Abstract
Abstract A vertical deflection amplifier of a video display apparatus includes first and second transistor amplifier output stages arranged in a totem-pole, push-pull configuration. A vertical deflection winding is coupled to the output stages at a deflection amplifier output terminal. An S-capacitor is coupled to the deflection winding at a second terminal remote from the output terminal. A source of deflection rate signals is coupled to the deflection amplifier for generating a deflection current in the deflection winding. A base current generating circuit is coupled to one of the transistor amplifier output stages for providing base current thereto.
The S-capacitor voltage is applied to the base current generating circuit for enabling conduction of base current in the one amplifier output stage. When the video display apparatus is first turned on, the initially discharged S-capacitor is slowly charged from a DC voltage supply to delay generation of vertical deflection past completion of picture tube degaussing.
The S-capacitor voltage is applied to the base current generating circuit for enabling conduction of base current in the one amplifier output stage. When the video display apparatus is first turned on, the initially discharged S-capacitor is slowly charged from a DC voltage supply to delay generation of vertical deflection past completion of picture tube degaussing.
Description
~2~B44~5 RCA 8 3 , 2 1 6 B
VERTICAL DEFLECTION CIRCUIT
This application is a division of Canadian Application Serial No. 534,2~9, filed April 8, 1987.
This invention relates to deflection amplifier circuitry.
In a typical linearly operated vertical deflection circuit, first and second output transistors are coupled together in a push-pull configuration at a deflection amplifier output terminal. A vertical deflection winding, in series with an S-shaping capacitor, is coupled to the output texminal. A vertical rate, sawtooth input signal is coupled to the deflection amplifier to generate a sawtooth vertical deflection current in the deflection winding.
During the first half of vertical trace, the top output transistor is conducting to generate the first half of the vertical deflection current and to charge the S-shaping capacitor from a DC voltage source. During the second half of vertical trace, the bottom output transistor is conducting to apply the S-capacitor voltage to the deflection winding for generating the second half of the vertical deflection current.
The S-shaping capacitor is discharged by the vertical deflection current through the bottom transistor. Except for a small overlap interval at the center of trace, the top output transistor is nonconductive when the bottom transistor is conductive.
DC negative feedback of the amplifier output voltage or of the S-capacitor voltage establishes correct DC biasing of the deflection amplifier. Thus, for example, should the S-capacitor voltage tend to decreaæe~ the DC feedback increases conduction of the top output transistor to increase the charging current to the S-capacitor from the DC voltage source, thereby maintaining the proper DC operating point.
A fault operating condition may arise if the S-capacitor becomes short-circuited, decreasing the DC
voltage at the amplifier output terminal to a very low value. The DC negative feedback loop tries to restore the DC
output voltage by turning on the top output transistor ~' ..
~9044!~5 -2- RCA 83,216B
to full or near full conduction in an attempt to recharge the S-capacitor from the DC voltage source via the vertical deflection winding.
Such fault mode operation may be undesirable in that excessive power dissipation may result in the top output device and in any current limiting resistor in series with the DC voltage source. Furthermore, the large unidirectional current flowing in the deflection winding during fault mode operation, may deflect the electron beams to such an extreme angle that they strike the picture tube neck, causing neck heating and possible tube breakage.
A feature of the invention is a vertical deflection circuit with amplifier drive circuitry that avoids such undesirable operation in a fault operating mode. A deflection amplifier includes first and second transistor amplifier output stages. A deflection winding is coupled to the first and second transistor amplifier output stages at a deflection amplifier output terminal.
An S-shaping capacitance is coupled to the deflection winding. A source of deflection rate signals is coupled to the deflection amplifier for generating a deflection current in the deflection winding. A base current generating circuit is coupled to one of the translstor amplifier output stages for providing base current thereto.
The base current generating circuit is coupled to the second terminal and has an S-capacitance voltage applied thereto for enabling the conduction of the base current.
In carrying out an aspect of the invention, a main charging path of the S-capacitance is provided via the top output stage of a deflection amplifier arranged in a push-pull configuration. A second, slower charging path for the S-capacitance is also provided which bypasses the top output stage. Conduction of base current to the top output stage is enabled only when the S-capacitance voltage is greater than a predetermined magnitude.
During start-up, when the S-capacitance is initially discharged, the main charging path is disabled.
9~5 _3_ RCA 83,216B
The second charging path charyes the S capacitor to the voltage level needed to enable operation of the top output device. By proper selection of the charging rate in the second charging path, a start-up delay is provided to operation of the ver~ical deflection circuit. The start-up delay enables picture tube degaussing to be completed before vertical deflection current is generated. This prevents the vertical deflection magnetic field from undesirably affecting the degaussing process.
In accordance with another inventi~e feature, a degaussing circuit is responsive to an on-off switch for providing degaussing action during a degaussing interval initiated when the on-off switch is switched to an "on"
position. A vertical deflection circuit includes a vertical deflection winding and a capacitor, in which capacitor there is developed a vertical rate voltage during steady-state operation that controls the generation of vertical deflection current in the vertical deflection winding. A DC power supply generates a DC supply voltage that energizes the deflection circuit. The DC power supply is responsive to the on-off switch to generate the DC
supply voltage after the on-off switch ls switched to the "on" position. The DC supply voltage attains a level adequate to energize the vertical deflection circu t prior to the conclusion of the degaussing interval. A means for charging the capacitor from the DC power supply is provided, that charges the capacitor after the on-off switch is switched to the "on" position at a sufficiently slow rate to delay the generation of vertical deflection current pass the conclusion of the degaussing interval.
In the Drawing:
FIGURES 1 and 2 illustrate two different inventive embodiments of a vertical deflection circult; and FIGURE 3 illus-trates a video display apparatus, embodying the invention, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing.
~;~9~14~,5 _4_ RCA 83,216B
In vertical deflection circuit 20 of FIGURE l, a vertical deflection amplifier 30 comprlses output transistor stages Ql and Q2 coupled together in a push-pull configuration at an amplifier output terminal Z2. A
vertical deflection winding ~ is coupled to terminal 22.
An S-capacitor Cl is coupled to deflection winding LV at a second terminal 21 remote from output terminal 22. A
current sampling resistor R12 is coupled between the lower terminal of capacitor Cl and ground.
The collector of bottom output transistor Q2 is coupled to the base of top output transistor Q1 via a resistor R4 and a diode D4 to form a totem-pole configuration, wherein base drive for top transistor Q1 is shunted through bottom transistor Q2. A resistor R8 is coupled between output terminal 22 and the collector of transistor Q2 to reduce crossover distortion. A diode D3 parallels resistor R8 and becomes conductive during the second half of vertical trace to shunt current away from resistor R8 at large deflection current amplitudes during the second half of trace. This reduces.overall power dissipation during the second half of vertical trace and enables a lower DC operating point to be selected for output terminal 2Z. A +24V supply source is coupled to the collector of transistor Q1 via a small current limiting resistor R6 and a diode D5.
The control circuitry for deflection amplifier 30 includes a vertical sawtooth generator 23 that develops a vertical rate sawtooth voltage V3 that is AC coupled to the noninverting input terminal of a driver amplifier U1 via a capacitor C4 and a resistor R13. A reference voltage VREF
is coupled to the inverting input terminal. ~he output of driver U1 is coupled to the base of bottom transistor Q2 via resistor R9 of biasing resistors R9 and R14.
A base current generating circuit 40, embodying an aspect of the invention, generates a base current il for top output transistor Q1. Base current generating circult 40 includes a bootstrap capacitor C2 having a lower .
12904~S
_5_ RCA 83,216B
terminal coupled to amplifier output terminal 22 at the emitter of transistor Ql and an upper terminal coupled to the junction of a diode D1 and a resistor R3. Resistor R3 is coupled to the base of translstor Q1. Bootstrap S capacitor C2 is charged by a current iC2 flowing from terminal 21 via a relatively small valued resistor R2 and diode D1. The value of current iC2 is established in accordance with the S-capacitor voltage V1 established at terminal 21. During normal steady-state deflection circuit operation, voltage V1 is a vertical rate parabola voltage, skewed downwardly by the superimposed sawtooth voltage Vs developed across sampling resistor R12.
At the beginning portion of the vertical trace interval Tt, output transistor Q1 is conducting a positive vertical deflection current 1V to charge S-capacitox C1 from the +24V supply via resistor R6 and diode D5.
Bootstrap capacitor C2 provides the forward base current for transistor Q1 during the early portions of vertical trace. Near the beginning of vertical trace, deflection amplifier output voltage V2 developed at terminal 22 is sufficiently greater than S-capacitance voltage V1 to reverse bias diode D1 and prevent the recharging of bootstrap capacitor C2.
The decreasing, positive sawtooth portion of vertical deflection current iv during the first half of vertical trace is produced as a result of the decreasing conduction of top output transistor Q1. In the totem-pole deflection amplifier arrangement, the upwardly ramping sawtooth input voltage V3 is amplified by driver U1 to increase the conduction of bottom output transistor Q2, thereby increasing the amoun-t of current shunted away from the base of transistor Q1 via reslstor R4 and diode D4. At some point near the center of vertical trace, transistor Q2 shunts enough base current il to cut off conduction in output transistor Q1.
During the second half of vertical trace, with transistor Q2 conductive, S-capacitor voltage V1 drives vertical deflection current iv in the negative direction ~2~ s -6- RCA 83,216~
via transistor Q2. Amplifier U1 lncreases the conductlon of transistor Q2 as the second half of vertical trace progresses, to generate the negative portion of the downwardly ramping vertical deflection current.
During the vertical trace interval Tt, output voltage V2 is a downwardly ramping voltage. At some instant after the center of trace, S-capacitor voltage Vl has increased and output voltage V2 has decreased to values which enable diode D1 to become forward biased. At this time, bootstrap capacitor C2 is recharged by current iC2 to the S-capacltor voltage V1. With diode D1 conducting, S-capacitor terminal 21 sources currents iC2 and il.
When diode D1 first begins conducting after the center of vertical trace, deflection current iv flows into terminal 21 from S-capacitor C1, and is large enough to be the main source for current iC2. Near the center of trace and during the second half of trace, S-capacitor Cl becomes the main source fox current iC2.
To maintain scan linearity, the AC sawtooth Z0 sampling voltage Vs, developed across current sampling resistor R12, is summed via a resistor Rll with the 180 out-of-phase sawtooth input voltage V3 at the noninvertlng input termlnal of amplifier U1.
To stabilize the DC operating point of output terminal 22 at a predetermined average value, S-capacltor voltage V1, developed at terminal 21, is DC coupled to the noninverting input terminal of driver U1 via a resistor Rl0. A negative feedback loop is formed from output terminal 22, that includes deflection winding Lv, terminal 21, driver amplifier U1 and bottom output transistor Q2.
Should, for example, S-capacitor voltage V1 tend to decrease, this decrease in voltage is applied to driver U1 to decrease conduction of transistor Q2. Conduction in transistor Ql is increased to recharge capacitor C1 to its stabilized average value.
To initiate the vertical retrace lnterval Tr, sawtooth input voltage V3 abruptly decreases, producing the cutoff of bottom output transistor Q2 at the end of ~race.
4~15 _7 RCA 83,216B
A resonant retrace interval is initiated that charges a retrace capacitor C3 coupled across diode D5. When transistor Q2 becomes cut off, output voltage V2 beglns to increase due to the inductive kick provided by deflec~ion winding ~. Voltage V2 forward biases a retrace diode D2 coupled between the base and emitter electrodes of transistor Q1, and forward biases the base-collector path of transistor Q1. Deflection current iv flows via retrace diode D~ and reverse base collector conduction into retrace capacitor C3 and the +24 volt supply. Deflection current iV begins to rapidly ramp up during retrace.
During retrace, when deflection current iv is negative, bootstrap capacitor C2 is discharged by deflection current iv via reverse collector conduction of transistor Ql. When deflection current iv ramps up during retrace through its zero current value, the inductive action of deflection winding LV decreases output voltage V2 at the emitter of transistor Q1 by an amount that enables diode D2 to become reverse biased. Bootstrap capacitor C2 begins to discha~ge into the base of top output transistor Ql, maintaining the transistor in saturated conduction throughout the remainder of the retrace interval.
At the end of vertical retrace, the positive retrace deflection current iv has increased to a value that enables sawtooth sampling voltage Vs to reestablish drive to bottom output transistor Q2, thereby initiating the subsequent vertical trace interval. With bottom device Q2 conducting, a shunt path is established for current il that bypasses the base of transistor Ql, bringing the transistor out of saturation into the linear mode of operation.
At the end of vertical retrace, some voltage remains in retrace capacitor C3. Capacitor C3 becomes discharged very early within trace by conduction of transistor Q1, after which time diode D5 becomes forward biased.
one terminal of a resistor R7 is coupled to a +131V DC voltage supply of value greater than the +24V
supply. The other terminal of resistor R7 is coupled to the ~0445 -8 RCA 83,216B
junction of the collector of transistor Q1 and retrace capacitor C3. A reslstor R5 is coupled across retrace capacitor C3. During the second half of vertical trace, when transistor Q1 is cut of~, capacitor C3 is precharged to a voltage level that is established by voltage dividing resistors R7 and R5, coupled between the +131V voltage source and the +24V voltage source, ln accordance with the RC time constant associated with the resistors and capacitor C3. The precharged voltage on retrace capacitor C3 at the end of trace provides a more rapid retrace of vertical deflection current iv, thereby shortening the duration of retrace interval Tr.
In accordance with an aspect of the invention, S-capacitor voltage V1 is applied to base current generating circuit 40 independently of the DC stabilizlng negative feedback loop, to enable the generation of current il when the S-capacitor voltage V1 exceeds a predetermined magnitude.
Base current generating circuit 40 is dependent on S-capacitance voltage V1 as a DC voltage supply source.
Should the magnitude of S-capacltance voltage V1 decrease below the predetermined magnitude, base current generating circuit 40 will be unable to generate adequate current il to maintain top output transistor Q1 in conduction. The main charging path for S-capacitor C1 is via top output transistor Q1. When base current generating circuit 40 is unable to supply base current to maintain transistor Q1 conductive, this main charging path will be disabled.
Under certain fault operating situations, it may be desirable for the fault to trigger the disabling of base current generating circuit 40 and of the main charging path to capacitor C1. Such a situation may arise, for example, if S-capacitor Cl becomes short-circuited. When S-capacitor Cl becomes short-circuited, voltage V1 will tend to decrease to zero. The DC negative feedback loop via resistor R10 tries to maintain voltage V1 at its stabilized value by turning bottom output transistor Q2 off, in an attempt to maintain transistor Q1 conducting ua~5 -9- RCA 83,216B
heavily. If base current generating circuit 40 were not disabled in such a situation, large current would flow in the main charging path to the now short-circuited S-capacitor via deflection winding ~, transistor Q1, diode D5 and resistor R6. Excessive dissipation and possible component failure would result. Furthermore, the large unidirectional current flowing in deflection winding LV
would deflect the electron beams of the picture tube by a large angle, permitting the electron beams to strike and possibly damage the neck of the picture tube.
In accordance with an aspect of the invention, when the S-capacitor voltage decreases below a predetermined magnitude, such as may occur when the S-capacitor becomes short-circuited, voltage V1 becomes too low to provide forward bias to diode D1. Bootstrap capacitor C2 becomes disconnected from its source of charging current, disabling the generation of current il into the base of top output transistor Q1. Without base current, transistor Q1 becomes nonconductive, disabling the main charging path into the short-circuit of capacitor C1, thereby avoiding undesirable short-circuit fault operation of vertical deflection circuit 20.
In accordance with another aspect of the invention, an auxiliary or second charging path for capacitor Cl is provided directly to a DC voltage supply, bypassing the main charging path of top output transistor Ql and the vertical deflection winding Lv. A relatively large valued resistor Rl is coupled from a +30V supply to S-capacitor terminal 21. An auxiliary charging current io flows from the +30V supply via resistor Rl to S-capacitor terminal 21.
When the television recelver is first turned on, S-capacitor Cl is initially in a discharged state. When the power supply for the television receiver generates the DC supply voltages such as the +24V, +30V and +131V
voltages, S-capacitor Cl begins to charge with current io from the +30V supply via resistor R1. Due to the relatively large value of S-capacitor Cl, voltage V1 ~;~9~S
-10- ~CA 83,216B
remains below the predetermined magnitude required during start-up for enabling base current generatlng circuit 40.
During this substantial start-up delay intexval, transistor Ql remains essentially cutoff, disabling the main charging path for capacitor C1 via deflection winding Lv.
When the television receiver is first turned on, the discharged S-capacitor C1 slowly beyins to charge with current io from the +30V supply. Voltage Vl begins to increase as Cl charges. As long as voltage V1 is below its normal steady-state value, the DC negati~e feedback loop maintains transistor Q2 cutoff. No significant current path to ground exists by which bootstrap capacitor C2 may charge.
When S-capacitor C1 has charged sufficiently to permit voltage V1 to increase to approximately or slightly greater than its normal, steady-state value, the DC
negative feedback loop turns on transistor Q2, enabling bootstrap capacitor C2 to charge to a value which is capable of forward biasing transistor Q1. Soon afterwards, normal steady-state deflection circuit operation commences.
During steady-state operation, the value of auxiliary charging current io is determined by the difference in voltage between ~he ~30V supply and the steady-state value of S-capacitor voltage V1. The DC
component of current io flows into terminal 21 from the +30V supply. By proper selection of component values, such as the value of resistor R3, the DC component of the current flowing in the current path (R2, D1, R3) equals the DC component of current io~ In this situation, no net DC
current flows in deflection winding LV from resistor Rl.
If the DC component of current il differs from the DC
component of current io~ the difference current will flow as a DC component in vertical deflection current iv. This difference current is of relatively small value and may be eliminated, if so desired, by proper adjustment of a DC
centering control circuit for deflection winding Lv, not illustrated in FIGURE 1.
~l290~ 5 RCA ~3 3, 2 1 6 B
For the values given in the circuit of FIGURE 1, the start-up delay time for the generation of vertical deflection current is approxlmately one to two seconds.
The start-up delay advantageously permits completion of picture tube degaussing before the generatlon of vertlcal deflection current, thereby avoiding any undeslrable interaction between the vertical deflection magnetic field and the degaussing process.
FIGURE 3 illustrates a portion of a video display apparatus 60, embodying an aspect of the invention, that includes a picture tube degaussing circuit 10 and vertical deflection circuit 20 of FIGURE 1, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing. Vertical deflection circuit 20 of FIGURE 1 is shown in FIGURE 3 in partial detail only.
In FIGURE 1, an AC mains supply, developing a voltage VAc, energizes a DC power supply 16 when an on-off switch 15 is conductive, or switched to the on-position.
DC power supply 16 develops various DC supply voltages for the circuitry of video display apparatus 60 including a +DCl, a +DC2, a +DC3 and a +DC4 voltage. Voltage +DC4, for example, energizes a horizontal deflection circuit 17 to generate horizontal deflection current in a horizontal deflection winding ~.
Degaussing circuit 10 includes a degaussing coil DG located adjacent a picture tube 50 of video display apparatus 60. Degaussing coil DG is coupled in series with a positive temperature coefficient thermistor 13, AC mains supply 14 and the mechanical switch portion of an electro-mechanical degaussing relay 11. The mechanical switch portion of relay 11 is normally non-conductive when the relay coil is deengerized, To initiate a degaussing interval, when degaussing action takes place, on-off switch 15 is made conductive to permit DC power supply 16 to develap the DC
supply voltages, including the +DCl supply voltage. The +DC1 supply voltage is coupled via a charging capacitor 12 to the coil of relay 11. Current flows in the relay coil 9~ 5 -12- RCA 83,216B
from the +DC1 supply, energlzlng the relay coil and closing the mechanical switch portion of degaussing relay 11. With the mechanical switch portion of r~lay 11 conductive, AC
degaussing current flows from AC mains supply 14 in degaussing coil DG and thermistor 13 at the frequency of AC
mains voltage VAc. As thermistor 13 self-heats by the degaussing current, its resistance increases producing a decaying alternating degaussing current that reaches a very low residual amplitude, bringing the degaussing interval to a conclusion. The decaying alternating degaussing current produces a decaying alternating degaussing magnetic field that degausses the shadow mask, magnetic shield and other magnetizable material associated with picture tube 50, but not illustrated in FIGURE 3. After conclusion of the degaussing interval, series capacitor 12 charges to the +DCl supply level, preventing current from flowing in the coil of relay 11. The mechanical switch portion of relay 11 returns to its normally non-conductive posltion to eliminate the flow of even a residual current in degaussing coil DG after conclusion of the degaussing interval.
The DC supply voltages developed by power supply 16 are rapidly developed from a zero voltage level after on-off switch 15 is made conductive. In particular, the DC
supply voltages developed for vertical deflection circuit 20 attain levels adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval.
Advantageously, however, capacitor Cl, whose voltage V1 controls operation of vertical deflectlon circuit 20, disables base current generator 40 to prevent the generation of vertical deflection current in vertical deflection winding LV immediately after on-off switch 15 is closed. Capacitor C1 is slowly charged from the ~DC3 supply via resistor Rl to delay the enablement of base current generating circuit 40 and thus to delay the generation of vertical deflection current until after conclusion of the degaussing interval. This delay avoids ~904~5 -13- RC~ 83,216B
any undesirable interaction between the vertical deflection magnetic field and the degaussing process.
FIGURE 2 illustrates a vertical deflection circuit 120, embodying the invention, similar to the S vertical deflection circuit of F~GURE 1, but modified to reduce any net DC current that may flow through deflection winding ~ from auxiliary charging current io. Items in FIGURES 1 and 2 similarly identified represent similar elements or quantities.
In FIGURE 2, a controllable impedance, a transistor Q3, is interposed between base current generating circuit 40 and the +30V supply, with the collector of the transistor coupled to the +30V supply and the emitter coupled to resistor R2. The base of transistor Q3 is coupled to S-capacitor second terminal 21 at the junction of charging resistor R1 and S-capacitor C1. The S-capacitor voltage V1 controls the conductivity of transistor Q3 and the amount of current flowing ln the collector circuit of transistor Q3 to base current generating circuit 40.
Should capacitor Cl become short-circuited and voltage V1 decrease to near zero, transistor Q3 becomes cut off, disconnecting the +30V supply from base current generating circuit 40, and disabling the generation of current il into the base of top output transistor Q1.
Similarly during start-up, because capacitor C1 is initially discharged, transistor Q3 is cut off to disable top output translstor Q1. The auxiliary charging current io charges capacitor C1 after a start-up delay to the value needed to turn on transistor Q3 for enabling base current generating circuit 40. Because of the gain provided by transistor Q3, charging current io may be relatively small, and the net DC current component introduced into deflection winding ~ by current io is negligible.
VERTICAL DEFLECTION CIRCUIT
This application is a division of Canadian Application Serial No. 534,2~9, filed April 8, 1987.
This invention relates to deflection amplifier circuitry.
In a typical linearly operated vertical deflection circuit, first and second output transistors are coupled together in a push-pull configuration at a deflection amplifier output terminal. A vertical deflection winding, in series with an S-shaping capacitor, is coupled to the output texminal. A vertical rate, sawtooth input signal is coupled to the deflection amplifier to generate a sawtooth vertical deflection current in the deflection winding.
During the first half of vertical trace, the top output transistor is conducting to generate the first half of the vertical deflection current and to charge the S-shaping capacitor from a DC voltage source. During the second half of vertical trace, the bottom output transistor is conducting to apply the S-capacitor voltage to the deflection winding for generating the second half of the vertical deflection current.
The S-shaping capacitor is discharged by the vertical deflection current through the bottom transistor. Except for a small overlap interval at the center of trace, the top output transistor is nonconductive when the bottom transistor is conductive.
DC negative feedback of the amplifier output voltage or of the S-capacitor voltage establishes correct DC biasing of the deflection amplifier. Thus, for example, should the S-capacitor voltage tend to decreaæe~ the DC feedback increases conduction of the top output transistor to increase the charging current to the S-capacitor from the DC voltage source, thereby maintaining the proper DC operating point.
A fault operating condition may arise if the S-capacitor becomes short-circuited, decreasing the DC
voltage at the amplifier output terminal to a very low value. The DC negative feedback loop tries to restore the DC
output voltage by turning on the top output transistor ~' ..
~9044!~5 -2- RCA 83,216B
to full or near full conduction in an attempt to recharge the S-capacitor from the DC voltage source via the vertical deflection winding.
Such fault mode operation may be undesirable in that excessive power dissipation may result in the top output device and in any current limiting resistor in series with the DC voltage source. Furthermore, the large unidirectional current flowing in the deflection winding during fault mode operation, may deflect the electron beams to such an extreme angle that they strike the picture tube neck, causing neck heating and possible tube breakage.
A feature of the invention is a vertical deflection circuit with amplifier drive circuitry that avoids such undesirable operation in a fault operating mode. A deflection amplifier includes first and second transistor amplifier output stages. A deflection winding is coupled to the first and second transistor amplifier output stages at a deflection amplifier output terminal.
An S-shaping capacitance is coupled to the deflection winding. A source of deflection rate signals is coupled to the deflection amplifier for generating a deflection current in the deflection winding. A base current generating circuit is coupled to one of the translstor amplifier output stages for providing base current thereto.
The base current generating circuit is coupled to the second terminal and has an S-capacitance voltage applied thereto for enabling the conduction of the base current.
In carrying out an aspect of the invention, a main charging path of the S-capacitance is provided via the top output stage of a deflection amplifier arranged in a push-pull configuration. A second, slower charging path for the S-capacitance is also provided which bypasses the top output stage. Conduction of base current to the top output stage is enabled only when the S-capacitance voltage is greater than a predetermined magnitude.
During start-up, when the S-capacitance is initially discharged, the main charging path is disabled.
9~5 _3_ RCA 83,216B
The second charging path charyes the S capacitor to the voltage level needed to enable operation of the top output device. By proper selection of the charging rate in the second charging path, a start-up delay is provided to operation of the ver~ical deflection circuit. The start-up delay enables picture tube degaussing to be completed before vertical deflection current is generated. This prevents the vertical deflection magnetic field from undesirably affecting the degaussing process.
In accordance with another inventi~e feature, a degaussing circuit is responsive to an on-off switch for providing degaussing action during a degaussing interval initiated when the on-off switch is switched to an "on"
position. A vertical deflection circuit includes a vertical deflection winding and a capacitor, in which capacitor there is developed a vertical rate voltage during steady-state operation that controls the generation of vertical deflection current in the vertical deflection winding. A DC power supply generates a DC supply voltage that energizes the deflection circuit. The DC power supply is responsive to the on-off switch to generate the DC
supply voltage after the on-off switch ls switched to the "on" position. The DC supply voltage attains a level adequate to energize the vertical deflection circu t prior to the conclusion of the degaussing interval. A means for charging the capacitor from the DC power supply is provided, that charges the capacitor after the on-off switch is switched to the "on" position at a sufficiently slow rate to delay the generation of vertical deflection current pass the conclusion of the degaussing interval.
In the Drawing:
FIGURES 1 and 2 illustrate two different inventive embodiments of a vertical deflection circult; and FIGURE 3 illus-trates a video display apparatus, embodying the invention, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing.
~;~9~14~,5 _4_ RCA 83,216B
In vertical deflection circuit 20 of FIGURE l, a vertical deflection amplifier 30 comprlses output transistor stages Ql and Q2 coupled together in a push-pull configuration at an amplifier output terminal Z2. A
vertical deflection winding ~ is coupled to terminal 22.
An S-capacitor Cl is coupled to deflection winding LV at a second terminal 21 remote from output terminal 22. A
current sampling resistor R12 is coupled between the lower terminal of capacitor Cl and ground.
The collector of bottom output transistor Q2 is coupled to the base of top output transistor Q1 via a resistor R4 and a diode D4 to form a totem-pole configuration, wherein base drive for top transistor Q1 is shunted through bottom transistor Q2. A resistor R8 is coupled between output terminal 22 and the collector of transistor Q2 to reduce crossover distortion. A diode D3 parallels resistor R8 and becomes conductive during the second half of vertical trace to shunt current away from resistor R8 at large deflection current amplitudes during the second half of trace. This reduces.overall power dissipation during the second half of vertical trace and enables a lower DC operating point to be selected for output terminal 2Z. A +24V supply source is coupled to the collector of transistor Q1 via a small current limiting resistor R6 and a diode D5.
The control circuitry for deflection amplifier 30 includes a vertical sawtooth generator 23 that develops a vertical rate sawtooth voltage V3 that is AC coupled to the noninverting input terminal of a driver amplifier U1 via a capacitor C4 and a resistor R13. A reference voltage VREF
is coupled to the inverting input terminal. ~he output of driver U1 is coupled to the base of bottom transistor Q2 via resistor R9 of biasing resistors R9 and R14.
A base current generating circuit 40, embodying an aspect of the invention, generates a base current il for top output transistor Q1. Base current generating circult 40 includes a bootstrap capacitor C2 having a lower .
12904~S
_5_ RCA 83,216B
terminal coupled to amplifier output terminal 22 at the emitter of transistor Ql and an upper terminal coupled to the junction of a diode D1 and a resistor R3. Resistor R3 is coupled to the base of translstor Q1. Bootstrap S capacitor C2 is charged by a current iC2 flowing from terminal 21 via a relatively small valued resistor R2 and diode D1. The value of current iC2 is established in accordance with the S-capacitor voltage V1 established at terminal 21. During normal steady-state deflection circuit operation, voltage V1 is a vertical rate parabola voltage, skewed downwardly by the superimposed sawtooth voltage Vs developed across sampling resistor R12.
At the beginning portion of the vertical trace interval Tt, output transistor Q1 is conducting a positive vertical deflection current 1V to charge S-capacitox C1 from the +24V supply via resistor R6 and diode D5.
Bootstrap capacitor C2 provides the forward base current for transistor Q1 during the early portions of vertical trace. Near the beginning of vertical trace, deflection amplifier output voltage V2 developed at terminal 22 is sufficiently greater than S-capacitance voltage V1 to reverse bias diode D1 and prevent the recharging of bootstrap capacitor C2.
The decreasing, positive sawtooth portion of vertical deflection current iv during the first half of vertical trace is produced as a result of the decreasing conduction of top output transistor Q1. In the totem-pole deflection amplifier arrangement, the upwardly ramping sawtooth input voltage V3 is amplified by driver U1 to increase the conduction of bottom output transistor Q2, thereby increasing the amoun-t of current shunted away from the base of transistor Q1 via reslstor R4 and diode D4. At some point near the center of vertical trace, transistor Q2 shunts enough base current il to cut off conduction in output transistor Q1.
During the second half of vertical trace, with transistor Q2 conductive, S-capacitor voltage V1 drives vertical deflection current iv in the negative direction ~2~ s -6- RCA 83,216~
via transistor Q2. Amplifier U1 lncreases the conductlon of transistor Q2 as the second half of vertical trace progresses, to generate the negative portion of the downwardly ramping vertical deflection current.
During the vertical trace interval Tt, output voltage V2 is a downwardly ramping voltage. At some instant after the center of trace, S-capacitor voltage Vl has increased and output voltage V2 has decreased to values which enable diode D1 to become forward biased. At this time, bootstrap capacitor C2 is recharged by current iC2 to the S-capacltor voltage V1. With diode D1 conducting, S-capacitor terminal 21 sources currents iC2 and il.
When diode D1 first begins conducting after the center of vertical trace, deflection current iv flows into terminal 21 from S-capacitor C1, and is large enough to be the main source for current iC2. Near the center of trace and during the second half of trace, S-capacitor Cl becomes the main source fox current iC2.
To maintain scan linearity, the AC sawtooth Z0 sampling voltage Vs, developed across current sampling resistor R12, is summed via a resistor Rll with the 180 out-of-phase sawtooth input voltage V3 at the noninvertlng input termlnal of amplifier U1.
To stabilize the DC operating point of output terminal 22 at a predetermined average value, S-capacltor voltage V1, developed at terminal 21, is DC coupled to the noninverting input terminal of driver U1 via a resistor Rl0. A negative feedback loop is formed from output terminal 22, that includes deflection winding Lv, terminal 21, driver amplifier U1 and bottom output transistor Q2.
Should, for example, S-capacitor voltage V1 tend to decrease, this decrease in voltage is applied to driver U1 to decrease conduction of transistor Q2. Conduction in transistor Ql is increased to recharge capacitor C1 to its stabilized average value.
To initiate the vertical retrace lnterval Tr, sawtooth input voltage V3 abruptly decreases, producing the cutoff of bottom output transistor Q2 at the end of ~race.
4~15 _7 RCA 83,216B
A resonant retrace interval is initiated that charges a retrace capacitor C3 coupled across diode D5. When transistor Q2 becomes cut off, output voltage V2 beglns to increase due to the inductive kick provided by deflec~ion winding ~. Voltage V2 forward biases a retrace diode D2 coupled between the base and emitter electrodes of transistor Q1, and forward biases the base-collector path of transistor Q1. Deflection current iv flows via retrace diode D~ and reverse base collector conduction into retrace capacitor C3 and the +24 volt supply. Deflection current iV begins to rapidly ramp up during retrace.
During retrace, when deflection current iv is negative, bootstrap capacitor C2 is discharged by deflection current iv via reverse collector conduction of transistor Ql. When deflection current iv ramps up during retrace through its zero current value, the inductive action of deflection winding LV decreases output voltage V2 at the emitter of transistor Q1 by an amount that enables diode D2 to become reverse biased. Bootstrap capacitor C2 begins to discha~ge into the base of top output transistor Ql, maintaining the transistor in saturated conduction throughout the remainder of the retrace interval.
At the end of vertical retrace, the positive retrace deflection current iv has increased to a value that enables sawtooth sampling voltage Vs to reestablish drive to bottom output transistor Q2, thereby initiating the subsequent vertical trace interval. With bottom device Q2 conducting, a shunt path is established for current il that bypasses the base of transistor Ql, bringing the transistor out of saturation into the linear mode of operation.
At the end of vertical retrace, some voltage remains in retrace capacitor C3. Capacitor C3 becomes discharged very early within trace by conduction of transistor Q1, after which time diode D5 becomes forward biased.
one terminal of a resistor R7 is coupled to a +131V DC voltage supply of value greater than the +24V
supply. The other terminal of resistor R7 is coupled to the ~0445 -8 RCA 83,216B
junction of the collector of transistor Q1 and retrace capacitor C3. A reslstor R5 is coupled across retrace capacitor C3. During the second half of vertical trace, when transistor Q1 is cut of~, capacitor C3 is precharged to a voltage level that is established by voltage dividing resistors R7 and R5, coupled between the +131V voltage source and the +24V voltage source, ln accordance with the RC time constant associated with the resistors and capacitor C3. The precharged voltage on retrace capacitor C3 at the end of trace provides a more rapid retrace of vertical deflection current iv, thereby shortening the duration of retrace interval Tr.
In accordance with an aspect of the invention, S-capacitor voltage V1 is applied to base current generating circuit 40 independently of the DC stabilizlng negative feedback loop, to enable the generation of current il when the S-capacitor voltage V1 exceeds a predetermined magnitude.
Base current generating circuit 40 is dependent on S-capacitance voltage V1 as a DC voltage supply source.
Should the magnitude of S-capacltance voltage V1 decrease below the predetermined magnitude, base current generating circuit 40 will be unable to generate adequate current il to maintain top output transistor Q1 in conduction. The main charging path for S-capacitor C1 is via top output transistor Q1. When base current generating circuit 40 is unable to supply base current to maintain transistor Q1 conductive, this main charging path will be disabled.
Under certain fault operating situations, it may be desirable for the fault to trigger the disabling of base current generating circuit 40 and of the main charging path to capacitor C1. Such a situation may arise, for example, if S-capacitor Cl becomes short-circuited. When S-capacitor Cl becomes short-circuited, voltage V1 will tend to decrease to zero. The DC negative feedback loop via resistor R10 tries to maintain voltage V1 at its stabilized value by turning bottom output transistor Q2 off, in an attempt to maintain transistor Q1 conducting ua~5 -9- RCA 83,216B
heavily. If base current generating circuit 40 were not disabled in such a situation, large current would flow in the main charging path to the now short-circuited S-capacitor via deflection winding ~, transistor Q1, diode D5 and resistor R6. Excessive dissipation and possible component failure would result. Furthermore, the large unidirectional current flowing in deflection winding LV
would deflect the electron beams of the picture tube by a large angle, permitting the electron beams to strike and possibly damage the neck of the picture tube.
In accordance with an aspect of the invention, when the S-capacitor voltage decreases below a predetermined magnitude, such as may occur when the S-capacitor becomes short-circuited, voltage V1 becomes too low to provide forward bias to diode D1. Bootstrap capacitor C2 becomes disconnected from its source of charging current, disabling the generation of current il into the base of top output transistor Q1. Without base current, transistor Q1 becomes nonconductive, disabling the main charging path into the short-circuit of capacitor C1, thereby avoiding undesirable short-circuit fault operation of vertical deflection circuit 20.
In accordance with another aspect of the invention, an auxiliary or second charging path for capacitor Cl is provided directly to a DC voltage supply, bypassing the main charging path of top output transistor Ql and the vertical deflection winding Lv. A relatively large valued resistor Rl is coupled from a +30V supply to S-capacitor terminal 21. An auxiliary charging current io flows from the +30V supply via resistor Rl to S-capacitor terminal 21.
When the television recelver is first turned on, S-capacitor Cl is initially in a discharged state. When the power supply for the television receiver generates the DC supply voltages such as the +24V, +30V and +131V
voltages, S-capacitor Cl begins to charge with current io from the +30V supply via resistor R1. Due to the relatively large value of S-capacitor Cl, voltage V1 ~;~9~S
-10- ~CA 83,216B
remains below the predetermined magnitude required during start-up for enabling base current generatlng circuit 40.
During this substantial start-up delay intexval, transistor Ql remains essentially cutoff, disabling the main charging path for capacitor C1 via deflection winding Lv.
When the television receiver is first turned on, the discharged S-capacitor C1 slowly beyins to charge with current io from the +30V supply. Voltage Vl begins to increase as Cl charges. As long as voltage V1 is below its normal steady-state value, the DC negati~e feedback loop maintains transistor Q2 cutoff. No significant current path to ground exists by which bootstrap capacitor C2 may charge.
When S-capacitor C1 has charged sufficiently to permit voltage V1 to increase to approximately or slightly greater than its normal, steady-state value, the DC
negative feedback loop turns on transistor Q2, enabling bootstrap capacitor C2 to charge to a value which is capable of forward biasing transistor Q1. Soon afterwards, normal steady-state deflection circuit operation commences.
During steady-state operation, the value of auxiliary charging current io is determined by the difference in voltage between ~he ~30V supply and the steady-state value of S-capacitor voltage V1. The DC
component of current io flows into terminal 21 from the +30V supply. By proper selection of component values, such as the value of resistor R3, the DC component of the current flowing in the current path (R2, D1, R3) equals the DC component of current io~ In this situation, no net DC
current flows in deflection winding LV from resistor Rl.
If the DC component of current il differs from the DC
component of current io~ the difference current will flow as a DC component in vertical deflection current iv. This difference current is of relatively small value and may be eliminated, if so desired, by proper adjustment of a DC
centering control circuit for deflection winding Lv, not illustrated in FIGURE 1.
~l290~ 5 RCA ~3 3, 2 1 6 B
For the values given in the circuit of FIGURE 1, the start-up delay time for the generation of vertical deflection current is approxlmately one to two seconds.
The start-up delay advantageously permits completion of picture tube degaussing before the generatlon of vertlcal deflection current, thereby avoiding any undeslrable interaction between the vertical deflection magnetic field and the degaussing process.
FIGURE 3 illustrates a portion of a video display apparatus 60, embodying an aspect of the invention, that includes a picture tube degaussing circuit 10 and vertical deflection circuit 20 of FIGURE 1, wherein start-up of the vertical deflection circuit is delayed until after completion of degaussing. Vertical deflection circuit 20 of FIGURE 1 is shown in FIGURE 3 in partial detail only.
In FIGURE 1, an AC mains supply, developing a voltage VAc, energizes a DC power supply 16 when an on-off switch 15 is conductive, or switched to the on-position.
DC power supply 16 develops various DC supply voltages for the circuitry of video display apparatus 60 including a +DCl, a +DC2, a +DC3 and a +DC4 voltage. Voltage +DC4, for example, energizes a horizontal deflection circuit 17 to generate horizontal deflection current in a horizontal deflection winding ~.
Degaussing circuit 10 includes a degaussing coil DG located adjacent a picture tube 50 of video display apparatus 60. Degaussing coil DG is coupled in series with a positive temperature coefficient thermistor 13, AC mains supply 14 and the mechanical switch portion of an electro-mechanical degaussing relay 11. The mechanical switch portion of relay 11 is normally non-conductive when the relay coil is deengerized, To initiate a degaussing interval, when degaussing action takes place, on-off switch 15 is made conductive to permit DC power supply 16 to develap the DC
supply voltages, including the +DCl supply voltage. The +DC1 supply voltage is coupled via a charging capacitor 12 to the coil of relay 11. Current flows in the relay coil 9~ 5 -12- RCA 83,216B
from the +DC1 supply, energlzlng the relay coil and closing the mechanical switch portion of degaussing relay 11. With the mechanical switch portion of r~lay 11 conductive, AC
degaussing current flows from AC mains supply 14 in degaussing coil DG and thermistor 13 at the frequency of AC
mains voltage VAc. As thermistor 13 self-heats by the degaussing current, its resistance increases producing a decaying alternating degaussing current that reaches a very low residual amplitude, bringing the degaussing interval to a conclusion. The decaying alternating degaussing current produces a decaying alternating degaussing magnetic field that degausses the shadow mask, magnetic shield and other magnetizable material associated with picture tube 50, but not illustrated in FIGURE 3. After conclusion of the degaussing interval, series capacitor 12 charges to the +DCl supply level, preventing current from flowing in the coil of relay 11. The mechanical switch portion of relay 11 returns to its normally non-conductive posltion to eliminate the flow of even a residual current in degaussing coil DG after conclusion of the degaussing interval.
The DC supply voltages developed by power supply 16 are rapidly developed from a zero voltage level after on-off switch 15 is made conductive. In particular, the DC
supply voltages developed for vertical deflection circuit 20 attain levels adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval.
Advantageously, however, capacitor Cl, whose voltage V1 controls operation of vertical deflectlon circuit 20, disables base current generator 40 to prevent the generation of vertical deflection current in vertical deflection winding LV immediately after on-off switch 15 is closed. Capacitor C1 is slowly charged from the ~DC3 supply via resistor Rl to delay the enablement of base current generating circuit 40 and thus to delay the generation of vertical deflection current until after conclusion of the degaussing interval. This delay avoids ~904~5 -13- RC~ 83,216B
any undesirable interaction between the vertical deflection magnetic field and the degaussing process.
FIGURE 2 illustrates a vertical deflection circuit 120, embodying the invention, similar to the S vertical deflection circuit of F~GURE 1, but modified to reduce any net DC current that may flow through deflection winding ~ from auxiliary charging current io. Items in FIGURES 1 and 2 similarly identified represent similar elements or quantities.
In FIGURE 2, a controllable impedance, a transistor Q3, is interposed between base current generating circuit 40 and the +30V supply, with the collector of the transistor coupled to the +30V supply and the emitter coupled to resistor R2. The base of transistor Q3 is coupled to S-capacitor second terminal 21 at the junction of charging resistor R1 and S-capacitor C1. The S-capacitor voltage V1 controls the conductivity of transistor Q3 and the amount of current flowing ln the collector circuit of transistor Q3 to base current generating circuit 40.
Should capacitor Cl become short-circuited and voltage V1 decrease to near zero, transistor Q3 becomes cut off, disconnecting the +30V supply from base current generating circuit 40, and disabling the generation of current il into the base of top output transistor Q1.
Similarly during start-up, because capacitor C1 is initially discharged, transistor Q3 is cut off to disable top output translstor Q1. The auxiliary charging current io charges capacitor C1 after a start-up delay to the value needed to turn on transistor Q3 for enabling base current generating circuit 40. Because of the gain provided by transistor Q3, charging current io may be relatively small, and the net DC current component introduced into deflection winding ~ by current io is negligible.
Claims
RCA 83,216B
The embodiments of the invention in which a exclusive property or privilege is claimed are defined as follows:
1. A vertical deflection circuit of a video display apparatus with start-up of the vertical deflection circuit being delayed until after completion of degaussing, comprising:
an on-off switch;
a degaussing circuit responsive to said on-off switch for providing degaussing action during a degaussing interval initiated when said on-off switch is switched to an on-position;
a vertical deflection circuit including a vertical deflection winding and a capacitor in which capacitor there is developed a vertical rate voltage during steady state operation that controls the generation of vertical deflection current in said deflection winding;
a DC power supply for generating a DC
supply voltage that energizes said deflection circuit, said DC power supply being responsive to said on-off switch to generate said DC supply voltage after said on-off switch is switched to the on-position, said DC
supply voltage attaining a level adequate to energize said vertical deflection circuit prior to inclusion of said degaussing interval; and means for charging said capacitor from said power supply, after said on-off switch is switched to the on-position, at a sufficiently slow rate to delay the generation of said vertical deflection current past the conclusion of said degaussing interval.
The embodiments of the invention in which a exclusive property or privilege is claimed are defined as follows:
1. A vertical deflection circuit of a video display apparatus with start-up of the vertical deflection circuit being delayed until after completion of degaussing, comprising:
an on-off switch;
a degaussing circuit responsive to said on-off switch for providing degaussing action during a degaussing interval initiated when said on-off switch is switched to an on-position;
a vertical deflection circuit including a vertical deflection winding and a capacitor in which capacitor there is developed a vertical rate voltage during steady state operation that controls the generation of vertical deflection current in said deflection winding;
a DC power supply for generating a DC
supply voltage that energizes said deflection circuit, said DC power supply being responsive to said on-off switch to generate said DC supply voltage after said on-off switch is switched to the on-position, said DC
supply voltage attaining a level adequate to energize said vertical deflection circuit prior to inclusion of said degaussing interval; and means for charging said capacitor from said power supply, after said on-off switch is switched to the on-position, at a sufficiently slow rate to delay the generation of said vertical deflection current past the conclusion of said degaussing interval.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/852,358 US4700114A (en) | 1986-04-15 | 1986-04-15 | Vertical deflection circuit |
| CA000534229A CA1279724C (en) | 1986-04-15 | 1987-04-08 | Vertical deflection circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000534229A Division CA1279724C (en) | 1986-04-15 | 1987-04-08 | Vertical deflection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1290445C true CA1290445C (en) | 1991-10-08 |
Family
ID=25671304
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000615748A Expired - Lifetime CA1290446C (en) | 1986-04-15 | 1990-05-24 | Vertical deflection circuit |
| CA000615747A Expired - Lifetime CA1290445C (en) | 1986-04-15 | 1990-05-24 | Vertical deflection circuit |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000615748A Expired - Lifetime CA1290446C (en) | 1986-04-15 | 1990-05-24 | Vertical deflection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (2) | CA1290446C (en) |
-
1990
- 1990-05-24 CA CA000615748A patent/CA1290446C/en not_active Expired - Lifetime
- 1990-05-24 CA CA000615747A patent/CA1290445C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CA1290446C (en) | 1991-10-08 |
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| MKEX | Expiry |