CA1290446C - Vertical deflection circuit - Google Patents
Vertical deflection circuitInfo
- Publication number
- CA1290446C CA1290446C CA000615748A CA615748A CA1290446C CA 1290446 C CA1290446 C CA 1290446C CA 000615748 A CA000615748 A CA 000615748A CA 615748 A CA615748 A CA 615748A CA 1290446 C CA1290446 C CA 1290446C
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- deflection
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- voltage
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Abstract
Abstract A vertical deflection amplifier of a video display apparatus includes first and second transistor amplifier output stages arranged in a totem-pole, push-pull configuration. A vertical deflection winding is coupled to the output stages at a deflection amplifier output terminal. An s-capacitor is coupled to the deflection winding at a second terminal remote from the output terminal. A source of deflection rate signals is coupled to the deflection amplifier for generating a deflection current in the deflection winding. A base current generating circuit is coupled to one of the transistor amplifier output stages for providing base current thereto.
The S-capacitor voltage is applied to the base current generating circuit for enabling conduction of base current in the one amplifier output stage. When the video display apparatus is first turned on, the initially discharged S-capacitor is slowly charged from a DC voltage supply to delay generation of vertical deflection past completion of picture tube degaussing.
The S-capacitor voltage is applied to the base current generating circuit for enabling conduction of base current in the one amplifier output stage. When the video display apparatus is first turned on, the initially discharged S-capacitor is slowly charged from a DC voltage supply to delay generation of vertical deflection past completion of picture tube degaussing.
Description
~2~0~6 RCA 83,216A
V~RTICAL DEFLECTI~N CIRCUIT
This application is a division of Canadian Application ~erial No. 534,229, ~iled April 8, 1987.
This invention relates to deflection amplifier circuitry.
In a typical linearly operated vertical deflection circuit, first and second output transistors are coupled together in a push-pull configuration at a deflection amplifier output terminal. A vertical deflection winding, in series with an S-shaping capacitor, is coupled to the output terminal. A vertical rate, sawtooth input signal is coupled to the deflection amplifier to generate a sawtooth vertical deflection current in the deflection winding.
During the first half of vertical trace, the top output transistor is conducting to generate the first half of the vertical deflection current and to charge the S-shaping capacitor from a DC voltage source. During the second half of vertical trace, the bottom output transistor is conducting to apply the S-capacitor voltage to the deflection winding for generating the second half of the vertical deflection current.
The S-shaping capacitor is discharged by the vertical deflection current through the bottom transistor. Except for a small overlap interval at the center of trace, the top output transistor is nonconductive when the bottom transistor is conductive.
DC negative feedback of the amplifier output voltage or of the S-capacitor voltage establishes correct DC biasing of the deflection amplifier. Thus, for example, should the S-capacitor voltage tend to decrease, the DC feedback increases conduction of the top output transistor to increase the charging current to the S-capacitor from the DC voltage source, thereby maintaining the proper DC operating point.
A fault operating condition may arise if the S-capacitor becomes short-circuited, decreasing the DC
voltage at the amplifier output terminal to a very low value. The DC negative feedback loop tries to restore the DC
output voltage by turning on the top output transistor ~, - ~29(~6 -2- RCA 83, 216A
to full or near rull conductlon ln an attempt to recharge the S-capacitor from the DC voltage source vla the vertical de~lection winding.
Such fault mode operat on may be undesirable ln that excessive power dissipation may result in the top output device and in any current limiting resistor in series with the DC voltage source. Furthermore, the large unidirectional current flowing in the deflection winding during fault mode operation, may deflect the electron beams to such an extreme angle that they strike the picture tube neck, causing neck heating and possible tube breakage.
A feature of the invention is a vertical deflection circuit with amplifier drive circuitry that avoids such undesirable operatlon in a fault operating mode. A deflection amplifier includes first and second transistor amplifier output stages. A deflection winding is coupled to the first and second transistor amplifier output stages at a deflection amplifier output termlnal.
An S-shaping capacitance is coupled to the deflection winding. A source of de~lection rate signals is coupled to the deflection amplifier for generating a deflection current in the deflection winding. A base current generating circuit is coupled to one of the transistor amplifier output stages for providing base current thereto.
The base current generating circult is coupled to the second terminal and has an S-capacitance voltage applied thereto for enabling the conduction of the base current.
In carrying out an aspect of the inventlon, a main charging path of the S-capacitance is provided via the top output stage of a deflection amplifier arranged in a push-pull configuration. A second, slower charging path for the S-capacitance is also provided which bypasses the top output stage. Conduction of base current to the top output stage is enabled only when the S-capacitance voltage is greater than a predetermined magnitude.
During start-up, when the S-capacltance is initially discharged, the main charging path is disabled.
~.2~044~
_3_ RCA 83, 216A
The second charglng path charges the S-capac1tor to the voltage level needed to enable operatlon of the top output device. By proper selection o the charging rate in the second charging path, a start-up delay is provided to S operation of the vertical deflection circuit. The start-up delay enables picture tube degaussing to be completed before ver~ical deflection current is generated. ~his prevents the vertical deflection magnetic field from undesirably affecting the degaussing process.
In accordance with another inVentlve feature, a degaussing circuit is responsive to an on-off swltch for providing degaussing action during a degaussing interval inltiated when the on-off switch is switched to an "on"
position. A vertical deflection circuit includes a vertical deflection winding and a capacitor, in which capacltor there is developed a vertical rate voltage during steady-state operation that controls the,generation of vertical deflection current in the vertical deflection winding. A DC power supply generates a DC supply voltage that energizes the deflection circuit. The DC power supply is responsive to the on~off switch to generate the DC
supply voltage after the on-off switch is switched to the "on" position. The DC supply voltage attains a level adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval. A means for charging the capacitor from the DC power supply is provided, that charges the capacitor after the on-off switch is switched to the "on" position at a sufficiently slow rate to delay the generation of vertical deflection current pass the conclusion of the degaussing interval.
In the Drawing:
FIGURES 1 and 2 illustrate two different inventive embodiments of a vertical deflection circult; and FIGURE 3 illustrates a video display apparatus, embodying the invention, wherein start-up of the vertlcal deflection circuit is delayed until after completion of degaussing.
~l29~446 _~_ RCA 83,216A
In vertlcal deflection circult 20 of FIGURE 1, a vert~cal deflection amplifier 30 comprises output transistor stages Ql and Q2 coupled together in a push pull configuration at an amplifier output terminal 22. A
vertical deflection winding ~ is coupled to terminal 22.
An S-capacitor Cl is coupled to deflection windlng ~ at a second terminal 21 remote from output terminal 22. A
current sampling resistor R12 is coupled between the lower terminal of capacitor Cl and ground.
The collector of bottom output transistor Q2 is coupled to the base of top output transistor Q1 via a resistor R4 and a diode D4 to form a totem pole configuration, wherein base drive for top transistor Q1 ls shunted through bottom transistor Q2. A resistor R8 is 15 coupled between output terminal 22 and the collector of -~
transistor Q2 to reduce crossover distortion. A diode D3 parallels resistor R8 and becomes conductive during the second half of vertical trace to shunt current away from resistor R8 at large deflection current amplitudes during the second half of trace. This reduces.overall power dissipation during the second half of vertical trace and enables a lower DC operating point to be selected for output terminal 22. A +24V supply source is coupled to the collector of transistor Q1 via a small current limiting resistor R6 and a diode D5.
The control circuitry for deflection amplifier 30 includes a vertical sawtooth generator 23 that develops a vertical rate sawtooth voltage V3 that is AC coupled to the noninverting input terminal of a driver amplifier U1 via a capacitor C4 and a resistor R13. A reference voltage VREF
is coupled to the inverting input terminal. The output of driver U1 is coupled to the base of bottom transistor Q2 via resistor R9 of biasing resistors R9 and R14.
A base current generating circuit 40, embodying an aspect of the invention, generates a base current il for top output transistor Q1. Base current genera~lng circult 40 includes a bootstrap capacitor C2 having a lower " ,,~
. .
~L.2~
RC~ 83,216A
termlnal coupled to amplifier ou~put termlnal 22 at the emitter of transistor Ql and an upper terminal coupled to the junction of a diode Dl and a resistor R3. Resistor R3 is coupled to the base of transistor Q1. Bootstrap capacitor C2 is charged by a current iC2 flowing from terminal 21 via a relatively small valued resistor R2 and diode Dl. The value of current iC2 ls established in accordance with the S~capacitor voltage V1 established at terminal 21. During normal steady-state deflection circuit operation, voltage V1 is a vertical rate parabola voltage, skewed downwardly by the superimposed sawtooth voltage v5 developed across sampling resistor R12.
At the beginning portion of the vertical trace interval Tt, output transistor Ql is conducting a positive vertical deflection current iv to charge S-capacitor C1 from the +24V supply via resistor R6 and diode D5.
Bootstrap capacitor C2 provides the forward base current for transistor Q1 durlng the early portions of vertical trace. Near the beginning of vertical trace, deflection amplifier output voltage V2 developed at terminal 22 is sufficiently greater than S-capacitance voltage V1 to reverse bias diode Dl and prevent the recharging of bootstrap capacitor C2.
The decreasing, positive sawtooth portion of vertical deflection current iv during the fixst half of vertical trace is produced as a result of the decreas1ng conduction of top output transistor Q1. In the totem-pole deflection amplifier arrangement, the upwardly ramping sawtooth input voltage V3 ls amplified by driver U1 to increase the conduction of bottom output transistor Q2, thereby increasing the amount of current shunted away from the base of transistor Q1 via resistor R4 and diode D4. At some point near the center of vertical trace, translstor Q2 shunts enough base current il to cut off conduction in output transistor Q1.
During the second half of vertical trace, with transistor Q2 conductive, S-capacitor voltage v~ drives vertical deflect1on current iv in the negatlve direc~lon ~9~
~, vla ~ranslstor Q2. Amplifler U1 increases the conduc~lon of transistor Q2 as the second half of vertical trace progresses, to generate the negative portion of the downwardly ramping vertical deflection current.
During the vertical trace interval Tt, output voltage V2 is a downwardly ramping voltage. At some instant after the center of trace, S-capacitor voltage V1 has increased and output voltage V2 has decreased to values which enable diode Dl to become forward blased. At this time, bootstrap capacitor C2 is recharged by current iC2 to the S-capacitor voltage V1. With diode Dl conductlng, S-capacitor terminal 21 sources currents iC2 and 11.
When diode D1 first begins conducting after the center of vertical trace, deflection current iv flows into terminal 21 from S-capacitor C1, and is large enough to be the main source for current iC2. Near the center of trace and during the second half of trace, S-capacitor C1 becomes the main source for current iC2.
To maintain scan linearlty, the AC sawtooth sampling voltage v5, developed across current sampling resistor R12, is summed via a resistor R11 with the 180 out-of-phase sawtooth input voltage V3 at the noninverting lnput terminal of amplifier U1.
To stabilize the DC operating point of output terminal 22 at a predeterm1ned average value, S-capacltor voltage V1, developed at terminal 21, is DC coupled to the noninverting input terminal of driver U1 via a resistor R10. A negative feedback loop is formed from output terminal 22, that includes deflection winding Lv, terminal 21, driver amplifier U1 and bottom output transistor Q2.
Should, for example, S-capacitor voltage V1 tend to decrease, this decrease in voltage is applied to driver U1 to decrease conduction of transistor Q2. Conduction in transistor Q1 is increased to recharge capacitor C1 to its stabilized average value.
To initiate the vertical retrace lnterval Tr, sawtooth input voltage V3 abruptly decreases, produclng the cutoff of bottom output transistor Q2 at the end of trace.
~29~4~
_7_ RCA 83,216A
resonant retrace lnterval is initlated that charges a retrace capacitor C3 coupled across diode D5. When transistor Q2 becomes cut off, ou~put voltage V2 beglns to increase due to the inductive kick provlded by deflectlon winding ~. Voltage V2 forward biases a retrace diode D2 coupled between the base and emitter electrodes of transistor Q1, and forward biases the base-collector path of transistor Ql. Deflection current iv flows via retrace diode D2 and reverse base~collector conduction into retrace capacitor C3 and the +24 volt supply. Deflection current iV begins to rapidly ramp up during retrace.
During retrace, when deflection current iv is negative, bootstrap capaci~or C2 is discharged by deflection current iv via reverse collector conduction of transistor Q1. When deflection current iv ramps up durlng retrace through its zero current value, the inductive action of deflection winding ~ decreases output voltage V2 at the emitter of transistor Ql by an amount that enables diode D2 to become reverse biased. Bootstrap capacitor C2 begins to discharge into the base of top output transistor Q1, maintaining the transistor in saturated conduction throughout the remainder of the retrace interval.
At the end of vertical retrace, the positive retrace deflection current iv has increased to a value that enables sawtooth sampling voltage Vs to reestablish drive to bottom output transistor Q2, thereby initiating the subsequent vertical trace interval. With bottom device Q2 conducting, a shunt path is established for current 11 that bypasses the base of transistor Q1, bringing the transistor out of saturation lnto the linear mode of operation.
At the end of vertical retrace, some voltage remains in retrace capacitor C3. Capacitor C3 becomes discharged very early within trace by conduction of transistor Q1, after which time diode D5 becomes forward biased.
One terminal of a resistor R7 is coupled to a +131V DC voltage supply of value greater than the +24V
supply. The other terminal of resistor R7 is coupled to the ~ 291:)44~
-8- RCA 83, 216A
junction of the collector of transistor Q1 and retrace capacitor C3. A resistor R5 is coupled across relrace capacitor C3. During the second half of vertical trace, when transistor Ql is cut off, capacitor C3 is precharged to a voltage level that ls established by voltage dividing resistors R7 and R5, coupled between the +131V voltage source and the +24V voltage source, in accordance with the RC time constant associated with the resistors and capacitor C3. The precharged voltage on retrace capacitor C3 at the end of trace provides a more rapid retrace of vertical deflection current iv, thereby shortening the duration of retrace interval Tr.
In accordance with an aspect of the invention, S-capacitor voltage V1 is applied to base current generating circuit 40 independently of the DC stabilizing negative feedback loop, to enable the generation of current il when the S-capacitor voltage Vl e~ceeds a predetermined magnitude.
Base current generating circuit 40 is dependent on S-capacitance voltage V1 as a DC voltage supply source.
Should the magnitude of S-capacitance voltage Vl decrease below the predetermined magnitude, base current generating clrcuit 40 will be unable to generate adequate current il to maintain top output transistor Ql in conduction. The main charging path for S-capacitor Cl is via top output transistor Ql. When base current generating circuit 40 is unable to supply base current to maintain transistor Ql conductive, this main charging path will be disabled.
Under certain fault operating situations, it may be desirable for the fault to trigger the disabling of base current generating circuit 40 and of the main charging path to capacitor Cl. Such a situation may arise, for example, if S-capacitor Cl becomes short-circuited. When S-capacitor Cl becomes short-circuited, voltage V1 will tend to decrease to zero. The DC negative feedback loop via resistor RlO tries to maintain voltage Vl at its stabilized value by turning bottom output transistor Q2 off, in an attempt to maln~ain transistor Q1 conducting , ~ :
~904~
-9- RCA 83, 216A
heavily. I f base current generating c1rcuit 40 were not disabled in such a sltuation, large current would flow in the main charging path to the now short-clrcuited S-capacitor via deflection winding Lv, transistor Ql, diode DS and resistor R6. Excessive dissipation and possible component failure would result. Furthermore, the large unidirectional current flowing in deflection winding L~
would deflect the electron beams of the picture tube by a large angle, permitting the electron beams to strike and possibly damage the neck of the picture tube.
In accordance with an aspect of the invention, when the S-capacitor voltage decreases below a predetermined magnitude, such as may occur when the S-capacitor becomes short-circuited, voltage V1 becomes too low to provide forward bias to diode Dl. Bootstrap capacitor C2 becomes disconnected from its source of charging current, disabling the generation of current i1 into the base of top output transistor Ql. Without base current, transistor Q1 becomes nonconductive, disabling the main charging path into the short-circuit of capacitor C1,.
thereby avoiding undesirable short-circuit fault operation of vertical deflection circuit 20.
In accordance with another aspect of the invention, an auxiliary or second charging path for capacitor Cl is provided directly to a DC voltage supply, bypassing the main charging path of top output transistor Q1 and the vertical deflection winding ~. A relatively large valued resistor Rl is coupled from a +30V supply to S-capacitor terminal 21. An auxiliary charging current io flows from the +30V supply via resistor Rl to S-capacitor terminal 21.
When the televislon receiver is first turned on, S-capacitor C1 is initially in a discharged state. When the power supply for the television receiver generates the DC supply voltages such as the +24V, +30V and +131V
voltages, s-capacitor Cl begins to charge with current io from the +30V supply via resistor Rl. Due to the relatively large value of S-capacitor C1, voltage Vl ~ 29~44~
-10- RCA 83, 216A
rema1ns below the predetermlned magnitude requlred during start-up for enabling base current generatlng circuit 40.
During this substantlal start-up delay interval, transistor Q1 remain~ essentially cutoff, disabling the main charging path for capacitor Cl via deflection winding Lv.
When the television receiver is first turned on, the discharged S-capacitor C1 slowly begins to charge with current io from the +30V supply. Voltage V1 begins to increase as C1 charges. As long as voltage Vl is below its normal steady-state value, the DC negative feedback loop maintains transistor Q2 cutoff. No significant current path to ground exists by which bootstrap capacitor C2 may charge.
When S-capacitor C1 has charged sufficiently to permit voltage Vl to increase to approximately or slightly greater than its normal, steady-state value, the DC
negative feedback loop turns on transistor Q2, enabling bootstrap capacitor C2 to charge to a value which is capable of forward biasing transistor Ql. Soon afterwards, normal steady-state deflection circuit operation commences.
During steady-state operation, the value of auxiliary charging current io is determined by the difference in voltage between the +30V supply and the steady-state value of S-capacitor voltage Vl. The DC
component of current io flows into terminal 21 from the +30V supply. By proper selection of component values, such as the value of resistor R3, the DC component of the current flowing in the current path (RZ, Dl, R3) equals the DC component of current io. In this situation, no net DC
current flows in deflection winding LV from resistor Rl.
If the DC component of current il differs from the DC
component of current io~ the difference current will flow as a DC component in vertical deflection current iv. This difference current is of relatively small value and may be eliminated, if so desired, by proper adjustment of a DC
centering control circuit for deflectlon wlnding ~J, not illustrated in FIGURE 1.
4~
~ RCA 83,216A
For the values given in the circult of FIGURE 1, the start-up delay time for the generation of vertical deflection current is approximately one to two seconds.
The start-up delay advantageously permits completion of picture tube degaussing before the generation of vertical deflection current, thereby avoiding any undesirable interaction between the vertical deflection magnetic field and the degaussing process.
FIGURE 3 illustrates a portion of a video display apparatus 60, embodying an aspect of the invention, that includes a picture tube degaussing circuit 10 and vertical deflection circuit 20 of FIGURE 1, wherein start-up of the vertical deflection circuit is delayed until a~ter completion of degaussing. Vertical deflection circuit 20 of FIGURE 1 is shown in FIGURE 3 in partial detail only.
In FIGURE 1, an AC mains supply, developing a voltage VAc, energizes a DC power supply 16 when an on-off switch 15 is conductive, or switched to the on-position.
DC power suppl,v 16 develops various DC supply voltages for the circuitry of video display apparatus 60 including a +DCl, a +DC2, a +DC3 and a +DC4 voltage. ~oltage +DC4, for example, energizes a horizontal deflection circult 17 to generate horizontal deflection current in a horizontal deflection winding ~.
Degaussing circuit 10 includes a degaussing coil DG located adjacent a picture tube 50 of video display apparatus 60. Degaussing coil DG is coupled in series with a positive temperature coef~icient thermistor 13, AC mains supply 14 and the mechanical switch portion of an electro-mechanical degaussing relay 11. The mechanical switch portion of relay ll is normally non~conductive when the relay coil is deengerized.
To initiate a degaussing interval, when degaussing action takes place, on-off switch 15 is made conductive to permit DC power supply 16 to develop the DC
supply voltages, including the +DCl supply voltage. The +DCl supply voltage is coupled via a charging capacitor 12 to the coil of relay ll. Current flows in the relay coil 9~
-12 RCA 83, 216A
from the +DCl supply, energiz1ng the relay coil and clos1ng the mechanical switch portion of degaussing relay 11. With the mechanical switch portion of relay 11 conductlve, AC
degaussing current flows from AC malns supply 14 in degaussing coil DG and thermistor 13 at the frequency of AC
mains voltage VAc. As thermistor 13 self-heats by the degaussing current, its resistance increases producing a decaying alternating degaussing current that reaches a very low residual amplitude, brlnging the degaussing lnterval to a conclusion. The decaying alternating degaussing current produces a decaying alternating degaussing magnetic field that degausses the shadow mask, magnetlc shield and other magnetizable material associated with picture tube 50, but not illustrated in FIGURE 3. After conclusion of the degaussing interval, series capacitor 12 charges to the +DCl supply level, preventing current from flowing in the coil of relay ll. The mechanical switch portion of relay ll returns to its normally non-conductive position to eliminate the flow of even a residual current in degaussing coil DG after conclusion of the degaussing interval.
The DC supply voltages developed by power supply 16 are rapidly developed from a zero voltage level after on-off switch lS is made conductive. In particular, the DC
supply voltages developed for vertical deflection circuit 20 attain levels adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval.
Advantageously, however, capacitor C1, whose voltage Vl controls operation of vertical deflection circuit 20, disables base current generator 40 to prevent the generation of vertical,deflection current in vertlcal deflection winding LV immediately after on-off switch lS is closed. Capac1tor C1 is slowly charged from the +DC3 supply via resistor Rl to delay the enablement of base current generating circuit 40 and thus to delay the generation of vertical deflection current until after conclusion of the degaussing interval. This delay avoids ~2~
-13- RCA 83, 216A
any undesirable interactlon between the vertical deflec~1on maynetlc field and the degaussing process.
FIGURE 2 illustrates a vertical deflection circuit lZ0, embodying the invention, similar to the S vertical deflection circuit of FIGURE 1, but modified to reduce any net DC current that may flow through deflection winding ~ from auxiliary charging current io. Items in FIGURES 1 and 2 similarly identified represent simllar elements or quantities.
In FIGURE 2, a controllable impedance, a transistor Q3, is interposed between base current ge~erating circuit 40 and the +30V supply, with the collector of the transistor coupled to the +30V supply and the emitter coupled to resistor R2. The base of transistor Q3 is coupled to s-capacitor second terminal 21 at the junction of charging resistor Rl and S-capacitor C1. The S-capacitor voltage V1 controls the conductivlty of transistor Q3 a~d the amount of current flowing ln the collector circuit of transistor Q3 to base current generating circuit 40.
Should capacitor Cl become short-circuited and voltage V1 decrease to near zero, transistor Q3 becomes cut off, disconnecting the +30V supply from base current generating circuit 40, and disabling the generation of current il into the base of top output transistor Ql.
Similarly during start-up, because capacitor Cl is initially discharged, transistor Q3 is cut off to disable top output transistor Ql. The auxiliary charging current io charges capacitor C1 after a start-up delay to the value needed to turn on transistor Q3 for enabling base current generating circuit 40. Because of the gain provided by transistor Q3, charging current io may be relatively small, and the net DC current component introduced into deflection winding ~ by current io is negligible.
V~RTICAL DEFLECTI~N CIRCUIT
This application is a division of Canadian Application ~erial No. 534,229, ~iled April 8, 1987.
This invention relates to deflection amplifier circuitry.
In a typical linearly operated vertical deflection circuit, first and second output transistors are coupled together in a push-pull configuration at a deflection amplifier output terminal. A vertical deflection winding, in series with an S-shaping capacitor, is coupled to the output terminal. A vertical rate, sawtooth input signal is coupled to the deflection amplifier to generate a sawtooth vertical deflection current in the deflection winding.
During the first half of vertical trace, the top output transistor is conducting to generate the first half of the vertical deflection current and to charge the S-shaping capacitor from a DC voltage source. During the second half of vertical trace, the bottom output transistor is conducting to apply the S-capacitor voltage to the deflection winding for generating the second half of the vertical deflection current.
The S-shaping capacitor is discharged by the vertical deflection current through the bottom transistor. Except for a small overlap interval at the center of trace, the top output transistor is nonconductive when the bottom transistor is conductive.
DC negative feedback of the amplifier output voltage or of the S-capacitor voltage establishes correct DC biasing of the deflection amplifier. Thus, for example, should the S-capacitor voltage tend to decrease, the DC feedback increases conduction of the top output transistor to increase the charging current to the S-capacitor from the DC voltage source, thereby maintaining the proper DC operating point.
A fault operating condition may arise if the S-capacitor becomes short-circuited, decreasing the DC
voltage at the amplifier output terminal to a very low value. The DC negative feedback loop tries to restore the DC
output voltage by turning on the top output transistor ~, - ~29(~6 -2- RCA 83, 216A
to full or near rull conductlon ln an attempt to recharge the S-capacitor from the DC voltage source vla the vertical de~lection winding.
Such fault mode operat on may be undesirable ln that excessive power dissipation may result in the top output device and in any current limiting resistor in series with the DC voltage source. Furthermore, the large unidirectional current flowing in the deflection winding during fault mode operation, may deflect the electron beams to such an extreme angle that they strike the picture tube neck, causing neck heating and possible tube breakage.
A feature of the invention is a vertical deflection circuit with amplifier drive circuitry that avoids such undesirable operatlon in a fault operating mode. A deflection amplifier includes first and second transistor amplifier output stages. A deflection winding is coupled to the first and second transistor amplifier output stages at a deflection amplifier output termlnal.
An S-shaping capacitance is coupled to the deflection winding. A source of de~lection rate signals is coupled to the deflection amplifier for generating a deflection current in the deflection winding. A base current generating circuit is coupled to one of the transistor amplifier output stages for providing base current thereto.
The base current generating circult is coupled to the second terminal and has an S-capacitance voltage applied thereto for enabling the conduction of the base current.
In carrying out an aspect of the inventlon, a main charging path of the S-capacitance is provided via the top output stage of a deflection amplifier arranged in a push-pull configuration. A second, slower charging path for the S-capacitance is also provided which bypasses the top output stage. Conduction of base current to the top output stage is enabled only when the S-capacitance voltage is greater than a predetermined magnitude.
During start-up, when the S-capacltance is initially discharged, the main charging path is disabled.
~.2~044~
_3_ RCA 83, 216A
The second charglng path charges the S-capac1tor to the voltage level needed to enable operatlon of the top output device. By proper selection o the charging rate in the second charging path, a start-up delay is provided to S operation of the vertical deflection circuit. The start-up delay enables picture tube degaussing to be completed before ver~ical deflection current is generated. ~his prevents the vertical deflection magnetic field from undesirably affecting the degaussing process.
In accordance with another inVentlve feature, a degaussing circuit is responsive to an on-off swltch for providing degaussing action during a degaussing interval inltiated when the on-off switch is switched to an "on"
position. A vertical deflection circuit includes a vertical deflection winding and a capacitor, in which capacltor there is developed a vertical rate voltage during steady-state operation that controls the,generation of vertical deflection current in the vertical deflection winding. A DC power supply generates a DC supply voltage that energizes the deflection circuit. The DC power supply is responsive to the on~off switch to generate the DC
supply voltage after the on-off switch is switched to the "on" position. The DC supply voltage attains a level adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval. A means for charging the capacitor from the DC power supply is provided, that charges the capacitor after the on-off switch is switched to the "on" position at a sufficiently slow rate to delay the generation of vertical deflection current pass the conclusion of the degaussing interval.
In the Drawing:
FIGURES 1 and 2 illustrate two different inventive embodiments of a vertical deflection circult; and FIGURE 3 illustrates a video display apparatus, embodying the invention, wherein start-up of the vertlcal deflection circuit is delayed until after completion of degaussing.
~l29~446 _~_ RCA 83,216A
In vertlcal deflection circult 20 of FIGURE 1, a vert~cal deflection amplifier 30 comprises output transistor stages Ql and Q2 coupled together in a push pull configuration at an amplifier output terminal 22. A
vertical deflection winding ~ is coupled to terminal 22.
An S-capacitor Cl is coupled to deflection windlng ~ at a second terminal 21 remote from output terminal 22. A
current sampling resistor R12 is coupled between the lower terminal of capacitor Cl and ground.
The collector of bottom output transistor Q2 is coupled to the base of top output transistor Q1 via a resistor R4 and a diode D4 to form a totem pole configuration, wherein base drive for top transistor Q1 ls shunted through bottom transistor Q2. A resistor R8 is 15 coupled between output terminal 22 and the collector of -~
transistor Q2 to reduce crossover distortion. A diode D3 parallels resistor R8 and becomes conductive during the second half of vertical trace to shunt current away from resistor R8 at large deflection current amplitudes during the second half of trace. This reduces.overall power dissipation during the second half of vertical trace and enables a lower DC operating point to be selected for output terminal 22. A +24V supply source is coupled to the collector of transistor Q1 via a small current limiting resistor R6 and a diode D5.
The control circuitry for deflection amplifier 30 includes a vertical sawtooth generator 23 that develops a vertical rate sawtooth voltage V3 that is AC coupled to the noninverting input terminal of a driver amplifier U1 via a capacitor C4 and a resistor R13. A reference voltage VREF
is coupled to the inverting input terminal. The output of driver U1 is coupled to the base of bottom transistor Q2 via resistor R9 of biasing resistors R9 and R14.
A base current generating circuit 40, embodying an aspect of the invention, generates a base current il for top output transistor Q1. Base current genera~lng circult 40 includes a bootstrap capacitor C2 having a lower " ,,~
. .
~L.2~
RC~ 83,216A
termlnal coupled to amplifier ou~put termlnal 22 at the emitter of transistor Ql and an upper terminal coupled to the junction of a diode Dl and a resistor R3. Resistor R3 is coupled to the base of transistor Q1. Bootstrap capacitor C2 is charged by a current iC2 flowing from terminal 21 via a relatively small valued resistor R2 and diode Dl. The value of current iC2 ls established in accordance with the S~capacitor voltage V1 established at terminal 21. During normal steady-state deflection circuit operation, voltage V1 is a vertical rate parabola voltage, skewed downwardly by the superimposed sawtooth voltage v5 developed across sampling resistor R12.
At the beginning portion of the vertical trace interval Tt, output transistor Ql is conducting a positive vertical deflection current iv to charge S-capacitor C1 from the +24V supply via resistor R6 and diode D5.
Bootstrap capacitor C2 provides the forward base current for transistor Q1 durlng the early portions of vertical trace. Near the beginning of vertical trace, deflection amplifier output voltage V2 developed at terminal 22 is sufficiently greater than S-capacitance voltage V1 to reverse bias diode Dl and prevent the recharging of bootstrap capacitor C2.
The decreasing, positive sawtooth portion of vertical deflection current iv during the fixst half of vertical trace is produced as a result of the decreas1ng conduction of top output transistor Q1. In the totem-pole deflection amplifier arrangement, the upwardly ramping sawtooth input voltage V3 ls amplified by driver U1 to increase the conduction of bottom output transistor Q2, thereby increasing the amount of current shunted away from the base of transistor Q1 via resistor R4 and diode D4. At some point near the center of vertical trace, translstor Q2 shunts enough base current il to cut off conduction in output transistor Q1.
During the second half of vertical trace, with transistor Q2 conductive, S-capacitor voltage v~ drives vertical deflect1on current iv in the negatlve direc~lon ~9~
~, vla ~ranslstor Q2. Amplifler U1 increases the conduc~lon of transistor Q2 as the second half of vertical trace progresses, to generate the negative portion of the downwardly ramping vertical deflection current.
During the vertical trace interval Tt, output voltage V2 is a downwardly ramping voltage. At some instant after the center of trace, S-capacitor voltage V1 has increased and output voltage V2 has decreased to values which enable diode Dl to become forward blased. At this time, bootstrap capacitor C2 is recharged by current iC2 to the S-capacitor voltage V1. With diode Dl conductlng, S-capacitor terminal 21 sources currents iC2 and 11.
When diode D1 first begins conducting after the center of vertical trace, deflection current iv flows into terminal 21 from S-capacitor C1, and is large enough to be the main source for current iC2. Near the center of trace and during the second half of trace, S-capacitor C1 becomes the main source for current iC2.
To maintain scan linearlty, the AC sawtooth sampling voltage v5, developed across current sampling resistor R12, is summed via a resistor R11 with the 180 out-of-phase sawtooth input voltage V3 at the noninverting lnput terminal of amplifier U1.
To stabilize the DC operating point of output terminal 22 at a predeterm1ned average value, S-capacltor voltage V1, developed at terminal 21, is DC coupled to the noninverting input terminal of driver U1 via a resistor R10. A negative feedback loop is formed from output terminal 22, that includes deflection winding Lv, terminal 21, driver amplifier U1 and bottom output transistor Q2.
Should, for example, S-capacitor voltage V1 tend to decrease, this decrease in voltage is applied to driver U1 to decrease conduction of transistor Q2. Conduction in transistor Q1 is increased to recharge capacitor C1 to its stabilized average value.
To initiate the vertical retrace lnterval Tr, sawtooth input voltage V3 abruptly decreases, produclng the cutoff of bottom output transistor Q2 at the end of trace.
~29~4~
_7_ RCA 83,216A
resonant retrace lnterval is initlated that charges a retrace capacitor C3 coupled across diode D5. When transistor Q2 becomes cut off, ou~put voltage V2 beglns to increase due to the inductive kick provlded by deflectlon winding ~. Voltage V2 forward biases a retrace diode D2 coupled between the base and emitter electrodes of transistor Q1, and forward biases the base-collector path of transistor Ql. Deflection current iv flows via retrace diode D2 and reverse base~collector conduction into retrace capacitor C3 and the +24 volt supply. Deflection current iV begins to rapidly ramp up during retrace.
During retrace, when deflection current iv is negative, bootstrap capaci~or C2 is discharged by deflection current iv via reverse collector conduction of transistor Q1. When deflection current iv ramps up durlng retrace through its zero current value, the inductive action of deflection winding ~ decreases output voltage V2 at the emitter of transistor Ql by an amount that enables diode D2 to become reverse biased. Bootstrap capacitor C2 begins to discharge into the base of top output transistor Q1, maintaining the transistor in saturated conduction throughout the remainder of the retrace interval.
At the end of vertical retrace, the positive retrace deflection current iv has increased to a value that enables sawtooth sampling voltage Vs to reestablish drive to bottom output transistor Q2, thereby initiating the subsequent vertical trace interval. With bottom device Q2 conducting, a shunt path is established for current 11 that bypasses the base of transistor Q1, bringing the transistor out of saturation lnto the linear mode of operation.
At the end of vertical retrace, some voltage remains in retrace capacitor C3. Capacitor C3 becomes discharged very early within trace by conduction of transistor Q1, after which time diode D5 becomes forward biased.
One terminal of a resistor R7 is coupled to a +131V DC voltage supply of value greater than the +24V
supply. The other terminal of resistor R7 is coupled to the ~ 291:)44~
-8- RCA 83, 216A
junction of the collector of transistor Q1 and retrace capacitor C3. A resistor R5 is coupled across relrace capacitor C3. During the second half of vertical trace, when transistor Ql is cut off, capacitor C3 is precharged to a voltage level that ls established by voltage dividing resistors R7 and R5, coupled between the +131V voltage source and the +24V voltage source, in accordance with the RC time constant associated with the resistors and capacitor C3. The precharged voltage on retrace capacitor C3 at the end of trace provides a more rapid retrace of vertical deflection current iv, thereby shortening the duration of retrace interval Tr.
In accordance with an aspect of the invention, S-capacitor voltage V1 is applied to base current generating circuit 40 independently of the DC stabilizing negative feedback loop, to enable the generation of current il when the S-capacitor voltage Vl e~ceeds a predetermined magnitude.
Base current generating circuit 40 is dependent on S-capacitance voltage V1 as a DC voltage supply source.
Should the magnitude of S-capacitance voltage Vl decrease below the predetermined magnitude, base current generating clrcuit 40 will be unable to generate adequate current il to maintain top output transistor Ql in conduction. The main charging path for S-capacitor Cl is via top output transistor Ql. When base current generating circuit 40 is unable to supply base current to maintain transistor Ql conductive, this main charging path will be disabled.
Under certain fault operating situations, it may be desirable for the fault to trigger the disabling of base current generating circuit 40 and of the main charging path to capacitor Cl. Such a situation may arise, for example, if S-capacitor Cl becomes short-circuited. When S-capacitor Cl becomes short-circuited, voltage V1 will tend to decrease to zero. The DC negative feedback loop via resistor RlO tries to maintain voltage Vl at its stabilized value by turning bottom output transistor Q2 off, in an attempt to maln~ain transistor Q1 conducting , ~ :
~904~
-9- RCA 83, 216A
heavily. I f base current generating c1rcuit 40 were not disabled in such a sltuation, large current would flow in the main charging path to the now short-clrcuited S-capacitor via deflection winding Lv, transistor Ql, diode DS and resistor R6. Excessive dissipation and possible component failure would result. Furthermore, the large unidirectional current flowing in deflection winding L~
would deflect the electron beams of the picture tube by a large angle, permitting the electron beams to strike and possibly damage the neck of the picture tube.
In accordance with an aspect of the invention, when the S-capacitor voltage decreases below a predetermined magnitude, such as may occur when the S-capacitor becomes short-circuited, voltage V1 becomes too low to provide forward bias to diode Dl. Bootstrap capacitor C2 becomes disconnected from its source of charging current, disabling the generation of current i1 into the base of top output transistor Ql. Without base current, transistor Q1 becomes nonconductive, disabling the main charging path into the short-circuit of capacitor C1,.
thereby avoiding undesirable short-circuit fault operation of vertical deflection circuit 20.
In accordance with another aspect of the invention, an auxiliary or second charging path for capacitor Cl is provided directly to a DC voltage supply, bypassing the main charging path of top output transistor Q1 and the vertical deflection winding ~. A relatively large valued resistor Rl is coupled from a +30V supply to S-capacitor terminal 21. An auxiliary charging current io flows from the +30V supply via resistor Rl to S-capacitor terminal 21.
When the televislon receiver is first turned on, S-capacitor C1 is initially in a discharged state. When the power supply for the television receiver generates the DC supply voltages such as the +24V, +30V and +131V
voltages, s-capacitor Cl begins to charge with current io from the +30V supply via resistor Rl. Due to the relatively large value of S-capacitor C1, voltage Vl ~ 29~44~
-10- RCA 83, 216A
rema1ns below the predetermlned magnitude requlred during start-up for enabling base current generatlng circuit 40.
During this substantlal start-up delay interval, transistor Q1 remain~ essentially cutoff, disabling the main charging path for capacitor Cl via deflection winding Lv.
When the television receiver is first turned on, the discharged S-capacitor C1 slowly begins to charge with current io from the +30V supply. Voltage V1 begins to increase as C1 charges. As long as voltage Vl is below its normal steady-state value, the DC negative feedback loop maintains transistor Q2 cutoff. No significant current path to ground exists by which bootstrap capacitor C2 may charge.
When S-capacitor C1 has charged sufficiently to permit voltage Vl to increase to approximately or slightly greater than its normal, steady-state value, the DC
negative feedback loop turns on transistor Q2, enabling bootstrap capacitor C2 to charge to a value which is capable of forward biasing transistor Ql. Soon afterwards, normal steady-state deflection circuit operation commences.
During steady-state operation, the value of auxiliary charging current io is determined by the difference in voltage between the +30V supply and the steady-state value of S-capacitor voltage Vl. The DC
component of current io flows into terminal 21 from the +30V supply. By proper selection of component values, such as the value of resistor R3, the DC component of the current flowing in the current path (RZ, Dl, R3) equals the DC component of current io. In this situation, no net DC
current flows in deflection winding LV from resistor Rl.
If the DC component of current il differs from the DC
component of current io~ the difference current will flow as a DC component in vertical deflection current iv. This difference current is of relatively small value and may be eliminated, if so desired, by proper adjustment of a DC
centering control circuit for deflectlon wlnding ~J, not illustrated in FIGURE 1.
4~
~ RCA 83,216A
For the values given in the circult of FIGURE 1, the start-up delay time for the generation of vertical deflection current is approximately one to two seconds.
The start-up delay advantageously permits completion of picture tube degaussing before the generation of vertical deflection current, thereby avoiding any undesirable interaction between the vertical deflection magnetic field and the degaussing process.
FIGURE 3 illustrates a portion of a video display apparatus 60, embodying an aspect of the invention, that includes a picture tube degaussing circuit 10 and vertical deflection circuit 20 of FIGURE 1, wherein start-up of the vertical deflection circuit is delayed until a~ter completion of degaussing. Vertical deflection circuit 20 of FIGURE 1 is shown in FIGURE 3 in partial detail only.
In FIGURE 1, an AC mains supply, developing a voltage VAc, energizes a DC power supply 16 when an on-off switch 15 is conductive, or switched to the on-position.
DC power suppl,v 16 develops various DC supply voltages for the circuitry of video display apparatus 60 including a +DCl, a +DC2, a +DC3 and a +DC4 voltage. ~oltage +DC4, for example, energizes a horizontal deflection circult 17 to generate horizontal deflection current in a horizontal deflection winding ~.
Degaussing circuit 10 includes a degaussing coil DG located adjacent a picture tube 50 of video display apparatus 60. Degaussing coil DG is coupled in series with a positive temperature coef~icient thermistor 13, AC mains supply 14 and the mechanical switch portion of an electro-mechanical degaussing relay 11. The mechanical switch portion of relay ll is normally non~conductive when the relay coil is deengerized.
To initiate a degaussing interval, when degaussing action takes place, on-off switch 15 is made conductive to permit DC power supply 16 to develop the DC
supply voltages, including the +DCl supply voltage. The +DCl supply voltage is coupled via a charging capacitor 12 to the coil of relay ll. Current flows in the relay coil 9~
-12 RCA 83, 216A
from the +DCl supply, energiz1ng the relay coil and clos1ng the mechanical switch portion of degaussing relay 11. With the mechanical switch portion of relay 11 conductlve, AC
degaussing current flows from AC malns supply 14 in degaussing coil DG and thermistor 13 at the frequency of AC
mains voltage VAc. As thermistor 13 self-heats by the degaussing current, its resistance increases producing a decaying alternating degaussing current that reaches a very low residual amplitude, brlnging the degaussing lnterval to a conclusion. The decaying alternating degaussing current produces a decaying alternating degaussing magnetic field that degausses the shadow mask, magnetlc shield and other magnetizable material associated with picture tube 50, but not illustrated in FIGURE 3. After conclusion of the degaussing interval, series capacitor 12 charges to the +DCl supply level, preventing current from flowing in the coil of relay ll. The mechanical switch portion of relay ll returns to its normally non-conductive position to eliminate the flow of even a residual current in degaussing coil DG after conclusion of the degaussing interval.
The DC supply voltages developed by power supply 16 are rapidly developed from a zero voltage level after on-off switch lS is made conductive. In particular, the DC
supply voltages developed for vertical deflection circuit 20 attain levels adequate to energize the vertical deflection circuit prior to the conclusion of the degaussing interval.
Advantageously, however, capacitor C1, whose voltage Vl controls operation of vertical deflection circuit 20, disables base current generator 40 to prevent the generation of vertical,deflection current in vertlcal deflection winding LV immediately after on-off switch lS is closed. Capac1tor C1 is slowly charged from the +DC3 supply via resistor Rl to delay the enablement of base current generating circuit 40 and thus to delay the generation of vertical deflection current until after conclusion of the degaussing interval. This delay avoids ~2~
-13- RCA 83, 216A
any undesirable interactlon between the vertical deflec~1on maynetlc field and the degaussing process.
FIGURE 2 illustrates a vertical deflection circuit lZ0, embodying the invention, similar to the S vertical deflection circuit of FIGURE 1, but modified to reduce any net DC current that may flow through deflection winding ~ from auxiliary charging current io. Items in FIGURES 1 and 2 similarly identified represent simllar elements or quantities.
In FIGURE 2, a controllable impedance, a transistor Q3, is interposed between base current ge~erating circuit 40 and the +30V supply, with the collector of the transistor coupled to the +30V supply and the emitter coupled to resistor R2. The base of transistor Q3 is coupled to s-capacitor second terminal 21 at the junction of charging resistor Rl and S-capacitor C1. The S-capacitor voltage V1 controls the conductivlty of transistor Q3 a~d the amount of current flowing ln the collector circuit of transistor Q3 to base current generating circuit 40.
Should capacitor Cl become short-circuited and voltage V1 decrease to near zero, transistor Q3 becomes cut off, disconnecting the +30V supply from base current generating circuit 40, and disabling the generation of current il into the base of top output transistor Ql.
Similarly during start-up, because capacitor Cl is initially discharged, transistor Q3 is cut off to disable top output transistor Ql. The auxiliary charging current io charges capacitor C1 after a start-up delay to the value needed to turn on transistor Q3 for enabling base current generating circuit 40. Because of the gain provided by transistor Q3, charging current io may be relatively small, and the net DC current component introduced into deflection winding ~ by current io is negligible.
Claims
RCA 83,216A
The embodiments of the invention in which a exclusive property or privilege is claimed are defined as follows:
1. A deflection circuit, comprising:
a deflection amplifier;
a deflection winding coupled to an output terminal of said deflection amplifier;
an S-capacitance coupled to said deflection winding and being charged during steady state operation via a main charging path that includes a main current conduction path within said deflection amplifier for developing an S-capacitance voltage;
a control circuit coupled to said deflection amplifier and responsive to a deflection rate input signal for generating a deflection current in said deflection winding, said control circuit being responsive to said S-capacitance voltage for disabling operation of said deflection amplifier when said S-capacitance voltage is less than a predetermined magnitude; and an auxiliary charging path for said S-capacitance that bypasses said main charging path for charging an initially discharged S-capacitance during a start-up interval to enable said operation of said deflection amplifier.
2. A deflection circuit according to Claim 1 wherein said auxiliary charging path also bypasses said deflection winding.
3. A deflection circuit according to Claim 2 wherein said S-capacitance is coupled to a terminal of said deflection winding remote from said output terminal.
4. A deflection circuit according to Claim 3 wherein said main current conduction path is a main path of a transistor output stage within said RCA 83,216A
deflection amplifier and wherein said control circuit includes a direct current path for forward base current in said transistor output stage from a DC voltage supply, said direct current path being disabled when said S-capacitance voltage is less than said predetermined magnitude.
5. A deflection circuit according to Claim 4 wherein said direct current path includes a main current path of a semiconductor element, said S-capacitance voltage being applied to said semiconductor element for blocking the main current path thereof when said S-capacitance voltage is less than said predetermined magnitude.
The embodiments of the invention in which a exclusive property or privilege is claimed are defined as follows:
1. A deflection circuit, comprising:
a deflection amplifier;
a deflection winding coupled to an output terminal of said deflection amplifier;
an S-capacitance coupled to said deflection winding and being charged during steady state operation via a main charging path that includes a main current conduction path within said deflection amplifier for developing an S-capacitance voltage;
a control circuit coupled to said deflection amplifier and responsive to a deflection rate input signal for generating a deflection current in said deflection winding, said control circuit being responsive to said S-capacitance voltage for disabling operation of said deflection amplifier when said S-capacitance voltage is less than a predetermined magnitude; and an auxiliary charging path for said S-capacitance that bypasses said main charging path for charging an initially discharged S-capacitance during a start-up interval to enable said operation of said deflection amplifier.
2. A deflection circuit according to Claim 1 wherein said auxiliary charging path also bypasses said deflection winding.
3. A deflection circuit according to Claim 2 wherein said S-capacitance is coupled to a terminal of said deflection winding remote from said output terminal.
4. A deflection circuit according to Claim 3 wherein said main current conduction path is a main path of a transistor output stage within said RCA 83,216A
deflection amplifier and wherein said control circuit includes a direct current path for forward base current in said transistor output stage from a DC voltage supply, said direct current path being disabled when said S-capacitance voltage is less than said predetermined magnitude.
5. A deflection circuit according to Claim 4 wherein said direct current path includes a main current path of a semiconductor element, said S-capacitance voltage being applied to said semiconductor element for blocking the main current path thereof when said S-capacitance voltage is less than said predetermined magnitude.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/852,358 US4700114A (en) | 1986-04-15 | 1986-04-15 | Vertical deflection circuit |
| CA000534229A CA1279724C (en) | 1986-04-15 | 1987-04-08 | Vertical deflection circuit |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000534229A Division CA1279724C (en) | 1986-04-15 | 1987-04-08 | Vertical deflection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1290446C true CA1290446C (en) | 1991-10-08 |
Family
ID=25671304
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000615748A Expired - Lifetime CA1290446C (en) | 1986-04-15 | 1990-05-24 | Vertical deflection circuit |
| CA000615747A Expired - Lifetime CA1290445C (en) | 1986-04-15 | 1990-05-24 | Vertical deflection circuit |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000615747A Expired - Lifetime CA1290445C (en) | 1986-04-15 | 1990-05-24 | Vertical deflection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CA (2) | CA1290446C (en) |
-
1990
- 1990-05-24 CA CA000615748A patent/CA1290446C/en not_active Expired - Lifetime
- 1990-05-24 CA CA000615747A patent/CA1290445C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CA1290445C (en) | 1991-10-08 |
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| MKEX | Expiry |