US4675717A - Water-scale-integrated assembly - Google Patents

Water-scale-integrated assembly Download PDF

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US4675717A
US4675717A US06/658,799 US65879984A US4675717A US 4675717 A US4675717 A US 4675717A US 65879984 A US65879984 A US 65879984A US 4675717 A US4675717 A US 4675717A
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Prior art keywords
wafer
assembly
conductive
layer
regions
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US06/658,799
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English (en)
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Victor Herrero
Leonard W. Schaper
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AMERICAN TELEPHONE AND TELEGRAPH COMPANY AT&T BELL LABORATORIES
AT&T Corp
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AMERICAN TELEPHONE AND TELEGRAPH COMPANY AT&T BELL LABORATORIES
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Priority to US06/658,799 priority Critical patent/US4675717A/en
Assigned to BELL TELEPHONE LABORATORIES, INCORPORATED, A NY CORP. reassignment BELL TELEPHONE LABORATORIES, INCORPORATED, A NY CORP. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HERRERO, VICTOR, SCHAPER, LEONARD W.
Priority to PCT/US1985/001910 priority patent/WO1986002490A1/en
Priority to EP85904950A priority patent/EP0197089B1/en
Priority to DE8585904950T priority patent/DE3581535D1/de
Priority to JP60504295A priority patent/JPS62500413A/ja
Priority to CA000492631A priority patent/CA1232364A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Definitions

  • This invention relates to integrated-circuit chips and, more particularly, to an assembly that includes multiple such chips interconnected by means of a multilevel conductive pattern formed on a wafer.
  • WSI wafer-scale-integrated
  • WSI assemblies are potentially faster than approaches based on individually packaged chips mounted and interconnected on a standard printed-circuit board.
  • the size of the chip package limits the density of circuits in a system.
  • unpackaged chips can be packed extremely closed on a single wafer, thus avoiding the major size limitations imposed by package size and thereby enabling faster performance due to substantial decreases in chip interconnection lengths.
  • WSI assemblies can also improve system reliability. This is so because the major failure sites in conventional electronic assemblies are the connections between different packaging levels: for example, between chips and packages, between packages and boards, and between boards and cables. In a WSI assembly, the placement and interconnection of multiple chips on a single wafer in an integrated array greatly reduces the number and type of these interlevel connections.
  • one feasible WSI assembly includes large-area power and ground conductors suitably separated from each other in a common plane in a three-level-metallization structure formed on one surface of the wafer. While not electrically ideal, such a structure is considerably easier and less costly to manufacture than a four-level-metalization one.
  • Virtually all WSI assemblies require decoupling capacitors. It is known to include such a capacitor under or adjacent to each chip on the wafer. For high-speed operation, it is vital that these capacitors be located as close as possible to their respective chips. But even relatively short leads extending between a decoupling capacitor and its associated chip may have sufficient inductance to deleteriously affect the performance of very-high-speed circuits. Additionally, the intrinsic inductance of the multiple individual capacitors also tends to limit the speed of operation of the circuits includes in the WSI assembly.
  • an object of the present invention is an improved WSI assembly. More specifically, an object of this invention is a more simply fabricated and more reliable such assembly characterized by an improved power-ground distribution structure that also enables the attainment in the assembly of an advantageous large-area decoupling capacitor.
  • a specific illustrative embodiment thereof that comprises a silicon wafer that is highly doped to render it relatively conductive.
  • a substantially planar and continuous power metallization layer is formed overlying the top surface of the wafer.
  • a continuous ground metallization layer is formed on the bottom surface of the wafer.
  • Spaced-apart X- and Y-signal metallization layers are then formed overlying the top surface.
  • the resulting WSI assembly thus includes three metallization layers on the top surface of the wafer and one such layer on the bottom surface thereof. Interconnected chips of the assembly are included on the top surface of the wafer.
  • the illustrative assembly also comprises a dielectric layer underlying a major extent of the power metallization layer.
  • the power layer thus constitutes one plate of a wafer-size capacitor.
  • the conductive wafer itself and the bottom-surface ground layer form the other plate of this capacitor.
  • advantageous ground connections are also easily made in the illustrative WSI assembly. This is done, for example, by means of isolated metallic portions of the power layer that are formed directly on the top surface of the wafer. Whenever an electrical connection is made between a pad on the chip and one of these isolated metallic portions, an effective ground connection is thereby made to the pad via the conductive wafer and the bottom-surface ground layer.
  • FIG. 1 is a generalized overall schematic representation of a conventional WSI assembly
  • FIG. 2 schematically depicts a three-layer metallization structure as heretofore proposed for an assembly of the FIG. 1 type
  • FIG. 3 represents a portion of the FIG. 2 assembly in the immediate vicinity of one of the component chips thereof;
  • FIG. 4 shows the details of a portion of a specific illustrative WSI assembly made in accordance with the pinciples of the present invention.
  • FIG. 5 is a generalized overall schematic representation of a larger portion of the FIG. 4 assembly.
  • the conventional WSI assembly represented in FIG. 1 comprises a wafer 10 made of silicon having a thickness t of approximately 500 micrometers ( ⁇ m).
  • the wafer 10 is square, measuring about 7.5 centimeters (cm) on a side.
  • the resistivity of the conventional wafer 10 is relatively high, being, for example, greater than ten ohm-centimeter.
  • each chip 12 is also about 500 ⁇ m thick and is square, measuring about 0.6 cm on a side.
  • a number of known ways are available for incorporating the chips 12 in the assembly depicted in FIG. 1.
  • the particular way that is illustrated in the drawing and that will be emphasized herein involves conventional face-down solder-ball bonding.
  • microminiature solder posts each about 50 ⁇ m high and having a diameter of approximately 125 ⁇ m are utilized to connect bonding pads on the face of each chip to lithographically defined conductors included in a three-level metallization structure 14 (FIG. 1) formed on the top surface of the wafer 10.
  • the WSI assembly shown in FIG. 1 is schematically depicted as being associated with a standard package 16.
  • the package includes instrumentalities (not shown) for making electrical contact with peripheral portions of the metallization structure 14 on the wafer 10.
  • the package also typically includes a suitable heat sinking arrangement for cooling the assembly.
  • the standard metallization structure 14 schematically depicted in FIG. 1 includes three levels suitably insulated from each other.
  • One level which will be described in detail below in connection with FIG. 2, includes spaced-apart planar power and ground conductors.
  • the other two levels respectively contain signal conductors.
  • the signal conductors in one of these levels are all disposed parallel to each other in the X direction, and the conductors in the other level are disposed parallel to each other in the Y direction.
  • These X-signal and Y-signal conductors are, for example, each about 2 ⁇ m thick and 10-to-20 ⁇ m wide.
  • connections are made between selected ones of the X-signal and Y-signal conductors and between selected signal conductors and patterned portions of the power/ground metallization included in the structure 14 of FIG. 1. Interconnections are also formed from these patterned portions and from the power/ground metallization to contact areas in a chip-mounting site.
  • bonding pads on the chip are thereby connected to selected ones of the power, ground, X-signal and Y-signal conductors of the WSI assembly.
  • FIG. 2 shows an illustrative single-level power/ground metallization pattern as heretofore proposed.
  • the pattern includes spaced-apart large-area planar conductors 18 and 20.
  • the conductor 18 comprises the power conductor of the depicted WSI assembly and the conductor 20 comprises the ground conductor of the assembly.
  • portions of these power and ground conductors surround each of nine mounted chips 21 through 29.
  • Two X-signal leads which are formed in a metallization level that overlies the aforedescribed power/ground level are schematically represented in FIG. 2 by dashed lines 30 and 31.
  • two Y-signal leads which are formed in yet another overlying metallization level are depicted in FIG. 2 by dashed lines 32 and 33.
  • the conductor 20 is connected to a point of reference potential such as d-c ground.
  • the conductor 18 is connected to a positive (or negative) potential with respect to ground. But, since the conductor 18 is also typically connected to ground via decoupling capacitors, the conductor 18 is in effect thereby maintained at a-c ground.
  • the signal leads 30 through 33 should overlie a continuous ground plane. In such an ideal structure, signals propagated in the leads 30 through 33 are minimally distorted.
  • the representative signal leads 30 through 33 of the actual depicted WSI assembly overlie discontinuities in the underlying metallization level that includes the power and ground conductors 18 and 20. With respect to the signal lead 33, for example, these discontinuities occur at breaks in the underlying metal. These break points are identified in FIG. 2 by reference numerals 34 through 43. Because of these and similar discontinuities in the underlying metallization, signals propagated in the X and Y leads represented in FIG. 2 suffer distortion. In some systems, this distortion may be sufficient to deleteriously affect the desired operation thereof.
  • FIG. 3 shows portions of the power and ground conductors 18 and 20 in the immediate vicinity of the mounted chip 22 of FIG. 2.
  • FIG. 3 represents a decoupling capacitor underlying the chip 22. This capacitor is shown in dashed outline and designated by reference numeral 44.
  • One way of achieving the decoupling capacitor 44 is to form two metal plates under the ship 22 separated by a dielctric layer of silicon dioxide, tantalum oxide, or other suitable dielectric. (By way of illustrative example herein, a single layer of silicon dioxide will be specified.) Alternatively, the bottom plate of such a capacitor may be formed by suitably doping a localized portion of the underlying wafer. In either case, the silicon dioxide thickness required to realize the required decoupling capacitance in such a small-area capacitor is typically only about 400 Angstrom units ( ⁇ ).
  • each under-chip decoupling capacitor it is necessary in a standard WSI assembly of the type described herein to connect the plates of each under-chip decoupling capacitor to the adjacent power and ground conductors of the assembly.
  • multiple leads are lithographically defined to connect the respective plates of the capacitor 44 to the power and ground conductors 18 and 20.
  • leads 46 through 48 connect one plate of the capacitor 44 to the power conductor 18, and leads 50 through 52 connect the other plate of the capacitor to the ground conductor 20.
  • the inductance of even relatively short leads such as the leads 46 through 48 and 50 through 52 of FIG. 3 can be limiting in a high-performance WSI assembly.
  • the inductance of these leads can impose an undesirable limit on the high-speed operating capabilities of the assembly.
  • FIG. 4 shows a portion of a specific illustrative WSI assembly made in accordance with the principles of the present invention. As will be described in detail below, this illustrative assembly is characterized by several significant and advantageous properties compared to the standard assembly described above and shown in FIGS. 1 through 3.
  • the FIG. 4 assembly comprises a square single-crystal silicon wafer 54 about 500 ⁇ m thick and measuring approximately 7.5 cm on a side.
  • the wafer 54 is highly doped to render it relatively conductive.
  • the wafer 54 is doped with an n-type impurity such as arsenic to a level of approximately 10 19 atoms per cubic centimeter.
  • this doping is done at the time of forming the silicon ingot from which the wafer is subsequently cut.
  • Such doping imparts a relatively low resistivity of approximately 0.006 ohm-centimeter to the wafer 54.
  • wafer resistivities less than approximately 0.01 ohm-centimeter will suffice for many applications.
  • a conductive layer 56 such as a 2- ⁇ m-thick layer of aluminum is deposited on the entire bottom surface of the wafer 54 of FIG. 4.
  • the planar layer 56 functions as a continuous ground conductor for the depicted assembly and, additionally, constitutes a part of one plate of a wafer-size decoupling capacitor included in the assembly.
  • the metallic layer 56 (FIG. 4) is deposited on the bottom surface of the wafer 54 during the same processing step in which a layer of the same material and thickness is being deposited on or overlying the top surface of the wafer 54.
  • the aforementioned 2- ⁇ m-thick aluminum layer 56 is deposited at the same time that layer 58 of the assembly is being deposited.
  • the layer 58 constitutes a large-area planar power conductor. The planar nature of the power conductor is typically interrupted only in regions immediately under mounted chips or in regions directly adjacent thereto, as will be evident from the description later below.
  • the layers 56 and 58 are deposited at the same time and on opposite sides of the wafer 54, the likelihood of bowing occurring in the wafer 54 during or after deposition is substantially reduced.
  • This advantageous result stems from the fact that the layers 56 and 58 subject the wafer 54 to forces that tend to counterbalance each other. As a result, no net force or no appreciable net force acts to distort the planar top surface of the wafer 54.
  • a dielectric layer 60 comprising, for example, a 1500- ⁇ -thick layer of thermally grown silicon dioxide directly underlies a major extent of the conductive layer 58. Because of its relative thickness (compared, for example, to 400 ⁇ ) the layer 60 constitutes an excellent virtually pin-hole-free dielectric.
  • the layer 60 of FIG. 4 comprises the dielectric of a large-area decoupling capacitor whose upper plate is the power conductor 58.
  • the lower plate of this capacitor includes the highly doped wafer 54 and the ground conductors 56.
  • the large-area nature of this capacitor permits the dielectric layer to be relatively thick (1500 ⁇ ) while the structure still achieves the required large value of decoupling capacitance.
  • the aforedescribed capacitor is distributed over virtually the entire extent of the wafer 54 of FIG. 4.
  • the power conductor 58 extends, there is formed an underlying decoupling capacitor.
  • decoupling capacitance is connected directly to the pad at the same time.
  • FIG. 4 wherein solder balls 62 and 64 are shown interposed between pads on chip 66 and portions of the power conductor 58.
  • solder balls 62 and 64 are shown interposed between pads on chip 66 and portions of the power conductor 58.
  • the only “leads" between the pads and the aforedescribed wafer-size capacitor are the solder balls themselves which inherently possess very little inductance.
  • the magnitude of the fringing fields of such a large-area capacitor is less than that of the fields associated with multiple discrete small-area capacitors of the type heretofore proposed.
  • the depicted capacitor exhibits advantageous high-speed characteristics.
  • lithographically defined interruptions in the power conductor 58 of FIG. 4 occur directly under the chip 66.
  • One such type of interruption is made to achieve ground connections between pads on the chip 66 and the ground conductor 56.
  • a portion of the dielectric layer 60 is removed from the top surface of the wafer 54 before the power conductor layer is deposited thereon.
  • the power conductor layer is patterned to provide isolated metallic regions such as region 68.
  • solder ball 70 is effective to connect a mating pad on the chip 66 to ground in an effective relatively low-inductance manner. In practice, multiple such ground connections are made between each chip and the ground conductor 56.
  • each ground connection such as the region 68 of FIG. 4 is designed to have a relatively large-area top surface measuring about 1.25 mm on a side. As a result, the resistance measured between the region 68 and the ground conductor 56 is relatively low (in one specific example, only about 19 milliohms). Additionally, since, as mentioned above, each chip typically includes multiple such ground connections, the net overall resistance of multiple parallel ground paths through the wafer 54 to the bottom-surface conductor 56 is many times lower. In one specific illustrative example in which eight such ground connections are provided to each chip, the net resistance between the ground connections associated with each chip and the bottom-surface conductor 56 measures only about 2.4 milliohms.
  • doping levels other than the one specifically mentioned above can impart the requisite electrical characteristic to the wafer 54 of FIG. 4.
  • the significant requirement is that the wafer 54 be doped to be sufficiently conductive to constitute an effective power supply connection between conductive connections on the top surface of the wafer and the bottom-surface conductor 56.
  • the requisite conductivity of such an interconnection is in turn a function of such factors as the particular technology from which the chips of the WSI assembly is made, the required noise margins of the chip circuits, the specified operating power levels of the chip circuits, etc. It can be appreciated that it is feasible also simply to dope heavily only selected portions of the wafer to permit high conductivity between metallic regions 68 and the bottom surface layer 56 in those instances where for some reasons it is desirable to limit the conductivity of portions of the wafer 54.
  • FIG. 4 Another type of lithographically defined interruption in the deposited power conductor layer is represented in FIG. 4. This type of interruption provides isolated metallic regions on the dielectric layer 60. These regions are the instrumentalities by which X- and Y-signal leads are connected to bonding pads on the mounted chips. One such region 72 is shown in FIG. 4.
  • FIG. 4 also shows one conductor 74 of multiple X-signal leads and one conductor 76 of multiple Y-signal leads included in the illustrative WSI assembly.
  • these leads are lithographically defined in a conductive material such as aluminum.
  • Each such lead is typically about 2 ⁇ m thick and 10-to-20 ⁇ m wide.
  • a dielectric layer 78 (FIG. 4) is interposed between the X-signal leads including the conductor 74 and the conductive layer that includes the regions 58, 68 and 72. Further, another dielectric layer 80 isolates the X-signal metallization level from the Y-signal metallization level.
  • each of these dielectric layers comprises a 5-to-20 ⁇ m-thick layer of polyimide material. Such a relatively thick low-dielectric-constant material ensures that the X- and Y-signal leads have relatively low values of parasitic capacitance associated therewith. Significantly, this enhances the high-speed performance characteristics of the unique depicted assembly.
  • the Y-signal conductor 76 is shown connected by a metallic via 82 to the X-signal conductor 74.
  • the conductor 74 is connected to the region 72 by a conductive portion 84.
  • solder ball 86 connects the region 72 to a specified one of the bonding pads included on the chip 66.
  • a significant advantage of the specific illustrative FIG. 4 assembly is that the signal leads thereof are designed wherever possible to overlie uninterrupted portions of the large-area conductor 58 which therefore constitutes in effect a continuous a-c ground plane. As a result, signals propagated in these overlying leads are minimally distorted.
  • FIG. 4 also schematically indicates that the depicted WSI assembly includes input/output terminals.
  • One such illustrative terminal 87 overlying insulating layer 91 is shown disposed along one edge of the assembly.
  • the WSI assembly can be connected to other such assemblies and/or to other equipment included in a system configuration.
  • the illustrative structure schematically represented in FIG. 4 constitutes only a one-chip portion of an overall WSI assembly made in accordance with the principles of the present invention. In some applications of practical importance, as many as 100 chips are mounted and interconnected in such an assembly.
  • the chips in a particular assembly may comprise only bipolar devices, metal-oxide-semiconductor (MOS) devices, complementary-MOS devices, laser devices, integrated-optical devices, etc., or a mixture of some or all of such different devices.
  • MOS metal-oxide-semiconductor
  • FIG. 5 illustrates an inventive assembly that includes three chips 88 through 90.
  • Layer 92 schematically represents the particular three-level metallization described above in connection with FIG. 4.
  • Wafer 94 is indicated by dots as being relatively highly doped, as specified above.
  • layer 96 represents applicants' unique bottom-surface ground conductor.
  • the entire WSI assembly is schematically depicted as being supported on a base member 98 which is part of a package that includes, for example, contacting and cooling capabilities.
  • the above-described structures and techniques are only illustrative of the principles of the present invention.
  • numerous modifications and alternatives may be devices by those skilled in the art without departing from the spirit and scope of the invention.
  • the chips may be mounted face-up on a wafer and connections made between the chips and the wafer by standard wire-bonding or tape-automated-bonding techniques.
  • the chips may be mounted in sloped-wall recesses formed in the wafer or may be fabricated as integral parts of the wafer itself. In these latter cases, the connections between the chips and the metallization pattern on the wafer may be lithographically formed.
  • the bottom-surface conductor of the assembly as a power plane and to utilize the large-area metallization on and overlying the top surface of the wafer as a ground plane.
  • silicon constitutes a particularly advantageous material from which to fabricate the herein-considered WSI assemblies
  • other avilable materials can be used as the basis for making assemblies of the type specified.
  • Gallium arsenide for example, constitutes one such attractive alternative material.
  • the conductor 56 (FIG. 4) be formed on the bottom surface of the wafer 54
  • inventive principles also encompass the case in which the conductor 56 is formed instead directly on the top surface of the wafer.
  • the remainder of the structure overlying such a top-surface conductor is the same as described above and shown in FIG. 4 with a dielectric layer 60 separating the top-surface layer 56 from layer 58.
  • Such an alternative structure also provides a readily accessible large-area decoupling capacitor in a WSI assembly.
  • dielectric materials or combinations of dielectric materials other than those specifically mentioned above may be utilized to form the layers 60, 78, 80 and 91 of the assembly shown in FIG. 4.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US06/658,799 1984-10-09 1984-10-09 Water-scale-integrated assembly Expired - Lifetime US4675717A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US06/658,799 US4675717A (en) 1984-10-09 1984-10-09 Water-scale-integrated assembly
PCT/US1985/001910 WO1986002490A1 (en) 1984-10-09 1985-09-30 Wafer-scale-integrated assembly
EP85904950A EP0197089B1 (en) 1984-10-09 1985-09-30 Wafer-scale-integrated assembly
DE8585904950T DE3581535D1 (de) 1984-10-09 1985-09-30 Integrierter zusammenbau auf einer halbleiterscheibe.
JP60504295A JPS62500413A (ja) 1984-10-09 1985-09-30 ウエ−ハ　スケ−ル集積アセンブリ
CA000492631A CA1232364A (en) 1984-10-09 1985-10-09 Wafer-scale-integrated assembly

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US06/658,799 US4675717A (en) 1984-10-09 1984-10-09 Water-scale-integrated assembly

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US4675717A true US4675717A (en) 1987-06-23

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US (1) US4675717A (enrdf_load_stackoverflow)
EP (1) EP0197089B1 (enrdf_load_stackoverflow)
JP (1) JPS62500413A (enrdf_load_stackoverflow)
CA (1) CA1232364A (enrdf_load_stackoverflow)
DE (1) DE3581535D1 (enrdf_load_stackoverflow)
WO (1) WO1986002490A1 (enrdf_load_stackoverflow)

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US5825092A (en) * 1996-05-20 1998-10-20 Harris Corporation Integrated circuit with an air bridge having a lid
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US5811868A (en) * 1996-12-20 1998-09-22 International Business Machines Corp. Integrated high-performance decoupling capacitor
US6462976B1 (en) 1997-02-21 2002-10-08 University Of Arkansas Conversion of electrical energy from one form to another, and its management through multichip module structures
US6226863B1 (en) 1997-06-20 2001-05-08 International Business Machines Corporation Reworkability method for wirebond chips using high performance capacitor
US6015955A (en) * 1997-06-20 2000-01-18 International Business Machines Corporation Reworkability solution for wirebound chips using high performance capacitor
US6518112B2 (en) 1998-01-05 2003-02-11 International Business Machines Corporation High performance, low power vertical integrated CMOS devices
US6426530B1 (en) 1998-01-05 2002-07-30 International Business Machines Corporation High performance direct coupled FET memory cell
US6137129A (en) * 1998-01-05 2000-10-24 International Business Machines Corporation High performance direct coupled FET memory cell
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US6707680B2 (en) 1998-10-22 2004-03-16 Board Of Trustees Of The University Of Arkansas Surface applied passives
US6169833B1 (en) 1999-01-22 2001-01-02 Lucent Technologies Inc. CMOS-compatible optical bench
US6300677B1 (en) * 1999-08-31 2001-10-09 Sun Microsystems, Inc. Electronic assembly having improved power supply bus voltage integrity
US6404615B1 (en) 2000-02-16 2002-06-11 Intarsia Corporation Thin film capacitors
US7081671B2 (en) * 2000-05-25 2006-07-25 Mitsubishi Denki Kabushiki Kaisha Power module
US6486530B1 (en) 2000-10-16 2002-11-26 Intarsia Corporation Integration of anodized metal capacitors and high temperature deposition capacitors
US20030173672A1 (en) * 2001-12-18 2003-09-18 Tomoyuki Furuhata Semiconductor devices and methods for manufacturing the same
US20040226735A1 (en) * 2003-05-12 2004-11-18 Ping Wu Method and apparatus for integrated noise decoupling
US7425760B1 (en) 2004-10-13 2008-09-16 Sun Microsystems, Inc. Multi-chip module structure with power delivery using flexible cables
US20090289354A1 (en) * 2008-05-20 2009-11-26 Infineon Technologies Ag Electronic module
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JPH0418471B2 (enrdf_load_stackoverflow) 1992-03-27
JPS62500413A (ja) 1987-02-19
DE3581535D1 (de) 1991-02-28
WO1986002490A1 (en) 1986-04-24
EP0197089A1 (en) 1986-10-15
CA1232364A (en) 1988-02-02
EP0197089B1 (en) 1991-01-23

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