US4091338A - Crystal oscillator implemented with CMOS technology - Google Patents

Crystal oscillator implemented with CMOS technology Download PDF

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US4091338A
US4091338A US05/760,522 US76052277A US4091338A US 4091338 A US4091338 A US 4091338A US 76052277 A US76052277 A US 76052277A US 4091338 A US4091338 A US 4091338A
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amplifier
output
input
resistor
voltage
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Mitsuo Morihisa
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Sharp Corp
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Sharp Corp
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Priority claimed from JP3004176A external-priority patent/JPS52113143A/ja
Priority claimed from JP8323876A external-priority patent/JPS538549A/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F5/00—Apparatus for producing preselected time intervals for use as timing standards
    • G04F5/04—Apparatus for producing preselected time intervals for use as timing standards using oscillators with electromechanical resonators producing electric oscillations or timing pulses
    • G04F5/06—Apparatus for producing preselected time intervals for use as timing standards using oscillators with electromechanical resonators producing electric oscillations or timing pulses using piezoelectric resonators

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  • the present invention relates to CMOS amplifiers useful for crystal oscillators.
  • CMOS analog amplifier as illustrated in FIG. 1 was employed as an amplifier in crystal oscillators for a variety of electronic apparatus for example solid state wristwatches to fulfill low power consumption requirements.
  • the amplifier includes a basic inverter consisting of a P-channel MOS transistor P and an N-channel MOS transistor N, and a resistor R f of a high resistance value connected between an input terminal V in and an output terminal V out of the complementary MOS inverter for biasing purposes.
  • the circuit exhibits high gain, low power dissipation performance characteristics while keeping a simplicity in circuit construction.
  • FIG. 2 depicts interrelation among an input voltage V in , an output voltage V out , output impedance R out , current I c flowing through P- and N-MOS transistors when supplied with a voltage (V DD - V SS ), which occur within the CMOS analog amplifier of FIG. 1.
  • the graph (I) in FIG. 2 shows a V in - V out characteristic of a conventional CMOS transistor, indicating that V in is biased at the substantially same as V out via the bias resistor R f and thus the CMOS operating center V coc is given.
  • the graph (II) shows the dependency of the output impedance R out upon variations in the output voltage V out , indicating that R out tends to take a maximum at the operating center V coc and reduce when the power supply potential approximates either V DD or V SS .
  • Analysis of the graph (II) also reveals the fact that a reduction in the power supply voltage (V DD - V SS ) and a temperature rise permit the output impedance R out to be increased as suggested by the curves (1) and (2).
  • the graph (III) shows variations in the current I c flowing through the CMOS when supplied with (V DD - V SS ), as a function of the input potential V in . While the current I c has a peak at the operating center, the same is correspondingly reduced in accordance with a degree of deviation from the operating center V coc .
  • FIG. 3 shows an example wherein the above discussed type of the amplifier is applied to timekeeping crystal oscillators whose frequency is about 32.768 KHz.
  • a quarts oscillator is denoted as X and phase shifting or frequency adjustment capacitors are denoted as C 1 and C 2 .
  • the crystal impedance value (hereinafter referred to as (I) of the quarts oscillator X is relatively small (typically, in the order of several tens K ⁇ )
  • the crystal oscillator of FIG. 3 is satisfactory for practical use of timekeeping devices.
  • the critical conditions for practical use of timekeeping devices are that regulation of oscillation frequency for power supply voltage ⁇ f/f.V is below 1.0 sec/day.V, dissipation of current under voltage supply of 1.6V is below 5 ⁇ A, lowest oscillation initiating voltage is below 1.4V and oscillation initiating period is within 8 seconds.
  • the circuit of FIG. 1 can fulfill these requirements no longer. In the event that CI is several hundred K ⁇ , oscillation itself will be very difficult. It is deemed that this is caused by the above disadvantages mentioned with respect to the CMOS analog amplifier of FIG. 1.
  • the difficulty in reducing the output impedance Romax in the vicinity of the operating center V coc means particularly that a period of time required for initiating oscillation is considerably longer because it is difficult to excite the quartz oscillator when initiating oscillation,.
  • the difficulty in reducing the average of the output impedance R out implies an increase in the oscillation initiating voltage.
  • FIG. 1 is a circuit diagram of a prior art CMOS analog amplifier
  • FIG. 2 is a graph showing the operating characteristics of the analog amplifier of FIG. 1;
  • FIG. 3 is a circuit diagram of an example of applications of the analog amplifier of FIG. 1;
  • FIG. 4 is a circuit diagram of one preferred form of an analog amplifier constructed in accordance with the present invention.
  • FIG. 5(a), 5(b), 5(c) and 5(d) are circuit diagrams of examples of the essential implementations of the circuit of FIG. 4;
  • FIG. 6 is a graph showing operating characteristics of the example shown in FIG. 5(a);
  • FIG. 7 is a circuit diagram of another preferred form of the present invention.
  • FIG. 8 is a graph showing operating characteristics of the circuit of FIG. 7 for illustration of operation
  • FIG. 9 is a circuit diagram of an example of application of the present invention.
  • FIG. 10 is a graph showing operating characteristics of the embodiment of FIG. 7;
  • FIG. 11 is a circuit diagram of still another preferred form of the present invention.
  • FIG. 12 is a circuit diagram of another preferred form of the present invention.
  • FIG. 13 is a circuit diagram of a resistor load MOS amplifier
  • FIG. 14 is a graph showing operating characteristics of the amplifier of FIG. 13;
  • FIG. 15 is a circuit diagram of one preferred form of the present invention utilizing the resistor-loaded MOS amplifier
  • FIG. 16 is a circuit diagram of another preferred form of the present invention utilizing the resistor-loaded MOS amplifier
  • FIG. 17 is a graph of characteristic curves for the purpose of illustration of operation of the embodiments of FIGS. 15 and 16;
  • FIG. 18 is a circuit diagram of a multi-stage amplifier utilizing the portion of the circuit of FIG. 16;
  • FIG. 19 is a circuit diagram of an oscillator utilizing the multi-stage amplifier of FIG. 18;
  • FIG. 20 is a graph showing frequency characteristic of the amplifier of FIG. 9;
  • FIG. 21 is a circuit diagram of one preferred form of the present invention effective to improve the frequency characteristic of FIG. 20;
  • FIG. 22 is a circuit diagram of an oscillator incorporating the embodiment of FIG. 21 thereinto.
  • FIGS. 23 and 24 are graphic representations of operating characteristics of the circuit of FIG. 22.
  • FIG. 4 of the drawings illustrates a basic construction of an amplifier embodying the present invention.
  • a CMOS analog amplifier having high gain and low power consumption properties as briefly described above is provided at its output with an impedance converter IC which has generally a considerably higher input impedance and a considerably lower output impedance, for the purposes of reducing the output impedance of the CMOS analog amplifier.
  • the resulting circuit arrangement assures low output impedance and low power consumption while keeping the high gain properties of the CMOS scheme.
  • the impedance converter IC may take a variety of forms some of which are shown in FIGS. 5(a) through 5(d).
  • CMOS complementary metal-oxide-semiconductor
  • a MOSFET follower as suggested in FIG. 5(a) is most beneficial because of its simplicity of integrated circuit manufacture.
  • a junction type FET of FIG. 5(b), bipolar transistors of FIGS. 5(c) and 5(d) may be equally applicable.
  • the output impedance of the CMOS analog amplifier is considerably high, it is recommended that the input impedance of the impedance converter IC is as high as possible.
  • the emitter follower of FIG. 5(c) ⁇ is as high as possible.
  • Darlington Connection may be applied.
  • super- ⁇ transistors may be employed.
  • Other elements may be employed as far as they do not interfere with the performances of the impedance converter.
  • P-channel or N-channel enhancement mode transistors or depletion mode transistors are optionally selectable.
  • bipolar transistors either PNP type or NPN transistors may be useful.
  • FIGS. 5(a) through 5(d) there is provided a resistor R as a passive element at their output portions. This follows that variations in the output impedance due to variations in power supply voltage and temperature are greatly reduced as compared with the circuit of FIG. 1 wherein the output impedance is established by only passive elements.
  • the output impedance itself may be optionally determined by the resistor R and gm of the transistors. However, in determining and more particularly reducing the output impedance, care must be taken not to increase current consumption.
  • FIG. 6 illustrates correlation among input voltage V in ', output voltage V out , output impedance R out , current I f flowing through the MOSFET and the resistor R when supplied with power voltage V DD - V SS , etc.
  • the graph (I) shows V in ' versus V out characteristic of a MOSFET follower.
  • the presence of the threshold voltage V th inherent to the MOSFET's develops no output V out while the input V in ' changes from V ss to V th .
  • the gain should not be more than 1 from the viewpoint of the operating principle of the follower amplifier. In other words, the maximum of the output V out never reaches V DD in contrast with the CMOS scheme.
  • the graph (II) indicates the development of the output impedance R out of the MOSFET follower as a function of variations in the output potential V out . Since the MOSFET is in the pinch off state before the input V in ' changes from V ss to V th , the output impedance R out is the very output resistor R. As the input V in ' exceeds the voltage V th and advances toward the voltage V DD , the ON resistor of the MOSFET is correspondingly reduced, thereby accomplishing a reduction of the output impedance R out .
  • the curve (1) represents the output impedance R out when power supply voltage V DD - V SS and at room temperature
  • the curve (2) represents the same when power supply voltage lower than V DD - V SS and at a higher than room temperature. It will be clear from the curves that the output impedance in the case (2) is higher than in the case (1).
  • the graph (III) depicts the current I F flowing across the power terminals V DD and V SS of the MOSFET follower when supplied with V DD - V SS , as a function of the input potential V in '. Since the MOSFET is in the pitch off state to permit little or no current I F till the input V in ' reaches the voltage V th . However, when the input V in ' is increased beyond the voltage V th to approach the voltage V DD , the ON resistor of the MOSFET is decreased and the current I F is increased.
  • FIG. 7 An amplifier arrangement which employs as a buffer means for the CMOS analog amplifier the MOSFET follower having the above discussed properties, is illustrated in FIG. 7.
  • An N-channel MOSFET forming the follower circuit is denoted as N'. While the output terminal of the CMOS analog amplifier is commonly connected to the input terminal of the next succeeding stage MOS follower, both are respectively denoted as V out , V in ' for the sake of explanation only.
  • a total of the consumption current I c of the CMOS analog amplifier and the consumption current I F of the MOS follower is denoted as I T .
  • FIG. 8 illustrates some of the operating characteristics of the CMOS analog amplifier.
  • the graph (I) depicts relationship between the input potential V in and the output potential V out '; the graph (II) depicts relationship between the input potential V in ' and the output potential V out within the MOS follower; the graph (III) depicts relationship between the output potential V out and the output impedance R out ; and the graph (IV) depicts relationship between the input potential V in and the consumption current I c and I F and the total consumption current I T .
  • These graphs are provided for comparison between the basic CMOS amplifier of FIG. 2 and the MOSFET follower of FIG. 6.
  • the circuit of FIG. 7 is effective in a field wherein the output impedance R out at the operating center should be low.
  • the only way to reduce the output impedance is to increase gm of the P- and N-MOS transistors or to decrease V th . This results in an increase in consumption current.
  • the output impedance of the CMOS amplifier may be so sufficiently high as not to disturb the frequency characteristic thereof.
  • the characteristics as suggested by the curve (2) of the graph (III) and the curve (4) of the graph (IV) may be employed. In other words, it is easy not to decline the voltage gain even if P- and N-MOS transistors within the CMOS scheme assume smaller gm. This enables the consumption current I c in the CMOS amplifier region to be largely reduced.
  • the output impedance R out of the MOS follower circuit is scarcely varied due to variations in the input and output potentials, the power supply voltage, temperature, etc.
  • the curve (6) in the graph (IV) of FIG. 8 illustrates changes in the consumption current I F in the MOS follower circuit as a function of changes in the input potential V in .
  • V in ' approaches V DD through V th I F is increased.
  • a voltage V s means the input voltage V in of the CMOS amplifier sufficient to permit the output voltage V out , of the CMOS amplifier to continue saturating at the voltage V DD .
  • a voltage V thin means the input voltage V in of the CMOS amplifier sufficient to permit the input potential V in ' of the MOS follower to reach the voltage V th .
  • the current I F is increased as the voltage changes from the voltage V thin to the voltage V s . But, I F becomes fixed during transition from V s to V ss . If variations in the consumption current I c responsive to variations in the input voltage V in are assumed to describe the curve (4) in the graph (IV) of FIG. 8, the total consumption current I T will I F + I c as viewed from the curve (7).
  • the amplifier embodying the present invention when the amplifier embodying the present invention is combined with quartz oscillators of higher CI in crystal oscillators for solid state timekeeping devices, the amplifier gives excellent oscillation characteristics. More particularly, it is possible to reduce the oscillation initiating duration, the oscillation initiating voltage and oscillating frequency deviation and power consumption. In addition, signals of large amplitude are obtainable through the utilization of the output terminal V out ' to assure a simplicity in a next succeeding stage pulse re-shaping circuit.
  • FIG. 9 is an example wherein excitation of the crystal oscillator having requirement for lowered output impedance is through the output V out of the MOS follower and signal stretching is through the output V out ' of the CMOS amplifier. The output is re-shaped easily by introduction into a CMOS re-shaping circuit I n .
  • the quartz oscillator is excited by the CMOS amplifier without using the MOS follower, the following unfavorable results are given: the consumption current is 5.8 ⁇ A; the oscillation initiating duration is over 40 sec.; the oscillation initiating voltage is 1.6V; the frequency deviation is 2.5 sec/day V.
  • Input-output waveform characteristics of the MOS follower stage when biased via the R f are illustrated in FIG. 10, wherein the curve (A) represents relationship between the follower input voltage V in ' and the follower output voltage V out in case where the threshold voltage V th of the MOS transistor N' of FIG. 7 can not be ignored as compared with the power supply voltage V DD - V SS .
  • the curve (B) is viewed in case where the threshold voltage V th is extremely low as compared with the power voltage V DD - V SS or zero.
  • the operating center of the output V out is V FOC ' when the input of the MOS follower is biased with the voltage (V DD - V SS /2) via R f within the CMOS amplifier.
  • the input V in ' takes the signal waveform (1)
  • the output V out will take the somewhat disturbed waveform (2).
  • the waveform of the output V out contains little distortion.
  • the MOS follower as shown by the curve (B) intends to increase the consumption current.
  • the CMOS amplifier and the MOS follower are AC coupled through a capacitor C as suggested in FIG. 11.
  • the source follower input V in ' is biased with (V DD - V th /2) to attain the waveform (5) containing little distortion.
  • V out has the operating center V FOC ".
  • FIG. 13 Another approach to reduce and stabilize the output impedance without a considerable large reduction in the consumption current is suggested in FIG. 13 showing employment of a resistor-load MOS amplifier.
  • FIG. 14 illustrates the output potential V out , the output impedance R out , the current I L flowing through N-channel MOS transistor N and the resistor R, etc., as a function of the input potential V in .
  • the graph (I) in FIG. 14 represents the V in - V out characteristics of the resistor-load amplifier. Due to the presence of the threshold voltage V th inherent to the MOS transistors, the output potential V out remains unchanged at V DD till the input potential V in changes from V ss to V th . However, during voltage transition from V th to V IS the output potential V out is greatly varied from V DD to V OS . As well, during transition from V IS to V DD the output potential V out is held at the saturated value V OS .
  • the graph (II) shows the development of the output impedance R out as a function of variations in the output potential V out .
  • the curve (1) in the graph (II) shows the output impedance R out under the power supply voltage V DD - V SS and at room temperature
  • the curve (2) shows the same under the conditions where the power supply voltage is lower than V DD - V SS and the circumambient temperature is higher than room temperature.
  • the graph (III) shows the current I L flowing across the power supply terminals V DD and V SS of the resistor-load MOS amplifier when supplied with V DD - V SS , as a function of the input potential V in . Since the MOS transistor is at the pinch off state when the input potential V in is varied from V SS to V th , no current I L flows. But, as the input potential V in is increased via V th to V IS , the ON resistor of the MOS transistor is reduced to thereby increase the current I L . If V IS is exceeded, the current I L is saturated at I LS .
  • the amplifier of FIG. 13 supplies current through the load resistor R when its active elements are at the ON state.
  • the output impedance R out is formed by the constant resistor R and the MOS transistor N.
  • the number of the MOS transistors as the active elements is reduced from two to one such that variations in the output impedance R out due to the input and output voltage levels, the power supply voltage and the temperature are further minimized.
  • FIG. 15 is one preferred form of the present invention which is predicated upon a combination of the complementarily coupled transistor amplifier and the above discussed resistor-load transistor amplifier; in accordance with the former amplifier, while the output impedance is relatively high and its variations due to the input and output levels and the power supply voltage are relatively large, the voltage gain is high and the input impedance is high; in accordance with the latter amplifier, as described with respect to FIGS. 13 and 14, the input impedance is high but the output impedance is relatively low and its variations due to the input and output levels and the power supply voltage also is relatively low.
  • the embodiment of FIG. 15 comprises a CMOS amplifier 1 including a P-channel MOS transistor P, an N-channel MOS amplifier N and a bias resistor R f provided between its input and output, and a resistor-load MOS amplifier 2 of which the load resistor R is is connected to the drain of the N-channel MOS transistor N, the output node of the CMOS amplifier 1 being connected to the input node of the resistor-load MOS amplifier 2.
  • the input node of the resistor-load MOS amplifier 2 is biased.
  • DC level is cut via a capacitor C and a resistor R f ' establishes self biasing as suggested in FIG. 16.
  • FIG. 17 illustrates various characteristics for the purpose of explanation of operation of the circuits shown in FIGS. 15 and 16.
  • the graph (I) represents relationship between the input potential V in ' and the output potential V out ' within the CMOS amplifier 1;
  • the graph (II) represents relationship between the input potential V in and the output potential V out within the resistor-load MOS amplifier 2;
  • the graph (III) represents relationship between the output potential V out and the output impedance R out ;
  • the operating center of the resistor-load MOS amplifier 1 is somewhat shifted depending upon whether the DC coupling of FIG. 15 or the AC coupling of FIG. 16 is employed. Such fact is depicted on the graphs (II) and (III) in FIG. 17. A shows the operating center in case of the DC coupling while B shows the same in case of the AC coupling.
  • the output potential V out and the output impedance R out are constant till the input potential V in ' is varied from V DD to V thin .
  • the consumption current I I of the resistor-load MOS amplifier 2 is zero and hence the total consumption current I T is only the consumption current I c of the CMOS amplifier.
  • the output potential V out is approximately equal to V OS and the output impedance R out is gradually decreased to the resistance R S during the period where the input V in ' is advanced from V thin toward V ISN . Simultaneously, the consumption current I I and in other words I T are increased.
  • the CMOS amplifier 1 may be provided in a multi-stage fashion. In case where the number of the amplifier stages is an even number, inversion is developed between the input V in and the output V out .
  • the respective ones of the CMOS amplifiers are AC coupled via a series of capacitors C, C',. . . C (n-1).
  • CMOS amplifier 1 is provided and the output V out of the resistor-load MOS amplifier 2 is employed to excite the quartz oscillator X.
  • FIG. 20 (a) represents the frequency characteristic of the CMOS amplifier and (b) represents the counterpart of the resistor-load amplifier, wherein the input signal is 10 mVp-p, the voltage supply is 3.0V and the output floating capacitance is 8 pF.
  • the voltage gain is about 130 at a low frequency range but only 1.8 in the vicinity of the oscillating frequency of the quartz oscillator X (i.e., 32.768 KHz).
  • the voltage gain is about 40 at a low frequency range and about 3.6 in the vicinity of the oscillating frequency 32.768 KHz.
  • the resistor-load amplifier therefore, manifests the better frequency characteristics although the current consumption is equal.
  • the gain within the DC and low frequency region is lower for the resistor-load amplifier, a multi-stage arrangement of the resistor-load amplifier is possible in principle.
  • FIG. 21 is an example of a two-stage direct coupling resistor-load amplifier. Detailed analysis of the bias characteristics of the resistor-load amplifier of FIG. 21 is as follows.
  • Biasing is basically accomplished by the resistor R f provided between the drain and the gate of the first stage MOS transistor M 1 . Therefore, when the input and output potentials of the transistor M 1 are respectively V in1 and V out1 .
  • the first stage amplifier biased via the bias resistor R f provides the output potential which is determined by V th1 of the MOS transistor M 1 , K 1 , the load resistor R 1 and the power supply voltage V DD without regard to R f .
  • K 2 is the constant of the MOS transistor M 2
  • V th2 is the threshold voltage of M 2
  • R 2 is the load resistor.
  • FIG. 22 shows an application to an oscillator containing a quartz oscillator of higher CI.
  • a quartz enabling stage CD consisting of a load resistor R 3 and a MOS transistor M 3 serves to excite a quartz current CC. Biasing is accomplished by R f '.
  • a pre-amplifier PA as suggested by FIG. 21 is coupled via a capacitor C 03 with the quartz enabling stage CD.
  • FIG. 23 illustrates deviation sec/day and a period of time required for initiating oscillation tosc as a function of the power supply voltage V ss and external capacitors C 1 and C 2 .
  • the greater the deviation the greater the capacitors C 1 and C 2 .
  • the most favorable results are obtained at 0-0.5 S/D ⁇ V out .
  • the period t osc takes a minimum (shorter than 1.0 sec.).
  • FIG. 24 depicts the total consumption current I T ( ⁇ A), the deviation (sec/day) and the oscillation period t osc (sec.) when the power supply voltage V DD - V SS is 1.55V and the external capacitors C 1 and C 2 are altered.

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  • General Physics & Mathematics (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
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US05/760,522 1976-01-19 1977-01-19 Crystal oscillator implemented with CMOS technology Expired - Lifetime US4091338A (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP522076A JPS5289047A (en) 1976-01-19 1976-01-19 Amplifier
JA51-5220 1976-01-19
JA51-30041 1976-03-18
JP3004176A JPS52113143A (en) 1976-03-18 1976-03-18 Amplifier
JA51-83238 1976-07-12
JP8323876A JPS538549A (en) 1976-07-12 1976-07-12 Amplifier

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US06/057,989 Expired - Lifetime US4322694A (en) 1976-01-19 1979-07-16 Crystal oscillator implemented with CMOS technology

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4527131A (en) * 1983-12-22 1985-07-02 Motorola, Inc. Oscillating circuit exhibiting tolerance to crystal impedance variations
US6582043B2 (en) * 2000-03-17 2003-06-24 Fuji Xerox Co., Ltd. Driving device and driving method for ink jet printing head
US20070008047A1 (en) * 2005-07-08 2007-01-11 Udo Karthaus Integrated quartz oscillator circuit
US20100182094A1 (en) * 2009-01-21 2010-07-22 Oki Semiconductor Co., Ltd. Constant current driven oscillating circuit
US20130063067A1 (en) * 2010-07-01 2013-03-14 Mitsubishi Electric Corporation Power semiconductor module, electric-power conversion apparatus, and railway vehicle
WO2019222770A1 (en) * 2018-05-17 2019-11-21 Microsoft Technology Licensing, Llc Circuit with shunt path

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3176296B2 (ja) * 1996-09-27 2001-06-11 山形日本電気株式会社 クロック信号発生回路
US6191661B1 (en) * 1997-10-30 2001-02-20 Nippon Precision Circuits, Inc. Oscillator circuit with reduced capacity for AC coupling capacitor
GB2351195A (en) * 1999-06-10 2000-12-20 Ericsson Telefon Ab L M An MOS voltage to current converter with current to voltage output stage and MOS feedback

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Publication number Priority date Publication date Assignee Title
US3040272A (en) * 1957-09-16 1962-06-19 North American Aviation Inc Frequency control circuit for a crystal oscillator
US2981899A (en) * 1958-08-12 1961-04-25 Hahnel Alwin Frequency divider
DE2146490B2 (de) * 1971-09-17 1972-12-07 Fa Diehl, 8500 Nürnberg Quarzoszillator, insbesondere fuer uhrenantriebe
US3979693A (en) * 1975-08-29 1976-09-07 Bell Telephone Laboratories, Incorporated Crystal-controlled oscillator having sinusoidal and square-wave output signals

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4527131A (en) * 1983-12-22 1985-07-02 Motorola, Inc. Oscillating circuit exhibiting tolerance to crystal impedance variations
US6582043B2 (en) * 2000-03-17 2003-06-24 Fuji Xerox Co., Ltd. Driving device and driving method for ink jet printing head
US20070008047A1 (en) * 2005-07-08 2007-01-11 Udo Karthaus Integrated quartz oscillator circuit
EP1742350A3 (de) * 2005-07-08 2007-03-14 ATMEL Germany GmbH Integrierte Quarzoszillatorschaltung
US7375600B2 (en) 2005-07-08 2008-05-20 Atmel Germany Gmbh Integrated quartz oscillator circuit
US20100182094A1 (en) * 2009-01-21 2010-07-22 Oki Semiconductor Co., Ltd. Constant current driven oscillating circuit
US8067993B2 (en) * 2009-01-21 2011-11-29 Oki Semiconductor Co., Ltd. Constant current driven oscillating circuit
US20130063067A1 (en) * 2010-07-01 2013-03-14 Mitsubishi Electric Corporation Power semiconductor module, electric-power conversion apparatus, and railway vehicle
US8791662B2 (en) * 2010-07-01 2014-07-29 Mitsubishi Electric Corporation Power semiconductor module, electric-power conversion apparatus, and railway vehicle
WO2019222770A1 (en) * 2018-05-17 2019-11-21 Microsoft Technology Licensing, Llc Circuit with shunt path
US10574181B2 (en) 2018-05-17 2020-02-25 Microsoft Technology Licensing, Llc Circuit with shunt path

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US4322694A (en) 1982-03-30
CH612570B (de)
CH612570GA3 (en) 1979-08-15

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