US3584741A - Batch sorting apparatus - Google Patents

Batch sorting apparatus Download PDF

Info

Publication number
US3584741A
US3584741A US837595A US3584741DA US3584741A US 3584741 A US3584741 A US 3584741A US 837595 A US837595 A US 837595A US 3584741D A US3584741D A US 3584741DA US 3584741 A US3584741 A US 3584741A
Authority
US
United States
Prior art keywords
objects
array
chips
chip
orientation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US837595A
Other languages
English (en)
Inventor
Edward F Schirmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of US3584741A publication Critical patent/US3584741A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67271—Sorting devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B07—SEPARATING SOLIDS FROM SOLIDS; SORTING
    • B07C—POSTAL SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTED PIECE-MEAL, e.g. BY PICKING
    • B07C5/00—Sorting according to a characteristic or feature of the articles or material being sorted, e.g. by control effected by devices which detect or measure such characteristic or feature; Sorting by manually actuated devices, e.g. switches
    • B07C5/34—Sorting according to other particular properties
    • B07C5/344—Sorting according to other particular properties according to electric or electromagnetic properties
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S209/00—Classifying, separating, and assorting solids
    • Y10S209/936—Plural items tested as group

Definitions

  • a system for this purpose includes a tester for measuring a characteristic of the objects in the array while maintaining them in a predetermined sequence and direction of orientation.
  • Means for storing a result based on the measurements for each object in the array is connected to the tester.
  • the sorting fixture for batch separation of objects with the desired characteristic on the basis of the stored results from the remainder of the objects is connected to the means for storing to allow selection of the objects on the basis of the stored results.
  • Means engageable by the sorting fixture receives the objects having the desired characteristic. The selection and release of the objects to the means engageable by the sorting fixture are both carried out while maintaining a predetermined. direction of orientation in the selected objects, enabling reorientation of the objects during their handling to be eliminated.
  • SHEET 3 OF 4 12 0 ojo o 0 o 0 40 O 0 Q 32/6 Q 0 4 3a 0 O b o o o o o o 40 w M H To 1 7 VACUUM VACUUM I 732 I 73 I n I WL ll 7 L i m J L 7 PEG. 6 1? 76 11 n PATENIED JUN! 5 l97l SHEET '4 OF 4 ELECTRICAL TESTER X-Y SERVOMECHANISM I I I COMPUTER SERVOMECHANISM BATCH SORTING APPARATUS FIELD OF THE INVENTION
  • This invention relates to apparatus for testing and batch sorting an array of objects while maintaining them in a predetermined direction of orientation.
  • it relates to such apparatus for testing and batch sorting nondefective semiconductor chips from defective chips and to a fixture for so sorting the chips on a batch basis while maintaining the nondefective chips in a predetermined direction of orientation, and preferably, a predetermined sequence of orientation as well.
  • Such semiconductor chips are fabricated in wafers containing up to 100 or more of the chips. After fabrication has been completed, the wafers are mounted on a dicing block with a suitable adhesive, such as glycol phthalate, then diced into individual chips. Testing of the chips may be carried out either while the chips retain their positions in a wafer, before or after dicing (called testing at the wafer level), or after the adhesive mounting the chips on the dicing block has been dissolved away to give individual chips (called testing at the chip level).
  • a suitable adhesive such as glycol phthalate
  • the chips are oriented and fed to testing stations by vibratory bowls.
  • Suitable apparatus or high volume testing at the chip level is disclosed in, for example, J. W. Broderick et al., U.S. Pat. 3,392,830, issued .luly I6, 1968.
  • the invention is based on a sorting fixture which has the capability of selecting objects in an array having a desired characteristic from those not having this characteristic on a batch basis, while maintaining a predetermined direction of orientation in the selected objects, and preferably, a predetermined sequence of orientation as well.
  • This sorting fixture may be combined with a tester for measuring a characteristic of the objects in the array. Means connected to the tester is provided in such a combination for storing a result based on the characteristic measured by the tester for each object in the array and its position in the array.
  • the sorter may then be used to select the objects having a desired characteristic while maintaining these objects in a predetermined direction of orientation.
  • means engageable by the sorting fixture for receiving the objects is also provided.
  • the sorting fixture of the invention includes a dicing block for separating a semiconductor wafer adhesively mounted on the block into an array containing a plurality of semiconductor chips adhesively mounted on the dicing block.
  • the sorting fixture has a matrix engageable with the dicing block, to be precisely positioned over a semiconductor wafer diced into an array of adhesively mounted chips on the dicing block.
  • the matrix has a location corresponding to each diced semiconductor chip.
  • Means is provided at each location in the matrix for maintaining each semiconductor chip at its corresponding location in the matrix and in a predetermined direction of orientation after separation from the dicing block.
  • Each location contains an individually actuable vacuum means for picking up the chip a each matrix location after separation from the dicing block, thus maintaining each selected chip in a predetermined direction and sequence of orientation with respect to other chips selected from the array.
  • the sorting fixture for the first time allows semiconductor chips to be tested at the wafer level, the results of the tests to be stored, nondefective chips to be automatically selected on the basis of the stored test results, and the selected chips to be delivered to a desired location, all while maintaining the chips in a predetermined sequence and direction of orientation, in the high volume production of semiconductor chips.
  • This capability though of special application to the manufacture of semiconductor chips, particularly integrated circuit chips that cannot be oriented and fed with vibratory bowls, makes the invention of value in testing and sorting a wide variety of electrical components or other objects in an array which must be shorted on the basis of their characteristics.
  • FIG. I is a perspective view of a fixture for sorting semiconductor chips in partially disassembled form and with partial cut aways to show detail;
  • FIG. 2 is a perspective view of the bottom of the lower portion of the fixture shown in FIG. I, also partially disassembled and with a partial cut away, showing detail not visible in FIG.
  • FIG. 3 is a section of the fixture shown in FIGS. 1 and 2, but assembled, taken along the lines 3-3 in FIGS. 1 and 2;
  • FIG. 4 is a top view of a location in a matrix in the fixture of FIG. 1 with a semiconductor chip in place.
  • FIG. 5 is an enlarged view of area 5 shown in FIG. 3 with semiconductor chips in place, and representing a partial section of three matrix locations of the type shown in FIG. 4;
  • FIG. 6 is a front view of another embodiment of a location in a matrix ofa fixture for sorting semiconductor chips with a semiconductor chip in place;
  • FIG. 7 is a partial cross section as in FIG. 5, but of three of the matrix locations of the type shown in FIG. 6;
  • FIG. 8 is a perspective view of a rack adapted to receive semiconductor chips from a sorting fixture of the invention.
  • FIG. 9 is a diagram of a system in accordance with the invention for testing and an nondefective semiconductor chips on a batch basis.
  • the fixture 19 comprises a base 20 holding a semiconductor dicing block 22 containing a diced semiconductor wafer 24 mounted thereon by a glycol phthalate adhesive 25 in precisely aligned relationship with respect to precision surfaces 26.
  • a top 28 of the fixture contains a matrix 30 of locations 32.
  • Top 28 has legs 34 extending from the top at either side of matrix 30 and adapted to mate with surfaces 26 on bottom 20 in a precision fitting relationship.
  • the precision mating of legs 34 and surfaces 26 enables the matrix 30 to be precisely positioned over semiconductor wafer 24, since wafer 24 has been previously aligned with respect to surfaces 26.
  • one location 32 in matrix 30 is positioned over each semiconductor chip 3 in diced wafer 24.
  • the spacing between each chip 38 and the size of chips 38 has been exaggerated for clarity.
  • An actual semiconductor wafer 24 of the type shown would be diced into up to I00 or more chips 38.
  • Each location 32 of matrix 30 has an individually actuable vacuum pickup 40 for picking up the chip 38 at each location 32.
  • semiconductor wafer 24 carried on dicing block 22 is mounted over aperture 41 in base 20 of the fixture.
  • the diced semiconductor chips 38 in wafer 24 are precisely aligned with respect to precision surfaces 26 on base 20.
  • Vacuum is then applied to aperture 41 now closed at the top by dicing block 22, from vacuum line 42 to hold dicing block 22 in place temporarily.
  • Clamps 44 are then adjusted by use of thumbscrews 46 to clamp dicing block 22 to base 20 with chips 38 in the desired position. Use of the vacuum to hold the dicing block 22 in place temporarily while clamps 44 are adjusted prevents the clamps 44 from moving dicing block 22 during their adjustment.
  • FIG. 2 shows an alignment means 48 on the underside of base 20 used for this purpose.
  • Alignment means 48 has an upper part 50 and a lower part 52.
  • the upper part 50 has a precision groove 53 and a precision surface 54.
  • Lower part 52 has a precision rod 56 which fits into precision groove 53, and a precision pin 49 which fits against precision surface 54 when the upper and lower parts of the alignment means 48 are together.
  • Screw 58 is used to fasten upper part 50 and lower part 52 together with the four precision members in engagement.
  • Lower part 52 of means 48 is mounted on a tester or other apparatus in which it is desired to align semiconductor chips 38 for automatic stepping inspection or other desired purpose.
  • upper portion 28 of the fixture is lowered into place with each location 32 of matrix 30 overlying one semiconductor chip 38. Screws 60 may then be tightened to fasten upper and lower portions 28 and 20 of the fixture 19 together in the desired relationship.
  • top 28 of fixture 19 is formed from two sections 61 and 62, which clamp together by means of pins 6 and sockets 64.
  • Vacuum lines 65 may be permanently connected to tubes 66 in section 62 of top 28.
  • Tubes 66 in section 62 terminate in polytetrafluoroethylene disc 67, holes 63 of which mate with vacuum pickups 40 in locations 32 of matrix 30 in section 61 of top 28.
  • Registration pins 69 serve to align holes 68 in disc 67 with each vacuum pickup 40.
  • Handles 70 on section 62 facilitate assembly with section 61.
  • the configuration of the locations 32 in matrix 30, shown in detail in FIGS. 4 and 5, allows the solvent to flow around each chip 38
  • the configuration there shown is for a chip 338 having a plurality of raised contact pads 71 around the chip periphery.
  • the vacuum pickup means 40 for each location 32 has an end 72 extending below the matrix surface 73 and of the proper size to fit within pads 71 on chip 38.
  • the end 72 of vacuum pickup 40 extend beyond the top of pads 60 toward chip surface 74. When this is done, the chip will not be free to wash away when the solvent dissolves the adhesive joining the chip to dicing block 22.
  • the end 72 of vacuum pickup 40 may touch surface 74 of chip 3% as shown in FIG. 5, while the adhesive 25 joining chip 38 to dicing block 22 is dissolved, but this is not necessary.
  • FIGS. 6 and 7 show an alternative embodiment of a matrix location 75 especially adapted for a chip 76 not having a plurality of raised solder pads around the periphery of the chip.
  • the location 75 has a plurality of projections, such as pins 77 which surround chip 76 to prevent movement of chip 76 from location 75 after the adhesive joining chip 76 to dicing block 22 has been dissolved.
  • the fixture is removed from the solvent and section 61 of top 28 rejoined to section 62.
  • Nondefective chips may then be selectively picked up by application of a vacuum to lines 65 connected to their corresponding locations 32 in matrix 30.
  • Defective chips and partial chips 78 around the edge of wafer 24 remain on dicing block 22 and may be washed away.
  • Semiconductor chips 38 which have been picked up by selective actuation of vacuum pickups 40 at their corresponding locations 32 in matrix 30 may be released to a suitable receiver, such as shown in FIG. 8, while maintaining a predetermined sequence and direction of orientation in the chips.
  • chip receiver 79 has a plurality of rows 80, each approximately the width of a semiconductor chip 38.
  • Suitable registration surfaces 82 are provided to engage legs 34 of top 28 of the chip-sorting fixture in the same manner as surfaces 26 on the bottom of the chip-sorting fixture, thus precisely positioning the matrix 30 with a row in the matrix corresponding to each channel 80.
  • the vacuum holding each chip 38 to vacuum pickup 40 at locations 32 may be released, thus allowing the chips 38 previously selected to drop into channels 80. .lf some of the chips 38 meet stringent test specifications while other chips 38 only meet less stringent test specifications, the chips meeting the most stringent specifications can be released into one chip receiver 79 and the chips 38 meeting the less stringent test specifications released to another chip receiver 79.
  • Chip receiver 79 may be conveniently used to invert the chips by providing a suitable cover 84 which fits over channels 80. Chip receiver 79 may simply be inverted with the cover 84 in place to invert the chips 38.
  • Chips 38 may be'moved to the ends 84 of chip receiver 79 or removed from the receiver 79 and conveyed to a chip positioning machine or other further manufacturing apparatus by application of a vacuum tochannels 80.
  • a vacuum tochannels 80 When removing the chips 38 from chip receiver 79 it is not necessary to retain the same sequence and direction of orientation of the chips. It is preferred, however, to maintain them in some known sequence and direction of orientation for continued identification of them and to eliminate the necessity to reorient them before positioning on a module or carrying out other manufacturing operations on them.
  • FIG. 9 shows a simplified schematic diagram of a semicon ductor chip-testing and sorting system incorporating a fixture of the type described above.
  • the base of the chip-sorting fixture 19 is engaged by a suitable X-Y servomechanism 86 for successively positioning semiconductor chips 38 in diced wafer 24 beneath probes 88.
  • a suitable test pulses are applied to chip 38 from tester 90 through cable 92, and the response of chip 38 thereto is sensed.
  • the tester 90 classifies the chip 38 as either nondefective or defective. This information, together with the location of the chip 38 in the array is supplied to computer 94 through cable 95.
  • top 28 of the chip-sorting fixture is fit into place with bottom 20, precisely positioning matrix 30 over semiconductor wafer 24, with each array location 32 corresponding to a semiconductor chip 38.
  • the adhesive joining chips 38 to dicing block 22 is then dissolved.
  • computer 94 connected to vacuum system 96 by cable 98 selectively actuates vacuum lines 65 to pick up nondefective semiconductor chips 38. Releasing the vacuum in lines 65 so actuated will then release nondefective semiconductor chips 38 selected to a chip receiver 79 positioned beneath top 28 of the fixture.
  • the computer 94 may be used for selective release of only the semiconductor chips 38 meeting the most stringent test specifications to one chip receiver 79 and release of the remaining semiconductor chips 38 selected to another chip receiver 79.
  • an additional tester such as visual tester 100 may be connected to computer 94 by cable 102.
  • the base 20 containing the chips 38 may be loaded into visual tester 100.
  • Computer 94 may then instruct X-Y servomechanism 104 associated with visual tester 100 to step sequentially only to the chips 38 which have tested as electrically nondefective.
  • a revision of the test results stored in computer 94 for the chips 38 in wafer 24 may be made from optical tester 100 through cable 102.
  • the system based on fixture 19 shown in FIG. 9 may be expanded by storing in the computer an identification of the chip receiver 79 in which nondefective chips 38 from a particular sort operation have been released. Since identification of the chips can be maintained, a chip placement machine could also be connected to computer 94 to record the use of particular chips 38 at a particular time. If a similar identification of module substrates onto which the chips 38 are mounted were maintained, ultimate identification of particular chips in modules as coming from particular semiconductor manufacturing lots could be maintained. This would, for the first time, allow actual semiconductor chip reliability data from the field to be obtained and correlated with process conditions for particular manufacturing lots. This has hitherto not been possible due to inability to maintain identification of particular semiconductor chips after wafer dicing has taken place.
  • the sorting fixture selects nondefective objects, such as semiconductor chips, from defective objects of the same type on a batch basis without requiring individual, serial handling of the selected objects.
  • the system allows an array of semiconductor chips or other objects to be tested, the results of the tests to be stored, and the nondefective objects to be selected from the array on a batch basis, all while maintaining a predetermined sequence and! direction or orientation ofthe selected objects.
  • An apparatus for selecting objects from an array having a desired characteristic from those having an undesired characteristic comprising:
  • D. means operatively connecting each of said individually actuable means for picking up the objects and said means for storing the determination of the characteristic of the objects for selective actuation of said means for picking up the objects.
  • An apparatus for sorting semiconductor chips comprismg:
  • C. means for maintaining each chip at its corresponding lo cation in the matrix and in a predetermined direction of orientation after separation from said dicing block
  • an individually actuable vacuum means for picking up the chip at each matrix location after separation from said dicing block while maintaining each chip in a predetermined direction of orientation with respect to other chips selected from the array.
  • the means for maintaining each chip at its location in the matrix and in a predetermined direction of orientation is a plurality of members extending between each chip at its location in the matrix and projecting beyond the vacuum means.
  • the apparatus for sorting semiconductor chips of claim B. a tester for measuring a characteristic of the chips in the array
  • D. means for storing the measurement of the characteristic for each chip in the array and its location in the array
  • E. means operatively connecting each of said vacuum means and said means for storing for selective actuation of said vacuum means in accordance with the stored measurements.
  • a system for testing and sorting an array of objects in a predetermined direction of orientation, based on their individual characteristics comprising:
  • B. means for storing a result based on the characteristic measured by the tester for each object in the array and its position in the array
  • D. means engageable by the sorter for receiving the objects in the array having a desired characteristic from the sorter while maintaining the objects having a desired characteristic in a predetermined direction of orientation.
  • the sorting means comprises a plurality of selectively actuable vacuum means for picking up objects in the array having a desired characteristic.
  • a process for selecting objects from an array having a desired characteristic from those having an undesired charac teristic comprising:

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
US837595A 1969-06-30 1969-06-30 Batch sorting apparatus Expired - Lifetime US3584741A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83759569A 1969-06-30 1969-06-30

Publications (1)

Publication Number Publication Date
US3584741A true US3584741A (en) 1971-06-15

Family

ID=25274909

Family Applications (1)

Application Number Title Priority Date Filing Date
US837595A Expired - Lifetime US3584741A (en) 1969-06-30 1969-06-30 Batch sorting apparatus

Country Status (5)

Country Link
US (1) US3584741A (enrdf_load_stackoverflow)
JP (1) JPS4827501B1 (enrdf_load_stackoverflow)
DE (1) DE2028910C3 (enrdf_load_stackoverflow)
FR (1) FR2052380A5 (enrdf_load_stackoverflow)
GB (1) GB1305593A (enrdf_load_stackoverflow)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845179A (enrdf_load_stackoverflow) * 1971-06-25 1973-06-28
US3762426A (en) * 1972-04-26 1973-10-02 Ibm Semiconductor chip separation apparatus
DE2315402A1 (de) * 1972-03-31 1973-10-04 Ibm Verfahren zum automatischen zerschneiden von halbleiterplaettchen in chips und zum orientierten aufloeten von chips auf modulsubstrate
US3847284A (en) * 1973-05-11 1974-11-12 Teledyne Inc Magnetic tape die sorting system
US3894633A (en) * 1974-10-24 1975-07-15 Western Electric Co Method and apparatus for sorting articles
US3915850A (en) * 1973-11-14 1975-10-28 Gti Corp Component handler and method and apparatus utilizing same
US3915784A (en) * 1972-04-26 1975-10-28 Ibm Method of semiconductor chip separation
DE2558963A1 (de) * 1974-12-28 1976-07-08 Sony Corp Vorrichtung zur anbringung von halbleiterplaettchen
EP0468153A1 (de) * 1990-07-25 1992-01-29 atg test systems GmbH Kontaktierungsvorrichtung für Prüfzwecke
WO1997015174A1 (en) * 1995-10-20 1997-04-24 Teradyne, Inc. Integrated prober, handler and tester for semiconductor components
US6078188A (en) * 1995-09-04 2000-06-20 Advantest Corporation Semiconductor device transporting and handling apparatus
US6222145B1 (en) 1998-10-29 2001-04-24 International Business Machines Corporation Mechanical strength die sorting
US6246251B1 (en) * 1998-04-24 2001-06-12 International Rectifier Corp. Test process and apparatus for testing singulated semiconductor die
US6505665B1 (en) * 1998-09-17 2003-01-14 Intermedics, Inc. Method and apparatus for use in assembling electronic devices
US6521853B1 (en) * 2000-05-08 2003-02-18 Micro Component Technology, Inc. Method and apparatus for sorting semiconductor devices
US6570374B1 (en) * 2000-06-23 2003-05-27 Honeywell International Inc. Vacuum chuck with integrated electrical testing points
US20100209219A1 (en) * 2009-02-17 2010-08-19 Sze Chak Tong Electronic device sorter comprising dual buffers
US20150183133A1 (en) * 2013-12-26 2015-07-02 Huping Jia Gripping mechanism, cutting device and cutting method for liquid crystal panel
US10173246B1 (en) * 2018-05-30 2019-01-08 Nanotronics Imaging, Inc. Systems, apparatus, and methods for sorting components using illumination
CN113426682A (zh) * 2021-06-04 2021-09-24 盐城东紫光电科技有限公司 一种MiniLED的检测分选工艺

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4406373A (en) * 1981-08-03 1983-09-27 Palomar Systems & Machines, Inc. Means and method for testing and sorting miniature electronic units
JPS59110758U (ja) * 1983-01-18 1984-07-26 大谷　均 ダブルタイヤの石取器
CN109454023A (zh) * 2018-12-21 2019-03-12 义乌臻格科技有限公司 一种用于拾取微型芯片的吸嘴装置及分选装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3503500A (en) * 1965-09-18 1970-03-31 Telefunken Patent Sorting apparatus and method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3503500A (en) * 1965-09-18 1970-03-31 Telefunken Patent Sorting apparatus and method

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845179A (enrdf_load_stackoverflow) * 1971-06-25 1973-06-28
DE2315402A1 (de) * 1972-03-31 1973-10-04 Ibm Verfahren zum automatischen zerschneiden von halbleiterplaettchen in chips und zum orientierten aufloeten von chips auf modulsubstrate
US3762426A (en) * 1972-04-26 1973-10-02 Ibm Semiconductor chip separation apparatus
US3915784A (en) * 1972-04-26 1975-10-28 Ibm Method of semiconductor chip separation
US3847284A (en) * 1973-05-11 1974-11-12 Teledyne Inc Magnetic tape die sorting system
US3915850A (en) * 1973-11-14 1975-10-28 Gti Corp Component handler and method and apparatus utilizing same
US3894633A (en) * 1974-10-24 1975-07-15 Western Electric Co Method and apparatus for sorting articles
DE2558963A1 (de) * 1974-12-28 1976-07-08 Sony Corp Vorrichtung zur anbringung von halbleiterplaettchen
EP0468153A1 (de) * 1990-07-25 1992-01-29 atg test systems GmbH Kontaktierungsvorrichtung für Prüfzwecke
US6078188A (en) * 1995-09-04 2000-06-20 Advantest Corporation Semiconductor device transporting and handling apparatus
US6024526A (en) * 1995-10-20 2000-02-15 Aesop, Inc. Integrated prober, handler and tester for semiconductor components
WO1997015174A1 (en) * 1995-10-20 1997-04-24 Teradyne, Inc. Integrated prober, handler and tester for semiconductor components
US6246251B1 (en) * 1998-04-24 2001-06-12 International Rectifier Corp. Test process and apparatus for testing singulated semiconductor die
US6505665B1 (en) * 1998-09-17 2003-01-14 Intermedics, Inc. Method and apparatus for use in assembling electronic devices
US6222145B1 (en) 1998-10-29 2001-04-24 International Business Machines Corporation Mechanical strength die sorting
US6521853B1 (en) * 2000-05-08 2003-02-18 Micro Component Technology, Inc. Method and apparatus for sorting semiconductor devices
US6570374B1 (en) * 2000-06-23 2003-05-27 Honeywell International Inc. Vacuum chuck with integrated electrical testing points
US20100209219A1 (en) * 2009-02-17 2010-08-19 Sze Chak Tong Electronic device sorter comprising dual buffers
US7851721B2 (en) * 2009-02-17 2010-12-14 Asm Assembly Automation Ltd Electronic device sorter comprising dual buffers
US20150183133A1 (en) * 2013-12-26 2015-07-02 Huping Jia Gripping mechanism, cutting device and cutting method for liquid crystal panel
US10173246B1 (en) * 2018-05-30 2019-01-08 Nanotronics Imaging, Inc. Systems, apparatus, and methods for sorting components using illumination
CN113426682A (zh) * 2021-06-04 2021-09-24 盐城东紫光电科技有限公司 一种MiniLED的检测分选工艺

Also Published As

Publication number Publication date
DE2028910B2 (de) 1979-01-11
GB1305593A (enrdf_load_stackoverflow) 1973-02-07
DE2028910C3 (de) 1979-09-06
JPS4827501B1 (enrdf_load_stackoverflow) 1973-08-23
FR2052380A5 (enrdf_load_stackoverflow) 1971-04-09
DE2028910A1 (de) 1971-01-07

Similar Documents

Publication Publication Date Title
US3584741A (en) Batch sorting apparatus
US3811182A (en) Object handling fixture, system, and process
US4528500A (en) Apparatus and method for testing circuit boards
KR100385014B1 (ko) 번인용재사용가능한다이캐리어및번인방법
KR100187559B1 (ko) 전기적특성의 측정방법 및 그의 측정장치
US6806725B2 (en) Method and apparatus for processing an array of packaged semiconductor devices
US6900459B2 (en) Apparatus for automatically positioning electronic dice within component packages
JP3412114B2 (ja) Ｉｃ試験装置
US5444386A (en) Probing apparatus having an automatic probe card install mechanism and a semiconductor wafer testing system including the same
US5534786A (en) Burn-in and test method of semiconductor wafers and burn-in boards for use in semiconductor wafer burn-in tests
JP4222442B2 (ja) 電子部品試験装置用インサート
JP2940858B2 (ja) Ｉｃ試験装置
JPH0798361A (ja) 被検査体の収納具及びプローブ装置
US6160415A (en) Apparatus and method for setting zero point of Z-axis in a wafer probe station
US5455518A (en) Test apparatus for integrated circuit die
CN115308556A (zh) 晶圆测试用的定位标记结构、曝光区域及晶圆
KR0124552Y1 (ko) 웨이퍼링 검사장치
JPH0513524A (ja) 半導体素子の検査方法
JPH0329335A (ja) 半導体チッププローバ
JPH02213777A (ja) 半導体チッププローバ
JP3012242B2 (ja) 半導体集積回路の製造方法
JPS5984531A (ja) 電子部品取付装置
JPS63170933A (ja) ウエ−ハプロ−バ
JP3009315B2 (ja) ペレットボンディング装置
US6968614B2 (en) Method for positioning an electronic module having a contact column array into a template