US20180005346A1 - Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register - Google Patents

Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register Download PDF

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Publication number
US20180005346A1
US20180005346A1 US15/201,269 US201615201269A US2018005346A1 US 20180005346 A1 US20180005346 A1 US 20180005346A1 US 201615201269 A US201615201269 A US 201615201269A US 2018005346 A1 US2018005346 A1 US 2018005346A1
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array
data
storage medium
dimensional
readable storage
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Albert Meixner
Daniel Frederic Finchelstein
David Patterson
William R. Mark
Jason Rupert Redgrave
Ofer Shacham
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Google LLC
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Google LLC
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Priority to US15/598,082 priority patent/US9978116B2/en
Priority to KR1020197003054A priority patent/KR102232723B1/ko
Priority to JP2018568290A priority patent/JP6837084B2/ja
Priority to PCT/US2017/036565 priority patent/WO2018005037A1/en
Priority to EP17734557.6A priority patent/EP3479341B1/en
Priority to GB1916257.7A priority patent/GB2576278B/en
Priority to GB201709788A priority patent/GB2553632B/en
Priority to DE102017113867.6A priority patent/DE102017113867A1/de
Priority to DE202017103727.4U priority patent/DE202017103727U1/de
Priority to TW107141459A priority patent/TWI690896B/zh
Priority to TW106121883A priority patent/TWI646501B/zh
Priority to CN201710534983.0A priority patent/CN107563954B/zh
Assigned to GOOGLE LLC reassignment GOOGLE LLC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: GOOGLE INC.
Publication of US20180005346A1 publication Critical patent/US20180005346A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/94—Hardware or software architectures specially adapted for image or video understanding
    • G06V10/955—Hardware or software architectures specially adapted for image or video understanding using specific electronic processors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the field of invention pertains generally to image processing, and, more specifically, to core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register.
  • Image processing typically involves the processing of pixel values that are organized into an array.
  • a spatially organized two dimensional array captures the two dimensional nature of images (additional dimensions may include time (e.g., a sequence of two dimensional images) and data type (e.g., colors).
  • additional dimensions may include time (e.g., a sequence of two dimensional images) and data type (e.g., colors).
  • the arrayed pixel values are provided by a camera that has generated a still image or a sequence of frames to capture images of motion.
  • Traditional image processors typically fall on either side of two extremes.
  • a first extreme performs image processing tasks as software programs executing on a general purpose processor or general purpose-like processor (e.g., a general purpose processor with vector instruction enhancements). Although the first extreme typically provides a highly versatile application software development platform, its use of finer grained data structures combined with the associated overhead (e.g., instruction fetch and decode, handling of on-chip and off-chip data, speculative execution) ultimately results in larger amounts of energy being consumed per unit of data during execution of the program code.
  • a general purpose processor or general purpose-like processor e.g., a general purpose processor with vector instruction enhancements
  • a second, opposite extreme applies fixed function hardwired circuitry to much larger blocks of data.
  • the use of larger (as opposed to finer grained) blocks of data applied directly to custom designed circuits greatly reduces power consumption per unit of data.
  • the use of custom designed fixed function circuitry generally results in a limited set of tasks that the processor is able to perform. As such, the widely versatile programming environment (that is associated with the first extreme) is lacking in the second extreme.
  • a technology platform that provides for both highly versatile application software development opportunities combined with improved power efficiency per unit of data remains a desirable yet missing solution.
  • a method includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration.
  • the method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations.
  • Another method includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
  • An apparatus includes means for, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration.
  • the apparatus also includes means for executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations.
  • Another apparatus includes means for, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
  • FIG. 1 shows various components of a technology platform
  • FIG. 2 a shows an embodiment of application software built with kernels
  • FIG. 2 b shows an embodiment of the structure of a kernel
  • FIG. 3 shows an embodiment of the operation of a kernel
  • FIGS. 4 a , 4 b and 4 c depict various aspects of a virtual processor's memory model for developing kernel threads in a higher level application software development environment
  • FIG. 5 a shows an embodiment of a thread written with load instructions having a position relative format
  • FIG. 5 b shows images having different pixel densities
  • FIG. 6 shows an embodiment of an application software development and simulation environment
  • FIG. 7 shows an embodiment of an image processor hardware architecture
  • FIGS. 8 a , 8 b , 8 c , 8 d and 8 e depict the parsing of image data into a line group, the parsing of a line group into a sheet and the operation performed on a sheet with overlapping stencils;
  • FIG. 9 a shows an embodiment of a stencil processor
  • FIG. 9 b shows an embodiment of a instruction word of the stencil processor
  • FIG. 10 shows an embodiment of a data computation unit within a stencil processor
  • FIGS. 11 a , 11 b , 11 c , 11 d , 11 e , 111 , 11 g , 11 h , 11 i , 11 j and 11 k depict an example of the use of a two-dimensional shift array and an execution lane array to determine a pair of neighboring output pixel values with overlapping stencils;
  • FIG. 12 shows an embodiment of a unit cell for an integrated execution lane array and two-dimensional shift array
  • FIG. 13 shows a two-dimensional row/column sum operation
  • FIGS. 14 a , 14 b , 14 c and 14 d show low level operations for implementing a two dimensional row sum operation
  • FIG. 15 pertains to a two-dimensional prefix sum operation
  • FIGS. 16 a , 16 b , 16 c and 16 d show low level operations for implementing a two-dimensional prefix sum operation
  • FIG. 17 pertains to a two-dimensional find minimum operation
  • FIGS. 18 a , 18 b , 18 c and 18 d show low level operations for implementing a two-dimensional find minimum operation
  • FIGS. 19 a and 19 b show a matrix multiply operation
  • FIGS. 20 a , 20 b , 20 c , 20 d and 20 e show low level operations for implementing a matrix multiply operation with a two dimensional shift register
  • FIG. 21 shows a DFT operation
  • FIGS. 22 a , 22 b , 22 c , 22 d , 22 e and 22 f show low level operations for implementing a DFT operation with a two dimensional shift register
  • FIG. 23 shows butterfly operations
  • FIGS. 24 a , 24 b and 24 c show butterfly operations implemented with a two-dimensional shift register
  • FIG. 25 shows a base image and an alternative image having a block image
  • FIGS. 26 a , 26 b , 26 c and 26 d show low level operations for performing a block matching algorithm
  • FIG. 27 shows an environment for generating program code that is targeted to a hardware platform having a two-dimensional execution lane array and a two-dimensional shift register array;
  • FIG. 28 shows an embodiment of a computing system.
  • FIG. 1 shows a high level view of an image processor technology platform that includes a virtual image processing environment 101 , the actual image processing hardware 103 and a compiler 102 for translating higher level code written for the virtual processing environment 101 to object code that the actual hardware 103 physically executes.
  • the virtual processing environment 101 is widely versatile in terms of the applications that can be developed and is tailored for easy visualization of an application's constituent processes.
  • the compiler 102 translates the code that was written within the virtual processing environment 101 into object code that is targeted for the actual hardware 103 .
  • FIG. 2 a shows an example of the structure and form that application software written within the virtual environment may take.
  • the program code may be expected to process one or more frames of input image data 201 to effect some overall transformation on the input image data 201 .
  • the transformation is realized with the operation of one or more kernels of program code 202 that operate on the input image data in an orchestrated sequence articulated by the developer.
  • the overall transformation is effected by first processing each input image with a first kernel K 1 .
  • the output images produced by kernel K 1 are then operated on by kernel K 2 .
  • Each of the output images produced by kernel K 2 are then operated on by kernel K 3 _ 1 or K 3 _ 2 .
  • the output images produced by kernel(s) K 3 _ 1 /K 3 _ 2 are then operated on by kernel K 4 .
  • Kernels K 3 _ 1 and K 3 _ 2 may be identical kernels designed to speed-up the overall processing by imposing parallel processing at the K 3 stage, or, may be different kernels (e.g., kernel K 3 _ 1 operates on input images of a first specific type and kernel K 3 _ 2 operates on input images of a second, different type).
  • the larger overall image processing sequence may take the form of a image processing pipeline or a directed acyclic graph (DAG) and the development environment may be equipped to actually present the developer with a representation of the program code being developed as such.
  • Kernels may be developed by a developer individually and/or may be provided by an entity that supplies any underlying technology (such as the actual signal processor hardware and/or a design thereof) and/or by a third party (e.g., a vendor of kernel software written for the development environment).
  • a nominal development environment will include a “library” of kernels that developers are free to “hook-up” in various ways to effect the overall flow of their larger development effort.
  • Some basic kernels that are expected to be part of such a library may include kernels to provide any one or more of the following basic image processing tasks: convolutions, denoising, color space conversions, edge and corner detection, sharpening, white balance, gamma correction, tone mapping, matrix multiply, image registration, pyramid construction, wavelet transformation, block-wise discrete cosine, and Fourier transformations.
  • FIG. 2 b shows an exemplary depiction of the structure of a kernel 203 as may be envisioned by a developer.
  • the kernel 203 can be viewed as a number of parallel threads of program code (“threads”) 204 that are each operating on a respective underlying processor 205 where each processor 205 is directed to a particular location in an output array 206 (such as a specific pixel location in the output image that the kernel is generating).
  • threads program code
  • every depicted output array location would have its own dedicated processor and corresponding thread. That is, a separate processor and thread can be allocated for each pixel in the output array.
  • a same thread may generate data for more than output pixel and/or two different threads (e.g., in certain limited cases) may collaborate on the generation of the data for a same output pixel.
  • an array of execution lanes and corresponding threads operate in unison (e.g., in a Single Instruction Multiple Data (SIMD) like fashion) to generate output image data for a portion of a “line group” of the frame currently being processed.
  • a line group is a contiguous, sizable section of an image frame.
  • the developer may be conscious the hardware operates on line groups, or, the development environment may present an abstraction in which there is a separate processor and thread for, e.g., every pixel in the output frame (e.g., every pixel in an output frame generated by its own dedicated processor and thread).
  • the developer understands the kernel to include an individual thread for each output pixel (whether the output array is visualized as an entire output frame or a section thereof).
  • the processors 205 that are presented to the developer in the virtual environment have an instruction set architecture (ISA) that, not only supports standard (e.g., RISC) opcodes, but also includes specially formatted data access instructions that permit the developer to easily visualize the pixel by pixel processing that is being performed.
  • ISA instruction set architecture
  • RISC standard
  • the ability to easily define/visualize any input array location in combination with an entire ISA of traditional mathematical and program control opcodes allows for an extremely versatile programming environment that essentially permits an application program developer to define, ideally, any desired function to be performed on any sized image surface. For example, ideally, any mathematical operation can be readily programmed to be applied to any stencil size.
  • the ISA of the virtual processors (“virtual ISA”) include a special data load instruction and a special data store instruction.
  • the data load instruction is able to read from any location within an input array of image data.
  • the data store instruction is able to write to any location within the output array of image data.
  • the latter instruction allows for easily dedicating multiple instances of the same processor to different output pixel locations (each processor writes to a different pixel in the output array).
  • stencil size itself (e.g., expressed as a width of pixels and a height of pixels) can be made an easily programmable feature.
  • Visualization of the processing operations is further simplified with each of the special load and store instructions having a special instruction format whereby target array locations are specified simplistically as X and Y coordinates.
  • each processor can execute their respective threads in parallel so that, e.g., the respective values for all locations in the output array are produced concurrently.
  • image processing routines typically perform the same operations on different pixels of the same output image.
  • each processor is presumed to be identical and executes the same thread program code.
  • the virtualized environment can be viewed as a type of two-dimensional (2D), SIMD processor composed of a 2D array of, e.g., identical processors each executing identical code in lock-step.
  • FIG. 3 shows a more detailed example of the processing environment for two virtual processors that are processing identical code for two different pixel locations in an output array.
  • FIG. 3 shows an output array 304 that corresponds to an output image being generated.
  • a first virtual processor is processing the code of thread 301 to generate an output value at location X1 of the output array 304 and a second virtual processor is processing the code of thread 302 to generate an output value at location X2 of the output array 304 .
  • the developer would understand there is a separate processor and thread for each pixel location in the output array 304 (for simplicity FIG. 3 only shows two of them). However, the developer in various embodiments need only develop code for one processor and thread (because of the SIMD like nature of the machine).
  • an output pixel value is often determined by processing the pixels of an input array that include and surround the corresponding output pixel location.
  • position X1 of the output array 304 corresponds to position E of the input array 303 .
  • the stencil of input array 303 pixel values that would be processed to determine output value X1 would therefore corresponds to input values ABCDEFGHI.
  • the stencil of input array pixels that would be processed to determine output value X2 would corresponds to input values DEFGHIJKL.
  • FIG. 3 shows an example of corresponding virtual environment program code for a pair of threads 301 , 302 that could be used to calculate output values X1 and X2, respectively.
  • both pairs of code are identical and average a stencil of nine input array values to determine a corresponding output value.
  • the only difference between the two threads is the variables that are called up from the input array and the location of the output array that is written to. Specifically, the thread that writes to output location X1 operates on stencil ABCDEFGHI and the thread that writes to output location X2 operates on stencil DEFGHIJKL.
  • each virtual processor at least includes internal registers R 1 and R 2 and at least supports the following instructions: 1) a LOAD instruction from the input array into R 1 ; 2) a LOAD instruction from the input array into R 2 ; 3) an ADD instruction that adds the contents of R 1 and R 2 and places the resultant in R 2 ; 4) a DIV instruction that divides the value within R 2 by immediate operand 9 ; and, 5) a STORE instruction the stores the contents of R 2 into the output array location that the thread is dedicated to.
  • every location in the output array could be assigned a virtual processor and corresponding thread that performs these functions.
  • the multiple threads execute in isolation of one another. That is, there is no thread-to-thread communication between virtual processors (one SIMD channel is preventing from crossing into another SIMD channel).
  • a pertinent feature of the virtual processors is their memory model.
  • a processor reads data from memory, operates on that data and writes new data back into memory.
  • a memory model is the perspective or view that a processor has of the manner in which data is organized in memory.
  • FIGS. 4 a -4 c pertain to an embodiment of the memory model for the virtual processors of the development environment.
  • a simplistic environment involving only three virtual processors and corresponding threads 401 is used for purposes of example.
  • the memory model of the virtual processors takes care to preserve SIMD semantics while, at the same time, provide for scalar operations and private intermediate value storage space for each virtual processor.
  • the memory region 420 that each virtual processor operates out of is organized into six different partitions based on the type of information that is stored. Specifically, there exists: 1) a private scratchpad region 402 ; 2) a global input data array region 403 ; 3) a global output data array region 404 ; 4) a global look-up table information region 405 ; 5) a global atomic statistics region 406 ; and, 6) a global constant table information region 407 .
  • FIG. 4 a attempts to visualize those regions of memory that are shared or “global” amongst virtual processors in keeping with the SIMD-like nature of the overall processing environment. Likewise, FIG. 4 a also attempts to visualize other regions of memory that are not shared amongst virtual processors or are “private” to a particular virtual processor. Specifically, as observed in FIG. 4 a , all of the memory partitions are global with the exception of a scratchpad region 402 that is private to each virtual processor. A number of the different memory regions also have different memory addressing schemes as described further below.
  • the memory model therefore includes per processor private scratchpad regions 402 for the storage of such intermediate information by each virtual processor's corresponding thread.
  • the scratch pad region for a particular processor is accessed 409 by that processor through a typical (e.g., linear) random access memory address and is a read/write region of memory (i.e., a virtual processor is able to both read information from private memory as well as write information into private memory).
  • a typical (e.g., linear) random access memory address i.e., a virtual processor is able to both read information from private memory as well as write information into private memory.
  • the input array portion 403 contains the set of input data that is called into 408 the set of threads in order to produce output data.
  • the input array corresponds to an image (e.g., a frame) or section of an image that each thread is operating on or within.
  • the input image may be a true input such as the pixel information provided by a camera, or, some form of intermediate image such as the information provided by a previous kernel in a larger overall image processing sequence.
  • Virtual processors typically do not compete for same input data items because they operate on different pixel locations of the input image data during a same cycle.
  • a novel memory addressing scheme is used to define which particular input values are to be called in from the input array 403 .
  • a “position relative” addressing scheme is used that defines the desired input data with X, Y coordinates rather than a traditional linear memory address.
  • the load instruction of the virtual processors' ISA includes an instruction format that identifies a specific memory location within the input array with an X component and a Y component.
  • a two-dimensional coordinate system is used to address memory for input values read from the input array 403 .
  • the output array 404 contains the output image data that the threads are responsible for generating.
  • the output image data may be final image data such as the actual image data that is presented on a display that follows the overall image processing sequence, or, may be intermediate image data that a subsequent kernel of the overall image processing sequence uses as its input image data information.
  • virtual processors typically do not compete for same output data items because they write to different pixel locations of the output image data during a same cycle.
  • the position relative addressing scheme is also used for writes to the output array.
  • the ISA for each virtual processor includes a store instruction whose instruction format defines a targeted write location in memory as a two-dimensional X, Y coordinate rather than a traditional random access memory address. More details concerning embodiments of the position relative instructions of the virtual ISA are provided further below.
  • FIG. 4 a also shows each virtual processor performing a look-up 410 into a look-up table 411 that is kept within the look-up table memory region 405 .
  • Look-up tables are often used by image processing tasks to, e.g., obtain filter or transform coefficients for different array locations, implement complex functions (e.g., gamma curves, sine, cosine) where the look-up table provides the function output for an input index value, etc.
  • complex functions e.g., gamma curves, sine, cosine
  • FIG. 4 a likewise shows each of the three virtual processors effectively looking-up information from a same look-up table 411 kept in the look-up table memory region 405 .
  • the look-up table information region is accessed using a normal linear accessing scheme.
  • the look-up region of memory is read only (i.e., the processor can not change information in a look-up table and is only permitted to read information from it).
  • FIG. 4 a suggests only one look-up table is resident within the look-up table region 405 but the virtual environment permits for multiple, different look-up tables to be resident during the simulated runtime.
  • Embodiments of the virtual ISA instruction format for instructions that perform look-ups into the look-up table are provided further below.
  • FIG. 4 b shows each of the three virtual processors writing 413 to the atomic statistics region 406 . It is not uncommon for image processes to “update” or make a modest change to output information. The updated information may then be used for other downstream processes that make use of the updated information. Examples of such updates or modest changes include simple additions of a fixed offset to output data, simple multiplication of a multiplicand against output data, or minimum or maximum comparisons of output data against some threshold.
  • output data that has just been calculated by the individual threads 401 may be operated upon and the resultants written 413 to the atomic statistics region 406 .
  • the output data that is operated on by an atomic act may be kept internally by the processor or called up 412 from the output array, FIG. 4 b shows the later.
  • the atomic acts that may be performed on the output data include add, multiply, min, and max.
  • the atomic statistics region 406 is accessed using a position relative addressing scheme (as with input and output array accesses) given that updates to output data would logically be organized in a same two dimensional array as the output data itself.
  • Embodiments of the virtual ISA instruction format for performing an atomic act on output data and writing the resultant to the statistics region 406 are described in more detail further below.
  • FIG. 4 c shows each of the virtual processors reading 414 a constant value from a constant look-up table 415 within the constant memory region 407 .
  • a constant look-up table 415 within the constant memory region 407 .
  • accesses into the constant look-up table 415 return a same, scalar value to each of the virtual processors as depicted in FIG. 4 c .
  • look-up tables are typically accessed with an index value
  • the constant look-up table memory region is accessed with a linear random access memory address.
  • the constant region of memory is read only (i.e., the processor can not change information in a constant table and is only permitted to read information from it).
  • FIG. 4 c only shows a single constant look-up table 415 in the constant memory region 407 . As threads may make use of more than one such table memory region 407 is configured to be large enough to hold as many constant tables are needed/used.
  • the virtual processor ISA may include a number of pertinent features. Some of these described at length immediately below.
  • each virtual processor's ISA uses a relative positioning approach to define an X, Y coordinate for each of the following: 1) a LOAD instruction that reads input image data from the input array memory region; 2) a STORE instruction that writes output image data to the output array; and, 3) an atomic update to the statistics region of memory.
  • instructions for loads/stores from/to the input/output arrays have the following format
  • the instruction format takes on the following similar structure
  • the Z operand of the instruction defines which channel of a named line group or stats table is targeted by the instruction.
  • a single image will have multiple channels.
  • video images typically have a red channel (R), a green channel (G), and a blue channel (B) for a same frame of the video stream.
  • R red channel
  • G green channel
  • B blue channel
  • Each line group and statistics table is therefore structured to include the content of each channel for the particular image being processed.
  • the (X*XS+X0)/XD operand defines the X location within a named line group or stats table that is targeted by the instruction and the (Y*YS+Y0)/YD operand defines the Y location within a named line group or stats table that is targeted by the instruction.
  • the XS and XD terms for the X location and the YS and YD terms for the Y location are used for scaling between input and output images having different pixel densities. Scaling is described in more detail further below.
  • the X and Y components of the instruction format simply take the form of X+X0 and Y+Y0 where X0 and Y0 are positional offsets relative to the position of the thread.
  • a thread is viewed as being assigned to the position within the output array line group that its output value is written to. A corresponding, same position is readily identifiable in the input array line group and any stats table.
  • a simple blur kernel that averages together the pixel values for the X,Y location along with its left and right neighbors may therefore be written in pseudo-code as depicted in FIG. 5 a .
  • the location ((X);(Y)) corresponds to the position of the virtual processor that is writing to the output array.
  • LOAD corresponds to the opcode for a load from the input array
  • STORE corresponds to the opcode for the store to the output array. Note that there exists a LINEGROUP_1 in the input array and a LINEGROUP_1 in the output array.
  • FIG. 5 b depicts scaled images for purposes of explaining the scaling features of the relative positioning load and store instruction format.
  • Down sampling refers to the transformation of a higher resolution image to a lower resolution image by providing in the output image less than all of the pixels that exist in the input image.
  • Up sampling refers to the transformation of a lower resolution image to a higher resolution image by creating more pixels in the output image than exist in the input image.
  • the pertinent pixels in the input image that determine the output value for an output pixel progress “farther away” from the output pixel location moving along either axis in the output image.
  • the first pixel in the output image along either axis corresponds to the first, second, and third pixels along the same axis in the input image
  • the second pixel in the output image corresponds to the fourth, fifth, and sixth pixels in the input image, etc.
  • the first output pixel has a pertinent pixel in the third location while the second output pixel has a pertinent pixel in the sixth location.
  • the XS and YS multiplicand terms in the relative positioning instruction format are used to implement down sampling. If the blur pseudo code of FIG. 5 a where to be rewritten for 3:1 down sampling along both axis, the code would be rewritten as:
  • R 1 ⁇ LOAD LINEGROUP_1[((3X) ⁇ 1);3(Y);0]
  • R 1 ⁇ LOAD LINEGROUP_1[(X ⁇ 1)/3;(Y)/3;0]
  • R 2 ⁇ LOAD LINEGROUP_1[(X)/3;(Y)/3;0]
  • R 3 ⁇ LOAD LINEGROUP_1[(X+1)/3;(Y)/3;0]
  • the instruction format for instructions that access the private, constant, and look-up portions of memory include an operand that also take the form of a*b+c where a is a base position, b is a scaling term and c is an offset.
  • a linear addressing approach is taken where the a*b+c term essentially corresponds to a linear index that is applied to the targeted table.
  • Each of these instructions also include in the opcode and an identifier of the memory region being accessed. For example, an instruction that performs a look-up from the look-up table memory region may be expressed as
  • a similar format with similarly minded opcode may be utilized for instructions that target the constant and the private memory regions (e.g., LOAD CNST_(name)[(A*B+C)]; LOAD PRVT_(name)[(A*B+C)].
  • look-up table and the constant table accesses are read-only (a processor can not change the data that has been placed there). As such no STORE instructions exist for these memory regions.
  • the private region of memory is read/write. As such a store instruction exists for that memory region (e.g., STORE PRVT[(A*B+C)].
  • each virtual processor includes general purpose registers that can contain integer, floating point or fixed point values. Additionally, the general purpose registers may contain data values of configurable bit width such as 8, 16 or 32 bit values. Thus, the image data at each pixel location in an input array or output array can have a data size of 8, 16 or 32 bits.
  • a virtual processor can be configured for an execution mode that establishes the bit size and the numerical format of the values within the general purpose registers. Instructions may also specify immediate operands (which are input operands whose input values are expressed directly in the instruction itself rather being found in a specified register). Immediate operands can also have configurable 8, 16 or 32 bit widths.
  • each virtual processor is also capable of operating in a scalar mode or a SIMD mode internal to itself. That is, the data within a specific array location may be viewed as a scalar value or as a vector having multiple elements. For example a first configuration may establish scalar operation of 8 bits where each image array position holds a scalar 8 bit value. By contrast another configuration may establish parallel/SIMD operation of 32 bits where each image array location is assumed to hold four 8 bit values for a total data size of 32 bits per array location.
  • each virtual processor also includes registers to hold predicate values.
  • a single predicate value is often only one bit in length and expresses a resultant from an opcode that performs a true/false or greater than/less than test on existing data.
  • Predicate values are used, e.g., to determine branch directions through the code during execution (and therefore are used as operands in conditional branch instructions). Predicate values can also be expressed as an immediate operand in an instruction.
  • each virtual processor includes registers to hold scalar values.
  • scalar values are stored into and read from the partition space of the memory model that is reserved for constants (as discussed above with respect to FIG. 4 c ).
  • each virtual processor of a group of virtual processors that are processing a same image uses the same scalar value from the constant memory space.
  • scalar predicates also exist. These are values kept in register space that meet the definition of both a predicate and a scalar.
  • each virtual processor is designed as a RISC-like instruction set whose supported arithmetic instruction opcodes include any workable combination of the following: 1) ADD (addition of operands A and B); 2) SUB (subtraction of operands A and B); 3) MOV (move operand from one register to another register); 4) MUL (multiple operands A and B); 5) MAD (multiply operands A and B and add C to resultant); 6) ABS (return absolute value of operand A); 7) DIV (divide operand A by operand B); 8) SHL (shift operand A to the left); 9) SHR (shift operand A to the right); 10) MIN/MAX (return which of operands A and B is greater); 11) SEL (select specified bytes of operand A); 12) AND (return the logical AND of operands A and B); 13) OR (return the logical OR of operands A and B); 14) XOR (
  • the instruction set also includes standard predicate operations such as: 1) SEQ (returns a 1 if A equals B); 2) SNE (returns a 1 if A does not equal B); 3) SLT (returns a 1 if A is less than B); 4) SLE (returns a 1 if A is less than or equal to B).
  • Control flow instructions are also included such as JMP (jump) and BRANCH each of which may include nominal variables or predicates as operands.
  • FIG. 6 depicts an application software development and simulation environment 601 .
  • a developer may develop a comprehensive image processing function (e.g., an image processing pipeline where each stage in the pipeline performs a dedicated image processing task, some other DAG prescribed set of routines, etc.) by arranging kernels in a strategic sequence that is consistent with the overall intended image transformation. Kernels may be called up from a library 602 and/or the developer may develop one or more custom kernels.
  • a comprehensive image processing function e.g., an image processing pipeline where each stage in the pipeline performs a dedicated image processing task, some other DAG prescribed set of routines, etc.
  • Kernels within the library 602 may be provided by a third party vendor of kernels and/or a provider of any underlying technology (e.g., a vendor of a hardware platform that includes the targeted hardware image processor or a vendor of the targeted hardware image processor (e.g., provided as a design thereof or as actual hardware)).
  • a third party vendor of kernels and/or a provider of any underlying technology e.g., a vendor of a hardware platform that includes the targeted hardware image processor or a vendor of the targeted hardware image processor (e.g., provided as a design thereof or as actual hardware)).
  • the developer need only write the program code for a single thread 603 . That is, the developer need only write program code that determines a single output pixel value by referencing input pixel values relative to the output pixel location (e.g., with the aforementioned position relative memory access instruction format).
  • the development environment may then automatically instantiate multiple instances of the thread code on a respective virtual processor to effect a kernel on an array of processors that operate on an image surface area.
  • the image surface area may be a section of an image frame (such as a line group).
  • the custom thread program code is written in the object code of the virtual processor ISA (or a higher level language that is compiled down to the virtual processor ISA object code).
  • Simulation of execution of the custom kernel's program code may be performed in a simulated runtime environment that includes a virtual processor accessing a memory organized according to the memory model.
  • software models object oriented or otherwise of a virtual processor 604 and a memory 605 that incorporates the model are instantiated.
  • the virtual processor model 604 then simulates execution of the thread code 603 .
  • the entirety of the simulation environment 601 may be implemented as software that runs on a computer system (e.g., a workstation) 606 .
  • FIG. 7 shows an embodiment of an architecture 700 for an image processor implemented in hardware.
  • the image processor may be targeted, for example, by a compiler that converts program code written for a virtual processor within a simulated environment into program code that is actually executed by the hardware processor. As observed in FIG.
  • the architecture 700 includes a plurality of line buffer units 701 _ 1 through 701 _M (hereinafter “line buffers”, “line buffer units” or the like) interconnected to a plurality of stencil processor units 702 _ 1 through 702 _N (hereinafter, “stencil processors”, “stencil processor units” or the like) and corresponding sheet generator units 703 _ 1 through 703 _N (hereinafter “sheet generators”, “sheet generator units” or the like) through a network 704 (e.g., a network on chip (NOC) including an on chip switch network, an on chip ring network or other kind of network).
  • NOC network on chip
  • any line buffer unit may connect to any sheet generator and corresponding stencil processor through the network 704 .
  • program code is compiled and loaded onto a corresponding stencil processor 702 to perform the image processing operations earlier defined by a software developer (program code may also be loaded onto the stencil processor's associated sheet generator 703 , e.g., depending on design and implementation).
  • an image processing pipeline may be realized by loading a first kernel program for a first pipeline stage into a first stencil processor 702 _ 1 , loading a second kernel program for a second pipeline stage into a second stencil processor 702 _ 2 , etc. where the first kernel performs the functions of the first stage of the pipeline, the second kernel performs the functions of the second stage of the pipeline, etc. and additional control flow methods are installed to pass output image data from one stage of the pipeline to the next stage of the pipeline.
  • the image processor may be realized as a parallel machine having two or more stencil processors 702 _ 1 , 702 _ 2 operating the same kernel program code.
  • a highly dense and high data rate stream of image data may be processed by spreading frames across multiple stencil processors each of which perform the same function.
  • any DAG of kernels may be loaded onto the hardware processor by configuring respective stencil processors with their own respective kernel of program code and configuring appropriate control flow hooks into the hardware to direct output images from one kernel to the input of a next kernel in the DAG design.
  • frames of image data are received by a macro I/O unit 705 and passed to one or more of the line buffer units 701 on a frame-by-frame basis.
  • a particular line buffer unit parses its frame of image data into a smaller region of image data, referred to as a “line group”, and then passes the line group through the network 704 to a particular sheet generator.
  • a complete or “full” singular line group may be composed, for example, with the data of multiple contiguous complete rows or columns of a frame (for brevity the present specification will mainly refer to contiguous rows).
  • the sheet generator further parses the line group of image data into a smaller region of image data, referred to as a “sheet”, and presents the sheet to its corresponding stencil processor.
  • input frames are directed to the same line buffer unit 701 _ 1 which parses the image data into line groups and directs the line groups to the sheet generator 703 _ 1 whose corresponding stencil processor 702 _ 1 is executing the code of the first kernel in the pipeline/DAG.
  • the sheet generator 703 _ 1 Upon completion of operations by the stencil processor 702 _ 1 on the line groups it processes, the sheet generator 703 _ 1 sends output line groups to a “downstream” line buffer unit 701 _ 2 (in some use cases the output line group may be sent_back to the same line buffer unit 701 _ 1 that earlier had sent the input line groups).
  • One or more “consumer” kernels that represent the next stage/operation in the pipeline/DAG executing on their own respective other sheet generator and stencil processor e.g., sheet generator 703 _ 2 and stencil processor 702 _ 2
  • sheet generator 703 _ 2 and stencil processor 702 _ 2 receive from the downstream line buffer unit 701 _ 2 the image data generated by the first stencil processor 702 _ 1 .
  • a “producer” kernel operating on a first stencil processor has its output data forwarded to a “consumer” kernel operating on a second stencil processor where the consumer kernel performs the next set of tasks after the producer kernel consistent with the design of the overall pipeline or DAG.
  • a stencil processor 702 is designed to simultaneously operate on multiple overlapping stencils of image data.
  • the multiple overlapping stencils and internal hardware processing capacity of the stencil processor effectively determines the size of a sheet.
  • arrays of execution lanes operate in unison to simultaneously process the image data surface area covered by the multiple overlapping stencils.
  • sheets of image data are loaded into a two-dimensional register array structure within the stencil processor 702 .
  • the use of sheets and the two-dimensional register array structure is believed to effectively provide for power consumption improvements by moving a large amount of data into a large amount of register space as, e.g., a single load operation with processing tasks performed directly on the data immediately thereafter by an execution lane array.
  • the use of an execution lane array and corresponding register array provide for different stencil sizes that are easily programmable/configurable.
  • FIGS. 8 a through 8 e illustrate at a high level embodiments of both the parsing activity of a line buffer unit 701 , the finer grained parsing activity of a sheet generator unit 703 , as well as the stencil processing activity of the stencil processor 702 that is coupled to the sheet generator unit 703 .
  • FIG. 8 a depicts an embodiment of an input frame of image data 801 .
  • FIG. 8 a also depicts an outline of three overlapping stencils 802 (each stencil having a dimension of 3 pixels by 3 pixels) that a stencil processor is designed to operate over.
  • the output pixel that each stencil respectively generates output image data for is highlighted in solid black.
  • the three overlapping stencils 802 are depicted as overlapping only in the vertical direction. It is pertinent to recognize that in actuality a stencil processor may be designed to have overlapping stencils in both the vertical and horizontal directions.
  • a line buffer unit 701 is responsible for parsing a line group of input image data from an incoming frame that is sufficient for the stencil processors to operate over for an extended number of upcoming cycles.
  • the line buffer unit 701 can comprehend different dynamics for sending/receiving a line group to/from a sheet generator. For example, according to one mode, referred to as “full group”, the complete full width lines of image data are passed between a line buffer unit and a sheet generator. According to a second mode, referred to as “virtually tall”, a line group is passed initially with a subset of full width rows. The remaining rows are then passed sequentially in smaller (less than full width) pieces.
  • each stencil processor consists of a two dimensional shift register array.
  • the two dimensional shift register array essentially shifts image data “beneath” an array of execution lanes where the pattern of the shifting causes each execution lane to operate on data within its own respective stencil (that is, each execution lane processes on its own stencil of information to generate an output for that stencil).
  • sheets are surface areas of input image data that “fill” or are otherwise loaded into the two dimensional shift register array.
  • the sheet generator parses an initial sheet 804 from the line group 803 and provides it to the stencil processor (here, the exemplary sheet of data corresponds to the five by five shaded region that is generally identified by reference number 804 ).
  • the stencil processor operates on the sheet of input image data by effectively moving the overlapping stencils 802 in a left to right fashion over the sheet.
  • the number of pixels for which an output value could be calculated (nine in a darkened 3 by 3 array) from the data within the sheet is exhausted (no other pixel positions can have an output value determined from the information within the sheet). For simplicity the border regions of the image have been ignored.
  • the sheet generator then provides a next sheet 805 for the stencil processor to continue operations on.
  • the initial positions of the stencils as they begin operation on the next sheet is the next progression to the right from the point of exhaustion on the first sheet (as depicted previously in FIG. 8 d ).
  • the stencils will simply continue moving to the right as the stencil processor operates on the new sheet in the same manner as with the processing of the first sheet.
  • the sheet generator may proceed to only send new data to the stencil processor and the stencil processor reuses the overlapping data from the previous sheet.
  • FIG. 9 a shows an embodiment of a stencil processor unit architecture 900 .
  • the stencil processor includes a data computation unit 901 , a scalar processor 902 and associated memory 903 and an I/O unit 904 .
  • the data computation unit 901 includes an array of execution lanes 905 , a two-dimensional shift array structure 906 and separate respective random access memories 907 associated with specific rows or columns of the array.
  • the I/O unit 904 is responsible for loading “input” sheets of data received from the sheet generator into the data computation unit 901 and storing “output” sheets of data from the stencil processor into the sheet generator.
  • the loading of sheet data into the data computation unit 901 entails parsing a received sheet into rows/columns of image data and loading the rows/columns of image data into the two dimensional shift register structure 906 or respective random access memories 907 of the rows/columns of the execution lane array (described in more detail below).
  • the individual execution lanes within the execution lane array 905 may then load sheet data into the two-dimensional shift register structure 906 from the random access memories 907 when appropriate (e.g., as a load instruction just prior to operation on the sheet's data).
  • the execution lanes of the execution lane array 905 operate on the data and eventually “write back” finished data as a sheet directly back to the sheet generator, or, into the random access memories 907 . If the execution lanes write back to random access memories 907 , the I/O unit 904 fetches the data from the random access memories 907 to form an output sheet which is then forwarded to the sheet generator.
  • the scalar processor 902 includes a program controller 909 that reads the instructions of the stencil processor's program code from scalar memory 903 and issues the instructions to the execution lanes in the execution lane array 905 .
  • a single same instruction is broadcast to all execution lanes within the array 905 to effect single instruction multiple data (SIMD)-like behavior from the data computation unit 901 .
  • the instruction format of the instructions read from scalar memory 903 and issued to the execution lanes of the execution lane array 905 includes a very-long-instruction-word (VLIW) type format that includes more than one opcode per instruction.
  • VLIW very-long-instruction-word
  • the VLIW format includes both an ALU opcode that directs a mathematical function performed by each execution lane's ALU (which, as described below, in an embodiment may specify more than one traditional ALU operation) and a memory opcode (that directs a memory operation for a specific execution lane or set of execution lanes).
  • execution lane refers to a set of one or more execution units capable of executing an instruction (e.g., logic circuitry that can execute an instruction).
  • An execution lane can, in various embodiments, include more processor-like functionality beyond just execution units, however.
  • an execution lane may also include logic circuitry that decodes a received instruction, or, in the case of more multiple instruction multiple data (MIMD)-like designs, logic circuitry that fetches and decodes an instruction.
  • MIMD multiple instruction multiple data
  • MIMD-like approaches although a centralized program control approach has largely been described herein, a more distributed approach may be implemented in various alternative embodiments (e.g., including program code and a program controller within each execution lane of the array 905 ).
  • an execution lane array 905 provides a widely adaptable/configurable hardware platform for a broad range of programmable functions.
  • application software developers are able to program kernels having a wide range of different functional capability as well as dimension (e.g., stencil size) given that the individual execution lanes are able to perform a wide variety of functions and are able to readily access input image data proximate to any output array location.
  • the random access memories 907 may also keep one or more look-up tables such as any look-up tables held in the look-up table component of the virtual processing memory described above in Section 1.0.
  • one or more scalar look-up tables may also be instantiated within the scalar memory 903 .
  • the one or more scalar look-up tables may be any scalar look-up tables held in the scalar look-up table component of the memory model described above in Section 1.0.
  • a scalar look-up involves passing the same data value from the same look-up table from the same index to each of the execution lanes within the execution lane array 905 .
  • the VLIW instruction format described above is expanded to also include a scalar opcode that directs a look-up operation performed by the scalar processor into a scalar look-up table.
  • the index that is specified for use with the opcode may be an immediate operand or fetched from some other data storage location.
  • a look up from a scalar look-up table within scalar memory essentially involves broadcasting the same data value to all execution lanes within the execution lane array 905 during the same clock cycle. Additional details concerning the use and operation of look-up tables is provided further below.
  • FIG. 9 b summarizes the VLIW instruction word embodiments(s) discussed above.
  • the VLIW instruction word format includes fields for three separate instructions: 1) a scalar instruction 951 that is executed by the scalar processor; 2) an ALU instruction 952 that is broadcasted and executed in SIMD fashion by the respective ALUs within the execution lane array; and, 3) a memory instruction 953 that is broadcasted and executed in a partial SIMD fashion (e.g., if execution lanes along a same row in the execution lane array share a same random access memory, then one execution lane from each of the different rows actually execute the instruction (the format of the memory instruction 953 may include an operand that identifies which execution lane from each row executes the instruction)).
  • a field 954 for one or more immediate operands is also included. Which of the instructions 951 , 952 , 953 use which immediate operand information may be identified in the instruction format. Each of instructions 951 , 952 , 953 also includes its own respective input operand and resultant information (e.g., local registers for ALU operations and a local register and a memory address for memory access instructions).
  • the scalar instruction 951 is executed by the scalar processor before the execution lanes within the execution lane array execute either of the other two instructions 952 , 953 .
  • the execution of the VLIW word includes a first cycle upon which the scalar instruction 951 is executed followed by a second cycle upon with the other instructions 952 , 953 may be executed (note that in various embodiments instructions 952 and 953 may be executed in parallel).
  • the scalar instructions executed by the scalar processor 902 include commands issued to the sheet generator 703 to load/store sheets from/into the memories or 2D shift register 906 of the data computation unit 901 .
  • the sheet generator's operation can be dependent on the operation of the line buffer unit 701 or other variables that prevent pre-runtime comprehension of the number of cycles it will take the sheet generator 703 to complete any command issued by the scalar processor 902 .
  • any VLIW word whose scalar instruction 951 corresponds to or otherwise causes a command to be issued to the sheet generator 703 also includes no-operation (NOOP) instructions in the other two instruction fields 952 , 953 .
  • NOOP no-operation
  • the program code then enters a loop of NOOP instructions for instruction fields 952 , 953 until the sheet generator completes its load/store to/from the data computation unit.
  • the scalar processor may set a bit of an interlock register that the sheet generator resets upon completion of the command.
  • the scalar processor monitors the bit of the interlock bit. When the scalar processor detects that the sheet generator has completed its command normal execution begins again.
  • FIG. 10 shows an embodiment of a data computation unit 1001 .
  • the data computation unit 1001 includes an array of execution lanes 1005 that are logically positioned “above” a two-dimensional shift register array structure 1006 .
  • a sheet of image data provided by a sheet generator is loaded into the two-dimensional shift register 1006 .
  • the execution lanes then operate on the sheet data from the register structure 1006 .
  • the execution lane array 1005 and shift register structure 1006 are fixed in position relative to one another. However, the data within the shift register array 1006 shifts in a strategic and coordinated fashion to cause each execution lane in the execution lane array to process a different stencil within the data. As such, each execution lane determines the output image value for a different pixel in the output sheet being generated. From the architecture of FIG. 10 it should be clear that overlapping stencils are not only arranged vertically but also horizontally as the execution lane array 1005 includes vertically adjacent execution lanes as well as horizontally adjacent execution lanes.
  • Some notable architectural features of the data computation unit 1001 include the shift register structure 1006 having wider dimensions than the execution lane array 1005 . That is, there is a “halo” of registers 1009 outside the execution lane array 1005 . Although the halo 1009 is shown to exist on two sides of the execution lane array, depending on implementation, the halo may exist on less (one) or more (three or four) sides of the execution lane array 1005 .
  • the halo 1005 serves to provide “spill-over” space for data that spills outside the bounds of the execution lane array 1005 as the data is shifting “beneath” the execution lanes 1005 .
  • FIG. 10 shows the registers of the right side of the halo as only having horizontal shift connections and registers of the bottom side of the halo as only having vertical shift connections when, in a nominal embodiment, registers on either side (right, bottom) would have both horizontal and vertical connections.
  • random access memories 1007 that are coupled to each row and/or each column in the array, or portions thereof (e.g., a random access memory may be assigned to a “region” of the execution lane array that spans 4 execution lanes row wise and 2 execution lanes column wise. For simplicity the remainder of the application will refer mainly to row and/or column based allocation schemes).
  • an execution lane's kernel operations require it to process pixel values outside of the two-dimensional shift register array 1006 (which some image processing routines may require) the plane of image data is able to further spill-over, e.g., from the halo region 1009 into random access memory 1007 .
  • FIGS. 11 a through 11 k demonstrate a working example of the manner in which image data is shifted within the two-dimensional shift register array “beneath” the execution lane array as alluded to above.
  • the data contents of the two-dimensional shift array are depicted in a first array 1107 and the execution lane array is depicted by a frame 1105 .
  • two neighboring execution lanes 1110 within the execution lane array are simplistically depicted.
  • each execution lane includes a register R 1 that can accept data from the shift register, accept data from an ALU output (e.g., to behave as an accumulator across cycles), or write output data into an output destination.
  • ALU output e.g., to behave as an accumulator across cycles
  • Each execution lane also has available, in a local register R 2 , the contents “beneath” it in the two-dimensional shift array.
  • R 1 is a physical register of the execution lane
  • R 2 is a physical register of the two-dimensional shift register array.
  • the execution lane includes an ALU that can operate on operands provided by R 1 and/or R 2 .
  • the shift register is actually implemented with multiple (a “depth” of) storage/register elements per array location but the shifting activity is limited to one plane of storage elements (e.g., only one plane of storage elements can shift per cycle).
  • FIGS. 11 a through 11 k depict one of these deeper register locations as being used to store the resultant X from the respective execution lanes. For illustrative ease the deeper resultant register is drawn alongside rather than beneath its counterpart register R 2 .
  • FIGS. 11 a through 11 k focus on the calculation of two stencils whose central position is aligned with the pair of execution lane positions 1111 depicted within the execution lane array 1105 .
  • the pair of execution lanes 1110 are drawn as horizontal neighbors when in fact, according to the following example, they are vertical neighbors.
  • FIG. 11 b shows the object code executed by both execution lanes 1111 .
  • the program code of both execution lanes 1111 causes the data within the shift register array 1107 to shift down one position and shift right one position. This aligns both execution lanes 1111 to the upper left hand corner of their respective stencils.
  • the program code then causes the data that is located (in R 2 ) in their respective locations to be loaded into R 1 .
  • the program code next causes the pair of execution lanes 1111 to shift the data within the shift register array 1107 one unit to the left which causes the value to the right of each execution lane's respective position to be shifted into each execution lane′ position.
  • the value in R 1 (previous value) is then added with the new value that has shifted into the execution lane's position (in R 2 ).
  • the resultant is written into R 1 .
  • FIG. 11 d the same process as described above for FIG. 11 c is repeated which causes the resultant R 1 to now include the value A+B+C in the upper execution lane and F+G+H in the lower execution lane. At this point both execution lanes 1111 have processed the upper row of their respective stencils.
  • the program code next causes the data within the shift register array to shift one unit up which causes both execution lanes 1111 to be aligned with the right edge of the middle row of their respective stencils.
  • Register R 1 of both execution lanes 1111 currently includes the summation of the stencil's top row and the middle row's rightmost value.
  • FIGS. 11 f and 11 g demonstrate continued progress moving leftwise across the middle row of both execution lane's stencils. The accumulative addition continues such that at the end of processing of FIG. 11 g both execution lanes 1111 include the summation of the values of the top row and the middle row of their respective stencils.
  • FIG. 11 h shows another shift to align each execution lane with its corresponding stencil's lowest row.
  • FIGS. 11 i and 11 j show continued shifting to complete processing over the course of both execution lanes' stencils.
  • FIG. 11 k shows additional shifting to align each execution lane with its correct position in the data array and write the resultant thereto.
  • the object code for the shift operations may include an instruction format that identifies the direction and magnitude of the shift expressed in (X, Y) coordinates.
  • the object code for a shift up by one location may be expressed in object code as SHIFT 0, +1.
  • a shift to the right by one location may be expressed in object code as SHIFT+1, 0.
  • shifts of larger magnitude may also be specified in object code (e.g., SHIFT 0, +2).
  • the instruction may be interpreted by the machine to require multiple cycle execution, or, the 2D shift register hardware may be designed to support shifts by more than one location per cycle. Embodiments of the later are described in more detail further below.
  • FIG. 12 shows another, more detailed depiction of the unit cell for the array execution lane and shift register structure (registers in the halo region do not include a corresponding execution lane).
  • the execution lane and the register space that is associated with each location in the execution lane array is, in an embodiment, implemented by instantiating the circuitry observed in FIG. 12 at each node of the execution lane array.
  • the unit cell includes an execution lane 1201 coupled to a register file 1202 consisting of four registers R 2 through R 5 .
  • the execution lane 1201 may read from or write to any of registers R 1 through R 5 .
  • the execution lane may retrieve both of operands from any of R 1 through R 5 .
  • the two dimensional shift register structure is implemented by permitting, during a single cycle, the contents of any of (only) one of registers R 2 through R 4 to be shifted “out” to one of its neighbor's register files through output multiplexer 1203 , and, having the contents of any of (only) one of registers R 2 through R 4 replaced with content that is shifted “in” from a corresponding one if its neighbors through input multiplexers 1204 such that shifts between neighbors are in a same direction (e.g., all execution lanes shift left, all execution lanes shift right, etc.).
  • the multiplexer arrangement 1203 , 1204 permits for different shift source and shift target registers within a same register file during a same cycle.
  • an execution lane will shift content out from its register file 1202 to each of its left, right, top, and bottom neighbors.
  • the execution lane will also shift content into its register file from a particular one of its left, right, top, and bottom neighbors.
  • the shift out target and shift in source should be consistent with a same shift direction for all execution lanes (e.g., if the shift out is to the right neighbor, the shift in should be from the left neighbor).
  • the content of only one register is permitted to be shifted per execution lane per cycle
  • other embodiments may permit the content of more than one register to be shifted in/out.
  • the content of two registers may be shifted out/in during a same cycle if a second instance of the multiplexer circuitry 1203 , 1204 observed in FIG. 12 is incorporated into the design of FIG. 12 .
  • shifts from multiple registers may take place between mathematical operations by consuming more clock cycles for shifts between mathematical operations (e.g., the contents of two registers may be shifted between math ops by consuming two shift ops between the math ops).
  • the memory unit (“M”) observed in each execution lane is used to load/store data from/to the random access memory space that is associated with the execution lane's row and/or column within the execution lane array.
  • the M unit acts as a standard M unit in that it is often used to load/store data that cannot be loaded/stored from/to the execution lane's own register space.
  • the primary operation of the M unit is to write data from a local register into memory, and, read data from memory and write it into a local register.
  • the mathematical opcodes supported by the hardware ALU are integrally tied with (e.g., substantially the same as) the mathematical opcodes supported by a virtual execution lane (e.g., ADD, SUB, MOV, MUL, MAD, ABS, DIV, SHL, SHR, MIN/MAX, SEL, AND, OR, XOR, NOT).
  • a virtual execution lane e.g., ADD, SUB, MOV, MUL, MAD, ABS, DIV, SHL, SHR, MIN/MAX, SEL, AND, OR, XOR, NOT.
  • memory access instructions can be executed by the execution lane 1201 to fetch/store data from/to their associated random access memory.
  • the hardware execution lane 1201 supports shift operation instructions (right, left, up, down) to shift data within the two-dimensional shift register structure.
  • program control instructions are largely executed by the scalar processor of the stencil processor.
  • FIGS. 13 and 14 a,b pertain to a row/column sum operation.
  • Row/sum column operations are particularly useful for statistics computation, noise suppression, and large scale down-sampling.
  • Row sum and/or column sum operations can be implemented on an image processor having a two-dimensional execution lane array and corresponding two-dimensional shift register array such as embodiments of the image processor described above in the preceding sections.
  • a row sum operation adds all values in a same row of an array and a column sum operation adds all values in a same column of an array. Additionally, as depicted, with a row sum operation the values of all rows can be simultaneously added within their respective rows. Likewise, with a column sum operation the values of all columns can be simultaneously added within their respective columns. Because of the versatility of the shift register array, however, summing across all rows or columns is not a requirement. That is, less than all rows in an array may be simultaneously summed over or less that all columns in an array may be simultaneously summed over.
  • FIGS. 14 a through 14 d show an embodiment of a machine level operation for implementing a row sum operation. For simplicity only a single row is shown. The reader will understand that the operations depicted in FIGS. 14 a through 14 d can also be applied to a column. Additionally, for both row or column operations, the sequence of FIGS. 14 a through 14 d can also be simultaneously performed for multiple rows or columns in the array. Additionally, the dimension of the row is only shown to be 8 locations wide (whereas in actual implementations the execution lane array and shift register array may be 16 ⁇ 16 or even larger).
  • the two-dimensional shift register array is designed to support direct logical shifts between opposite ends of the array 1401 . That is, the shift register can “roll” or “loop” or “wrap” its content between a rightmost array column and a leftmost array column when performing shifts along a row axis, and/or, roll or loop its content between a topmost array row and a bottom most array row when performing shifts along a column axis.
  • the shift register can support multiple register location hops in a single instruction (e.g., an opcode and/or variable associated with a shift instruction specifies whether the shift amount is +/ ⁇ 1, +/ ⁇ 2, +/ ⁇ 3 or +/ ⁇ 4 register location places along horizontal and/or vertical axis). Shift distances that are not supported in the hardware can be emulated by the compiler.
  • the row is loaded with data values A 0 through A 7 in the respective R 0 and R 1 register locations of each execution lane.
  • the R 1 register space locations are then shifted left one location and the R 1 and R 0 contents of each execution lane are summed with the resultant written back to R 0 and R 1 .
  • This produces a first accumulated partial sum in R 1 which, as will be made more clear in the following discussion, acts as an accumulator for the overall summation operation.
  • FIGS. 15 and 16 a through 16 d pertain to a row/column prefix sum operation that can also be executed on an image processor having a two-dimensional execution lane array and a corresponding two-dimensional shift register.
  • Row/column prefix sum operations are particularly useful for integral images, accelerating box filters, and the computation of addresses for compaction operations.
  • FIG. 15 for simplicity, only a single row is shown. However, the operation can also be performed for columns.
  • any number of rows (or columns) in the register array can be simultaneously summed over.
  • the dimension of the row in FIG. 15 is only shown to be 8 locations wide, whereas, in actual implementations the execution lane and shift register arrays may be 16 ⁇ 16 or even larger.
  • the resultant of a row prefix operation for any location within a row is the sum of the values that lead up to that location.
  • the value of a column prefix operation for any location within a column is the sum of the values that lead up to that location.
  • FIGS. 16 a through 16 d shows an embodiment of a machine level operation for a row prefix operation.
  • the row prefix operation employs the use of a two dimensional shift register than can roll shifts between array edge locations 1601 .
  • a row is initially loaded with data values A 0 through A 7 in the respective R 0 register location of each execution lane. Also, a null (“0”) is loaded into the R 2 register space of each execution lane.
  • the R 0 register space locations are shifted right one location into the destination location's R 1 register space.
  • a subsequent ADD operation adds the R 0 content with either the R 1 content or the R 2 content depending on the location of the lane relative to the iteration count.
  • the first row location therefore will maintain a value of A 0 in R 0 .
  • each of the other row locations because their location is greater than 2 N ⁇ 1, will select the shifted content in R 1 (rather than the null value in R 2 ), add it to the content in R 0 and store the resultant in R 0 .
  • each of the row locations other than the first row location will keep the sum of its original content and its leftmost neighbor in R 0 whereas the first row location will simply keep only its original content in R 0 .
  • a second iteration of machine level operations depicted in FIG. 16 c , the content of the R 0 register space locations are shifted right two locations into the destination's R 1 register space.
  • the shift amount doubles.
  • a subsequent ADD operation adds the R 0 content with either the R 1 content or the R 2 content depending on the location of the lane relative to the current iteration count.
  • each of the other row locations because their location is greater than the 2 N ⁇ 1, will select the shifted content in R 1 (rather than the null value in R 2 ), add the content of R 1 to the content in R 0 and store the resultant in R 0 .
  • each of the row locations other than the first and second row locations will keep in R 0 an accumulated sum based on its original content and its total shifted in content.
  • the R 0 register space locations are shifted right four locations into the destination's R 1 register space.
  • the shift amount doubles.
  • a subsequent ADD operation adds the R 0 content with either the R 1 content or the R 2 content depending on the location of the lane relative to the current iteration count.
  • Each of these lanes will therefore add the null value to the content in R 0 and store the resultant back in R 0 .
  • the first row location therefore will maintain its original value of A 0 in R 0
  • the second row location will maintain a value of A 0 +A 1 in R 0
  • the third row location will maintain a value of A 0 +A 1 +A 2 in R 0
  • the fourth row location will maintain a value of A 0 +A 1 +A 2 +A 3 in R 0 .
  • each of the other row locations because their location remains greater than 2 N ⁇ 1, will select the shifted content in R 1 (rather than the null value in R 2 ), add the content of R 1 to the content in R 0 and store the resultant in R 0 .
  • each of the row locations other than the first, second and third row locations will keep an accumulated sum based on its original content and its total shifted in content.
  • the prefix sum operation is complete. If the row were of dimension sixteen, only one more set of operations that shift the R 1 register contents by eight locations would be needed to accumulate the summation unique to all 16 different locations in all sixteen execution lanes.
  • FIGS. 17 and 18 a through 18 d pertain to a row/column find minimum operation that can also be executed on an image processor having a two-dimensional execution lane array and a corresponding two-dimensional shift register. Row/column find min operations are particularly useful for statistics computations and block matching post-processing.
  • a column find minimum operation can be implemented on a same processor that implements a row find minimum operation. Additionally, the minimum for a row (or column) can simultaneously be found for any number of rows (or columns) in the register array (including up to all rows/columns). Additionally, the dimension of the row/column is only shown to be 8 locations wide, whereas, in actual implementations the execution lane and shift register arrays may be 16 ⁇ 16 or even larger.
  • the resultant of a row find minimum operation corresponds to the smallest value amongst all values within a same row and its location/position (also referred to as its index) in the row.
  • the resultant of a column find minimum operation corresponds to the smallest value amongst all values within a same column and its location/position within the column.
  • the row/column find minimum operation employs the use of a two dimensional shift register than can roll shifts between array edge locations 1701 .
  • FIGS. 18 a through 18 d show an embodiment of machine level operations for a row prefix operation. Initially, as observed in FIG. 18 a , a row is loaded with data values A 0 through A 7 in the respective R 0 register location of each execution lane. Also, the index of each row location is loaded into the R 1 register space of each execution lane.
  • the content of the R 0 and R 1 register locations are shifted one unit into the R 2 and R 3 register space of a neighboring execution lane's register space.
  • the respective values of the R 0 and R 2 registers are then compared within each execution lane.
  • the minimum value of the comparison and its corresponding index are stored into the R 0 and R 1 register space. That is, if the R 0 value is less than the R 2 value, the R 0 and R 1 registers maintain their original content. Whereas, if the R 2 value is less than the R 0 value, the R 2 value is written into R 0 and the R 3 value is written into R 1 . This has the effect of keeping the minimum value of the comparison in R 0 and its index in R 1 .
  • each execution lane will have the minimum value of the entire row in its R 0 register space and its corresponding index in its R 1 register space (the row location that was originally provided with the minimum value will find its own row location identified in its R 1 register space). If the row were of dimension sixteen, only one more set of operations based on a shift of the R 0 and R 1 register contents downstream in the shift register by eight locations would be needed to provide the minimum of all sixteen different locations in all sixteen execution lanes.
  • find maximum operation could also be implemented using the same principles described above except that the core math operation includes finding the maximum rather than finding the minimum.
  • FIGS. 19 a,b and 20 pertain to a matrix multiply.
  • a matrix multiply is particularly useful for discrete fourier or cosine transforms (which are common primitives in compression and filtering) and to express larger matrix/multiply operations (which are commonly used in image recognition).
  • a matrix multiply of two matrices A and B is performed by summing, for each matrix coordinate location in the resultant, products of the elements in the row of the coordinate location and their corresponding elements in the column of the coordinate location.
  • FIG. 19 b shows the resultant matrix X for the matrix multiple of matrices A and B in FIG. 19 a .
  • associated partial product terms of matrices A and B for two coordinate locations 1901 , 1902 in the resultant matrix C are specially shown.
  • the resultant product for coordinate location c 12 in the resultant matrix C of FIG. 19 b is
  • the resultant for any coordinate location x,y in the resultant matrix C can be expressed as:
  • ⁇ k 1 to 4 ( a x,k )*( b k,y ).
  • FIGS. 20 a through 20 e show an embodiment of a matrix multiply operation that uses a two dimensional execution lane array and the unique shifting advantages of a corresponding two dimensional shift register array.
  • two matrices A and B are loaded into the two dimensional shift register array.
  • the values of matrix A may be loaded into the R 0 register space of the two dimensional shift register and the values of matrix B may be loaded into the R 1 register space of the two dimensional shift register array such that each matrix coordinate corresponds to a different execution lane's associated register space.
  • 4 ⁇ 4 matrices are depicted although in actual implementations larger matrices can be multiplied with a corresponding, larger dimensioned shift register array.
  • a rotational shearing algorithm shift is applied to both matrices with a row-wise rotational shearing algorithm shift sequence being applied to matrix A and a column-wise rotational shearing algorithm shift sequence being applied to matrix B.
  • a rotational shearing algorithm increases shift amount by N ⁇ 1 where N is the position in the matrix.
  • the first row of matrix A is not shifted at all, the second row of matrix A is shifted one unit, the third row of matrix A is shifted two units and the fourth row of matrix A is shifted three units.
  • the first column of matrix B is not shifted at all, the second column of matrix B is shifted one unit, the third column of matrix B is shifted two units and the fourth column of matrix B is shifted three units.
  • the two dimensional shift register array is understood to be able to roll elements at array edges for both row oriented shifts and column oriented shifts.
  • the two dimensional shift register array is able to shift different rows by different horizontal shift amounts and shift different columns by different vertical shift amounts while simultaneously executing the shift instructions across all execution lanes for a same matrix (in various embodiments, a same horizontal shift amount must be specified for lanes in a same row and a same vertical shift amount must be specified for lanes in a same column).
  • the shearing of both the A and B matrices can be completed in as few as two cycles (i.e., all shifts for one matrix are performed in one cycle assuming the shift register can implement multiple hop shifts in a single cycle).
  • a multiply operation is performed where each execution lane multiplies the A and B values in its corresponding two dimensional shift register space.
  • a values are, e.g., kept in R 0 space and B values are kept in R 1 space.
  • the resultant of the multiplication is stored in local R 2 space. Null values may be loaded as an initial condition into R 3 space and the resultant of the multiplication in R 2 is added to the contents of R 3 .
  • the resultant of the summation is stored back in R 3 .
  • R 3 takes on the roll of accumulator that accumulates the summation of partial product terms over the course the matrix multiply operation.
  • FIG. 20 b explicitly shows the contents in the resultant R 3 space after the first iteration for coordinate locations c 11 and c 22 in the resultant matrix C originally depicted in FIG. 19 b .
  • the R 3 register space at location C 11 contains the partial product term a 11 *b 11
  • the R 3 register space at location C 22 contains the partial product term (a 21 *b 12 ).
  • the R 0 registers containing matrix A data are then horizontally shifted one unit and the R 1 registers containing matrix B data are vertically shifted one unit.
  • the mathematical operations described just above with respect to FIG. 20 b are then repeated.
  • the R 3 register space of each lane initially contains the first iteration's partial product term (e.g., a 11 *b 11 in R 3 of location c 11 and a 21 *b 12 in R 3 of location c 22 ).
  • register R 3 will contain the accumulated sum of both partial products that have so far been calculated. That is, R 3 in location c 11 will have the sum (a 11 *b 11 )+(a 12 *b 21 ) and R 3 in location c 22 will have the sum (a 21 *b 12 )+(a 22 *b 22 ).
  • FIG. 21 depicts a two dimensional DFT (2D DFT).
  • a 2D DFT is particularly useful for noise reduction and accelerating convolutions.
  • a 2D DFT can be expressed as the summation over two dimensional space of the product of two complex terms 2101 , 2102 .
  • a first of the complex terms 2101 corresponds to a phasor whose magnitude and phase is a function of time and frequency.
  • the first complex term 2101 is expressly calculated as a first matrix of coefficients.
  • a second of the complex terms 2102 corresponds to the signal that is being transformed from the spatial domain to the frequency domain.
  • FIG. 21 represents the first complex term 2101 as Re1+jlm1 and represents the second complex 2102 term as Re2+jlm2.
  • the real part of (Re1+jlm1)*(Re2+jlm2) can be expressed as (Re1*Re2) ⁇ (Im1*Im2) while the imaginary part can be expressed as j((Re1*Im2)+(Re2*Im1)).
  • the summations of the 2D DFT over 2D space just like the matrix multiply discussed at length immediately above, add the products of elements in a row of a coordinate location by corresponding elements in the column of the coordinate location.
  • the real part of the DFT resultant can be calculated by performing a matrix multiply on an array of Re1 values and an array of Re2 values and subtracting from the resultant array the result of a matrix multiply on an array of Im1 values and Im2 values.
  • the imaginary part of the DFT resultant can be calculated by performing a matrix multiply on an array of Re1 values and an array of Im2 values and adding the resultant array to the result of a matrix multiply on an array of Re2 values and Im1 values.
  • FIG. 22 a shows machine operations for calculating the real part of the DFT.
  • an array of Re1 values are loaded into the R 0 register space of the two-dimensional shift register array
  • an array of Re2 values are loaded into the R 1 register space of the two-dimensional shift register array
  • an array of Im1 values are loaded into the R 2 register space of the two-dimensional shift register array
  • an array of Im2 values are loaded into the R 3 register space of the two-dimensional shift register array.
  • a rotational shearing algorithm is then applied to each of the array values with the Re1 and the Im1 values being sheared horizontally and the Re2 and Im2 values being sheared vertically.
  • an Re1*Re2 matrix multiply and an Im1*Im2 matrix multiply are then performed with the resultants being kept in the R 0 and R 2 register space, respectively.
  • the content of the R 2 register space is then subtracted from the R 0 register spacing with the resultant of the subtraction leaving the real part of the DFT transform in the R 0 register space as observed in FIG. 22 d.
  • the real part resultant in the R 0 register space is moved to R 4 register space (if it exists) or written out to local memory that is coupled to the shift register array. Then, the original Re1 and Im1 values are re-written back into the R 0 and R 1 register space (e.g., from the same local memory) and horizontally sheared so that the register content of FIG. 22 a is recreated in the two-dimensional shift register array.
  • An Re1*Im2 matrix multiply and an Re2*Im1 matrix multiply are then performed with the resultants being kept in the R 0 and R 2 register space, respectively. That is, a matrix multiply is performed on the contents of R 0 and R 3 with the resultant written back to R 0 , and, a matrix multiply is performed on the contents of R 2 and R 1 the contents being written into R 2 .
  • the resultant matrices in R 0 and R 2 are shown in FIG. 22 e .
  • the content of the R 0 register space is then added to the content of the R 2 register spacing and written back to R 0 . This leaves the imaginary part of the DFT transform in the R 0 register space as depicted in FIG. 22 f.
  • a fast fourier transform is a faster, less computationally intensive approach to a DFT.
  • FFTs rely on special efficient algorithms to rapidly convert time or space domain data into frequency domain data.
  • a critical component of such algorithms is a butterfly algorithm.
  • An exemplary butterfly algorithm is depicted in FIG. 23 .
  • a butterfly operation is defined by a stage where the specific stage determines an amount of swapping that transpires between elements of a same row or column.
  • a complete FFT includes performing mathematical operations on the swapped content of multiple, different stage butterfly operations in between the butterfly operations.
  • FIG. 23 shows each of 1, 2, and 4 stage butterfly operations.
  • neighboring elements are swapped.
  • neighboring pairs of elements are swapped.
  • 4 stage butterfly groups of 4 neighboring elements are swapped.
  • elements in a first array of signal data are swapped according to each of multiple butterfly stages with mathematical operations being performed on the swapped signal data elements.
  • FIG. 24 a shows machine level shift operations that can be used to effect a 1 stage 1 butterfly across an array of signal data that is stored in two dimensional R 0 register space. For simplicity only one row is shown. It is pertinent to recognize that multiple (e.g., all) rows or columns of an array in a two dimensional shift register may be simultaneously processed in accordance with the particular row that is observed.
  • the shift register is initially loaded with A 0 through A 7 across each of its rows in its R 0 register space.
  • the shift register then shifts the R 0 register content one unit to the right and each execution lane stores the data that has been just been shifted into its location in its R 1 register space.
  • the shift register shifts the R 0 register content two units to the left (the resultant of which is labeled R 0 ′).
  • Each execution lane then executes a selection operation in which either its local R 0 content or its local R 1 content is stored in R 0 (i.e., if R 0 is selected, the content of R 0 remains unchanged) depending on the location of the lane.
  • even lanes select R 0 while odd lanes select R 1 .
  • the correctly swapped values are in the R 0 register space of each execution lane (labeled as R 0 ′′).
  • FIG. 24 b and FIG. 24 c depict 2 stage and 4 stage butterfly operations. Processing is similar to the 1 stage butterfly operation described just above, except that in the case of the 2 stage butterfly the shift register array shifts the R 0 register content two units to the right and then four units to the left. Every other even lane and its rightmost neighbor select from one of R 1 and R 0 ′′ whereas the other even lanes an their rightmost neighbor select from the other of R 1 and R 0 ′′.
  • the shift register array shifts the contents of R 0 four units to the right and then selects all values as they reside in R 0 (labeled R 0 ′).
  • FIG. 25 shows a depiction of block matching.
  • Block matching is particularly useful for motion estimation (e.g., for video compression), image stabilization, and image fusion algorithms (e.g., exposure fusion, and temporal noise fusion).
  • a specific feature in a first base (e.g., previous) image looked for in an alternative (e.g., later) image.
  • the block ABCD that is present in the base image needs to be found in the alternative image.
  • FIGS. 26 a through 26 d shows a method for performing block matching on an image processor having a two dimensional execution lane array and a two dimensional shift register array.
  • the pixels of the alternative image are kept in the R 0 register space of the two dimensional shift register.
  • a first pixel of the feature in the base image that is being looked for e.g., “A”
  • a first pixel of the feature in the base image that is being looked for (e.g., “A”) is broadcast to all execution lanes and an absolute difference is taken on the content in the R 0 register space and the value “A” and the resultant is stored in R 1 (for simplicity it is assumed that no other pixels in the alternative image have any of the looked for feature's values (A, B, C, D).
  • the resultant in R 1 should be at (or near) zero. All other resultants in R 1 should be substantially non zero.
  • the alternative image is then shifted one unit in the two-dimensional shift register, a next pixel value “B” in the feature being looked for is broadcast to all execution lanes and the absolute difference is again taken and stored in R 1 .
  • the particular execution lane array location 2601 that has had two consecutive pixel matches should have the lowest resultant value in R 1 .
  • This particular execution lane location is the location where the particular order of pixel values that are being broadcast aligns with the particular scanning/shifting motion of the alternative image in R 0 of the shift register array.
  • the process continues with each next iteration broadcasting a next pixel value and shifting the alternative image data in a particular scan order.
  • a number of iterations sufficient to broadcast all sought for image pixels and to correspondingly shift the alternative image in R 0 over an area that corresponds to the size of the looked for image, ideally, only one location 2601 in the execution lane array will have experienced a match on every iteration cycle.
  • this particular array location 2601 should be able to maintain a zero or near zero value in its R 1 register space (or at least a smaller value than the other execution lanes) after all iterations have been completed.
  • a findmin operation as discussed above is executed on the R 1 register space across all rows in the array. The lowest corresponding value in each row will then be kept at each location of its row. A findmin operation is then executed on the R 1 register space across all columns in the array. The resultant should identify the pixel that matched the base image on every iteration which, in turn, can be used to identify the precise location of the looked for image in the alternative array.
  • FIG. 27 shows a pre-runtime development environment in which a programmer designs a high level image processing function and the application development environment (which may include the virtual ISA environment discussed at length above with respect to FIGS. 1 through 6 ) provides for any/all of the aforementioned special operations so that the developer does not have the write them from scratch.
  • the developer may specifically call out any of the operations discussed at length above and/or the development environment automatically provides them from a library 2701 in response.
  • the developer's need for such operations may be implied or deduced (such as a matrix multiply in the case of a 2D DFT) and the development environment automatically inserts program code from the library 2701 that performs these functions (e.g., as part of a compilation process).
  • the program code that performs the above described operations or alternate embodiments thereof may be expressed in higher level (e.g., virtual ISA) program code or lower level object code.
  • the higher level virtual ISA code may specify data values to be operated upon as memory reads having x,y address coordinates, while, the object code may instead comprehend these data accesses as two-dimensional shift register operations (such as any of the shift operations described above or similar embodiments).
  • a compiler may convert the x,y reads in the development environment into corresponding shifts of the two dimensional shift register that are specified object code (e.g., a read in the development environment having x,y coordinates (+2, +2) may be realized in object code as a shift to the left two spaces and a shift down of two spaces).
  • such prewritten routines may be invoked during runtime (e.g., by a just-in-time compiler) rather than pre-runtime.
  • Section 1.0 may be instantiated on a computer system.
  • an image processor as described above in Section 2.0 may be embodied in hardware on a computer system (e.g., as part of a handheld device's System on Chip (SOC) that processes data from the handheld device's camera).
  • SOC System on Chip
  • the various image processor architecture features described above are not necessarily limited to image processing in the traditional sense and therefore may be applied to other applications that may (or may not) cause the image processor to be re-characterized.
  • the image processor may be characterized as a graphics processing unit.
  • the image processor architectural features described above may be applied to other technical applications such as video processing, vision processing, image recognition and/or machine learning.
  • the image processor may be integrated with (e.g., as a co-processor to) a more general purpose processor (e.g., that is or is part of a CPU of computing system), or, may be a stand alone processor within a computing system.
  • a more general purpose processor e.g., that is or is part of a CPU of computing system
  • circuit descriptions may be embodied within a semiconductor chip and/or as a description of a circuit design for eventual targeting toward a semiconductor manufacturing process.
  • circuit descriptions may take of the form of a (e.g., VHDL or Verilog) register transfer level (RTL) circuit description, a gate level circuit description, a transistor level circuit description or mask description or various combinations thereof.
  • RTL register transfer level
  • Circuit descriptions are typically embodied on a computer readable storage medium (such as a CD-ROM or other type of storage technology).
  • an image processor as described above may be embodied in hardware on a computer system (e.g., as part of a handheld device's System on Chip (SOC) that processes data from the handheld device's camera).
  • SOC System on Chip
  • the image processor is embodied as a hardware circuit
  • the image data that is processed by the image processor may be received directly from a camera.
  • the image processor may be part of a discrete camera, or, part of a computing system having an integrated camera.
  • the image data may be received directly from the camera or from the computing system's system memory (e.g., the camera sends its image data to system memory rather than the image processor).
  • a graphics processor unit which renders animation
  • FIG. 28 provides an exemplary depiction of a computing system. Many of the components of the computing system described below are applicable to a computing system having an integrated camera and associated image processor (e.g., a handheld device such as a smartphone or tablet computer). Those of ordinary skill will be able to easily delineate between the two.
  • an integrated camera and associated image processor e.g., a handheld device such as a smartphone or tablet computer.
  • the basic computing system may include a central processing unit 2801 (which may include, e.g., a plurality of general purpose processing cores 2815 _ 1 through 2815 _N and a main memory controller 2817 disposed on a multi-core processor or applications processor), system memory 2802 , a display 2803 (e.g., touchscreen, flat-panel), a local wired point-to-point link (e.g., USB) interface 2804 , various network I/O functions 2805 (such as an Ethernet interface and/or cellular modem subsystem), a wireless local area network (e.g., WiFi) interface 2806 , a wireless point-to-point link (e.g., Bluetooth) interface 2807 and a Global Positioning System interface 2808 , various sensors 2809 _ 1 through 2809 _N, one or more cameras 2810 , a battery 2811 , a power management control unit 2824 , a speaker and microphone 2813 and an audio coder/decoder 2814 .
  • An applications processor or multi-core processor 2850 may include one or more general purpose processing cores 2815 within its CPU 2801 , one or more graphical processing units 2816 , a memory management function 2817 (e.g., a memory controller), an I/O control function 2818 and an image processing unit 2819 .
  • the general purpose processing cores 2815 typically execute the operating system and application software of the computing system.
  • the graphics processing units 2816 typically execute graphics intensive functions to, e.g., generate graphics information that is presented on the display 2803 .
  • the memory control function 2817 interfaces with the system memory 2802 to write/read data to/from system memory 2802 .
  • the power management control unit 2824 generally controls the power consumption of the system 2800 .
  • the image processing unit 2819 may be implemented according to any of the image processing unit embodiments described at length above in the preceding sections. Alternatively or in combination, the IPU 2819 may be coupled to either or both of the GPU 2816 and CPU 2801 as a co-processor thereof. Additionally, in various embodiments, the GPU 2816 may be implemented with any of the image processor features described at length above.
  • Each of the touchscreen display 2803 , the communication interfaces 2804 - 2807 , the GPS interface 2808 , the sensors 2809 , the camera 2810 , and the speaker/microphone codec 2813 , 2814 all can be viewed as various forms of I/O (input and/or output) relative to the overall computing system including, where appropriate, an integrated peripheral device as well (e.g., the one or more cameras 2810 ).
  • I/O components may be integrated on the applications processor/multi-core processor 2850 or may be located off the die or outside the package of the applications processor/multi-core processor 2850 .
  • one or more cameras 2810 includes a depth camera capable of measuring depth between the camera and an object in its field of view.
  • Application software, operating system software, device driver software and/or firmware executing on a general purpose CPU core (or other functional block having an instruction execution pipeline to execute program code) of an applications processor or other processor may perform any of the functions described above.
  • Embodiments of the invention may include various processes as set forth above.
  • the processes may be embodied in machine-executable instructions.
  • the instructions can be used to cause a general-purpose or special-purpose processor to perform certain processes.
  • these processes may be performed by specific hardware components that contain hardwired logic for performing the processes, or by any combination of programmed computer components and custom hardware components.
  • Elements of the present invention may also be provided as a machine-readable medium for storing the machine-executable instructions.
  • the machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, FLASH memory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, propagation media or other type of media/machine-readable medium suitable for storing electronic instructions.
  • the elements may be downloaded as a computer program transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).
  • a communication link e.g., a modem or network connection

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JP2018568290A JP6837084B2 (ja) 2016-07-01 2017-06-08 二次元実行レーンアレイおよび二次元シフトレジスタを有する画像プロセッサ上でのブロック処理のためのコアプロセス
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DE102017113867.6A DE102017113867A1 (de) 2016-07-01 2017-06-22 Kernprozesse für Blockoperationen an einem Bildprozessor mit einer zweidimensionalen Ausführungsbahnmatrix und einem zweidimensionalen Schieberegister
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TW107141459A TWI690896B (zh) 2016-07-01 2017-06-30 影像處理器、由其執行之方法、及非暫態機器可讀儲存媒體
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