WO2009031302A1 - 固体撮像素子及びその駆動方法 - Google Patents

固体撮像素子及びその駆動方法 Download PDF

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Publication number
WO2009031302A1
WO2009031302A1 PCT/JP2008/002426 JP2008002426W WO2009031302A1 WO 2009031302 A1 WO2009031302 A1 WO 2009031302A1 JP 2008002426 W JP2008002426 W JP 2008002426W WO 2009031302 A1 WO2009031302 A1 WO 2009031302A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage units
pixels
frames
signals
pixel output
Prior art date
Application number
PCT/JP2008/002426
Other languages
English (en)
French (fr)
Inventor
Shigetoshi Sugawa
Yasushi Kondo
Hideki Tominaga
Original Assignee
Tohoku University
Shimadzu Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tohoku University, Shimadzu Corporation filed Critical Tohoku University
Priority to CN200880105556XA priority Critical patent/CN101796821B/zh
Priority to EP08829005.1A priority patent/EP2192765B1/en
Priority to US12/676,505 priority patent/US8482640B2/en
Priority to JP2009531124A priority patent/JP4844853B2/ja
Publication of WO2009031302A1 publication Critical patent/WO2009031302A1/ja

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/587—Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/767—Horizontal readout lines, multiplexers or registers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

Abstract

　画素領域（２ａ）内に二次元状に配列された画素（１０）毎に独立した画素出力線（１４）を設け、各画素出力線（１４）に複数の記憶部を接続する。連続読み出しモードでは、全画素で同時に光電荷蓄積を実行し、各画素（１０）から画素出力線（１４）を通して記憶部に一斉に信号を保持した後に、各記憶部に保持した信号を逐次読み出して出力する。一方、バースト読み出しモードでは、全画素（１０）で同時に光電荷蓄積を実行し、各画素（１０）から画素出力線（１４）を通して記憶部に一斉に信号を保持させる、という動作を複数の記憶部に対して順番に実行することで複数フレームの信号を保持する。撮影停止の指示を受けて新たな信号の保持を停止し、その時点で記憶部に保持されている複数フレーム分の画像信号を逐次読み出し出力する。これにより、フレーム数は限られるものの非常に高速である撮影とこれより速度は下がるもののフレーム数の制約のない撮影とを行うことができる。
PCT/JP2008/002426 2007-09-05 2008-09-04 固体撮像素子及びその駆動方法 WO2009031302A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN200880105556XA CN101796821B (zh) 2007-09-05 2008-09-04 固体摄像元件和该固体摄像元件的驱动方法
EP08829005.1A EP2192765B1 (en) 2007-09-05 2008-09-04 Solid-state image sensor and drive method for the same
US12/676,505 US8482640B2 (en) 2007-09-05 2008-09-04 Solid-state image sensor and drive method for the same
JP2009531124A JP4844853B2 (ja) 2007-09-05 2008-09-04 固体撮像素子及びその駆動方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-230179 2007-09-05
JP2007230179 2007-09-05

Publications (1)

Publication Number Publication Date
WO2009031302A1 true WO2009031302A1 (ja) 2009-03-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/002426 WO2009031302A1 (ja) 2007-09-05 2008-09-04 固体撮像素子及びその駆動方法

Country Status (7)

Country Link
US (1) US8482640B2 (ja)
EP (3) EP2192765B1 (ja)
JP (1) JP4844853B2 (ja)
KR (1) KR101036596B1 (ja)
CN (1) CN101796821B (ja)
TW (1) TWI405462B (ja)
WO (1) WO2009031302A1 (ja)

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CN102202189A (zh) * 2010-03-25 2011-09-28 索尼公司 固体摄像装置和电子装置
WO2012107995A1 (ja) * 2011-02-08 2012-08-16 国立大学法人東北大学 固体撮像素子及びその駆動方法
JP2018038073A (ja) * 2015-05-29 2018-03-08 キヤノン株式会社 撮像素子および撮像装置
JP2021150846A (ja) * 2020-03-19 2021-09-27 株式会社東芝 固体撮像装置

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JP2015060053A (ja) 2013-09-18 2015-03-30 株式会社東芝 固体撮像装置、制御装置及び制御プログラム
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US10291813B2 (en) 2015-04-23 2019-05-14 Google Llc Sheet generator for image processor
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US10095479B2 (en) * 2015-04-23 2018-10-09 Google Llc Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
US9769356B2 (en) 2015-04-23 2017-09-19 Google Inc. Two dimensional shift array for image processor
US10313641B2 (en) 2015-12-04 2019-06-04 Google Llc Shift register with reduced wiring complexity
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Publication number Priority date Publication date Assignee Title
JP2010219998A (ja) * 2009-03-18 2010-09-30 Hitachi Kokusai Electric Inc 撮像方法及び撮像装置並びに撮像システム
CN102202189A (zh) * 2010-03-25 2011-09-28 索尼公司 固体摄像装置和电子装置
WO2012107995A1 (ja) * 2011-02-08 2012-08-16 国立大学法人東北大学 固体撮像素子及びその駆動方法
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JP2018038073A (ja) * 2015-05-29 2018-03-08 キヤノン株式会社 撮像素子および撮像装置
JP2021150846A (ja) * 2020-03-19 2021-09-27 株式会社東芝 固体撮像装置
JP7330124B2 (ja) 2020-03-19 2023-08-21 株式会社東芝 固体撮像装置

Also Published As

Publication number Publication date
KR20100039884A (ko) 2010-04-16
EP2663071B1 (en) 2015-11-18
US20100188538A1 (en) 2010-07-29
EP2192765B1 (en) 2015-11-11
CN101796821A (zh) 2010-08-04
US8482640B2 (en) 2013-07-09
EP2192765A4 (en) 2010-08-11
EP2192765A1 (en) 2010-06-02
EP2665256B1 (en) 2015-11-18
EP2665256A1 (en) 2013-11-20
EP2663071A2 (en) 2013-11-13
TW200920118A (en) 2009-05-01
EP2663071A3 (en) 2013-11-20
TWI405462B (zh) 2013-08-11
KR101036596B1 (ko) 2011-05-24
JP4844853B2 (ja) 2011-12-28
JPWO2009031302A1 (ja) 2010-12-09
CN101796821B (zh) 2012-12-12

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