WO2012107995A1 - 固体撮像素子及びその駆動方法 - Google Patents
固体撮像素子及びその駆動方法 Download PDFInfo
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- WO2012107995A1 WO2012107995A1 PCT/JP2011/052602 JP2011052602W WO2012107995A1 WO 2012107995 A1 WO2012107995 A1 WO 2012107995A1 JP 2011052602 W JP2011052602 W JP 2011052602W WO 2012107995 A1 WO2012107995 A1 WO 2012107995A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
Definitions
- the present invention relates to a solid-state imaging device and a driving method thereof, and more particularly to a solid-state imaging device capable of high-speed operation suitable for photographing extremely high-speed phenomena such as destruction, explosion, and combustion, and a driving method thereof.
- a high-speed imaging device for continuously capturing high-speed phenomena such as explosion, destruction, combustion, collision, and discharge for a short time is known (see Non-Patent Document 1, etc.).
- Such a high-speed imaging device requires extremely high-speed imaging at about 1 million frames / second or more. Therefore, a solid-state image sensor having a special structure and capable of high-speed operation is used, which is different from a normal image sensor used for a general video camera or a digital camera.
- a CCD-type solid-state imaging device called a pixel peripheral recording type imaging device described in Patent Document 1 and a MOS-type solid-state imaging described in Patent Documents 2 and 3 Devices are known.
- the latter is proposed by the present inventors in order to solve the problems in the former, and includes a pixel including a photodiode and a memory cell (1 to 1 corresponding to each pixel and for storing an image signal).
- a memory type solid-state imaging device having a structure in which a memory array unit having a large number of capacitors is two-dimensionally arranged in two spatially separated regions (pixel region and storage region).
- the total number of pixels is equal to the total number of memory array units, and one pixel and one memory array unit are connected by independent column lines. Yes. Therefore, it is possible to transfer a signal from each pixel to the memory array unit through the column line all at once.
- the number of column lines equal to the total number of pixels is required, and the ratio of the column line to the wiring area on the element chip increases, so it is difficult to increase the aperture ratio of the light receiving portion (photodiode).
- the solid-state imaging device described in Patent Document 3 has a structure in which N pixels (where N is an integer of 2 or more) and N memory array units are connected by a common column line. ing. Therefore, the total number of column lines is only the total number of pixels / N, and the area of the column line wiring region can be reduced, which is advantageous in increasing the aperture ratio of the light receiving portion. Instead, it is not possible to transfer pixel signals from each pixel to the memory array unit through the column line at the same time for all pixels. Instead, the pixel signals are transferred to the memory array unit in a time division manner in N pixels that share the column line. There is a need to.
- a source is provided inside each pixel in order to write a voltage signal from the pixel to the memory cell in the memory array unit by driving the column line.
- load current sources of the source follower amplifier are collectively arranged in a current source region provided between the pixel region and the storage region. This is mainly for reducing the pixel size and effectively using the area on the element chip.
- the line width of the column line which is a part of the load to be driven, is on the order of submicrons (for example, 0.28 ⁇ m), and the length is such that the pixel area and the storage area are separated.
- the maximum length is as long as several millimeters. Therefore, the column line has a large parasitic resistance (for example, about 1 k ⁇ for Al wiring), and a large parasitic capacitance is also generated because a plurality of column lines are extended in parallel on the element chip (for example, 1 pF).
- the bias current of the source follower amplifier that drives the column line is, for example, 100 ⁇ A (an example only because it depends on the size of the source follower amplifier). It is necessary to.
- the bias current flows through the column line itself, so that a voltage drop occurs due to the parasitic resistance described above, and the load current source side output terminal of the column line An offset voltage is generated between the pixel side input terminal. Since there is a large difference in the distance to the current source region between the pixel near the center of the pixel region and the pixel located near the lower end of the pixel region (region close to the current source region), the pixel signal voltages in these pixels have different offset voltages. Will have. Further, since a high resistance column line is interposed between the drive transistor of the source follower amplifier in the pixel and the load current source, the gain characteristic of the source follower amplifier is deteriorated. The degree of deterioration of the gain characteristic is also greatly different between the pixel near the center of the pixel area and the pixel located near the lower end of the pixel area, and therefore has a different gain characteristic for each pixel.
- the increase in ground potential as described above is greater at the center than at the left and right ends of the element chip, and this also occurs for each pixel. This is a major factor that causes different gain characteristics.
- the above-described offset voltage and gain characteristics that differ for each pixel are noise factors that degrade the quality of the pixel signal.
- the exposure time (charge accumulation time) at the time of shooting is extremely short, so that the signal level itself at each pixel is considerably low. It is very important to reduce the noise and improve the S / N of the pixel signal as much as possible.
- the present invention has been made in view of the above problems, and the object of the present invention is to reduce the noise applied to the pixel signal by reducing the difference in offset voltage and gain characteristics between the pixels, thereby improving the image quality.
- Another object of the present invention is to provide a solid-state imaging device capable of increasing the shooting speed while maintaining the same image quality, and a driving method thereof.
- the solid-state imaging device made to solve the above-described problems is a) a photodiode, a detection node for converting the photocharge generated by the photodiode from a charge signal to a voltage signal, a transfer gate for controlling transfer of the photocharge from the photodiode to the detection node, and A pixel region in which a plurality of pixels including a buffer circuit that sends a voltage signal from the detection node to a pixel output line described later is disposed; b) An area separated from the pixel area, in which a memory unit corresponding to each pixel is provided, and a plurality of memory cells are provided therein, and the same number of memory units are arranged.
- the buffer circuit includes at least one current driver that drives the pixel output line, and the current driver includes a current source serving as a load disposed inside the pixel.
- a solid-state imaging device made to solve the above problems is a) a photodiode, a detection node for converting the photocharge generated by the photodiode from a charge signal to a voltage signal, a transfer gate for controlling transfer of the photocharge from the photodiode to the detection node, and A pixel region including a plurality of pixels including a buffer circuit that sends a voltage signal from the detection node to the pixel output line; b) a region separated from the pixel region, and a storage region in which a storage unit corresponding to each pixel and having a plurality of storage cells provided therein is disposed; c) N pixels (N is an integer of 2 or more) in the pixel area and N storage units in the storage area associated with the N pixels for each of N pixels and storage units.
- the buffer circuit selectively connects at least one current driver that drives the pixel output line and one of N pixels connected to the same pixel output line to the pixel output line.
- the selection switch is characterized in that N pixel selection signal lines are wired independently of each other.
- the current driver is typically a source follower amplifier.
- the current source serving as the load of the current driving unit is concentrated in the current source region, whereas the solid-state imaging according to the first and second inventions.
- a current source serving as a load of the current driver is arranged inside each pixel. For this reason, for example, since the bias current of the current driving unit which is a source follower amplifier does not flow through the pixel output line, a voltage drop due to the resistance of the pixel output line itself and a signal voltage offset due to it do not occur. The variation of the offset voltage is also eliminated.
- the pixel output line having high resistance and capacitance is substantially included in the circuit of the current driver, whereas in the solid-state imaging device according to the first and second inventions, Since the output line is separated from the circuit of the current driver, the gain characteristic in the current driver of each pixel is improved, and no gain error between the pixels occurs.
- the load current source of each pixel is distributed in the pixel region without being intensively arranged in the element chip.
- the current feedback path is distributed.
- the pixel signal can be sent to the storage unit through the pixel output line all at once.
- the solid-state imaging device according to the second invention since one pixel output line is shared by N pixels, a set of N pixels is turned on / off by a pixel selection switch included in each pixel. Among these, a pixel that outputs a signal to one pixel output line is selected. When a signal is sent from a certain pixel in a set of N pixels to the pixel output line, the current driver of the other N ⁇ 1 pixels does not actually function.
- the buffer circuit includes a changeover switch for turning on / off the operation of the current driver.
- the changeover switch can be a transistor that cuts off a connection path between an amplifying transistor of the current driver and a transistor constituting a current source serving as a load thereof.
- a relay amplifier is inserted in the middle of each of the pixel output lines, and a plurality of the pixel outputs are provided in the storage area in order to arrange the relay amplifier. It is preferable that a plurality of relay amplifier regions be prepared along the line extending direction.
- one pixel output line is not driven only by the current driving unit arranged in the pixel, but is shared by the current driving unit and the relay amplifier arranged in the middle of the pixel output line. Can be driven.
- the drive load per amplifier is reduced, so that it is possible to drive at higher speed.
- the gain characteristic is further improved because less bias current is required.
- the current consumption in the pixel area is reduced by reducing the bias current generated by the current drive unit in the pixel, and the current consumption in the relay amplifier area distributed in the storage area is increased accordingly. As a result, it is possible to further alleviate the power concentration that causes the above-described increase in ground potential.
- one pixel output line is shared by N pixels, so that one image signal is transferred from each pixel to a memory cell in the memory unit. It takes about N times as long as the solid-state imaging device according to the first invention. This is a restriction for increasing the photographing speed in the solid-state imaging device according to the second invention.
- a driving method of the solid-state imaging device is a driving method for driving the solid-state imaging device according to the second invention, A first drive mode in which the N pixel selection switches are sequentially selected by a control signal passing through the N pixel selection signal lines, and the N pixels are sequentially connected to a common pixel output line; Second driving for selecting only a part of the N pixel selection switches using only a part of the N pixel selection signal lines and connecting a part of the N pixels to a common pixel output line. Mode, Is selectable.
- the first drive mode uses all pixels for shooting, whereas the second drive mode uses only some pixels for each set of N pixels without using all pixels. It is for shooting. That is, in the second drive mode, one image becomes a coarse image with some pixel signals thinned out, but there are few pixel signals to be sent from the pixel area to the storage area through one pixel output line. Therefore, the shooting speed can be increased accordingly. In other words, in the second drive mode, the shooting speed can be increased although the image quality is lower than in the first drive mode.
- the N pixels connected to the same pixel output line are an even number of pixels adjacent in the vertical direction, and in the second driving mode, Of the N pixels, only every other N / 2 pixels in the vertical direction are used, and every other pixel used in the pixel region even in the adjacent pixels in the horizontal direction.
- the pixel that has not been selected is selected.
- Corresponding storage units may also be assigned to increase the storage capacity for some of the selected pixels.
- noise factors such as an offset voltage between pixels and an error in gain characteristics are removed, and variations in ground potential are reduced.
- the quality of the pixel signal in each pixel that is, the SN ratio is improved, and the image quality can be improved.
- the solid-state imaging device driving method it is possible to increase the photographing speed while reducing the area of the region occupied by the pixel output line on the device.
- FIG. 1 is a schematic plan view showing a layout on a semiconductor chip of a solid-state imaging device that is a first embodiment of the present invention;
- storage unit in the solid-state image sensor of 1st Example. 4 is a schematic time chart of the operation in one pixel in the solid-state image sensor of the first embodiment.
- FIG. 10 is a schematic time chart of the operation in one pixel in the solid-state image sensor of the second embodiment.
- FIG. 6 is a schematic time chart of each drive mode in the solid-state image sensor of the second embodiment.
- FIG. 6 is a schematic time chart of each drive mode in the solid-state image sensor of the second embodiment.
- FIG. The conceptual diagram which shows the pixel position driven in the pixel half drive mode in the solid-state image sensor of 2nd Example.
- the figure which shows the connection state of the pixel in the solid-state image sensor of 3rd Example of this invention, a relay amplifier, and a memory
- FIG. 1 is a schematic plan view showing a layout on a semiconductor chip of a solid-state imaging device of this embodiment
- FIG. 2 is a diagram showing a connection state between a pixel and a storage unit
- FIG. 3 is a circuit of one pixel in a pixel region.
- FIG. 4 is a circuit diagram of one storage unit.
- this solid-state imaging device has one large pixel region 2 for receiving incident light and generating a pixel signal for each pixel, and two for holding the pixel signal until it is read out to the outside.
- the storage areas (first storage area 3 a and second storage area 3 b) divided into two are provided on the semiconductor substrate 1.
- the pixel area 2 and the storage areas 3a and 3b are areas separated from each other and gathered together.
- a total of N ⁇ M pixels 10 of N rows and M columns are arranged in a two-dimensional array in the substantially rectangular pixel region 2, and each of the pixel regions 2 has (N / 2) ⁇ M pixels 10. Is divided into two, a first pixel region 2a and a second pixel region 2b.
- (N / 2) ⁇ M storage units 30 are arranged in a two-dimensional array in each of the first and second storage areas 3a and 3b.
- the first storage area 3a is provided with a first vertical scanning circuit area 4a and a first horizontal scanning circuit area 5a
- the second storage area 3b is similarly provided with a second vertical scanning circuit area 4b and a second horizontal scanning circuit.
- a region 5b is attached.
- circuits such as a shift register and a decoder for controlling reading of signals from the storage cells included in the storage unit 30 in the first storage region 3a are disposed in the second vertical scanning circuit region 4b and the second horizontal scanning circuit region 5b.
- the solid-state imaging device of this embodiment is centered on a line (a straight line indicated by a dotted line in FIG. 1) that divides the pixel region 2 into two parts, a first pixel region 2a and a second pixel region 2b.
- a line a straight line indicated by a dotted line in FIG. 1
- the first pixel region 2a, the first storage region 3a, the first vertical scanning circuit region 4a, and the first horizontal scanning circuit region 5a The structure and operation will be described mainly.
- the number of pixels arranged in the pixel area 2 that is, the values of N and M can be determined arbitrarily. Increasing these values increases the resolution of the image, but on the other hand, the area of the entire chip increases, or if the chip area is the same, the chip area per pixel decreases, which is disadvantageous in terms of sensitivity. is there.
- the number of pixels arranged in each of the first pixel region 2a and the second pixel region 2b is 400 in the horizontal direction (horizontal direction) and 128 in the vertical direction (vertical direction).
- one pixel 10 in the pixel area 2a and one storage unit 30 in the storage area 3a are connected by one pixel output line 40, respectively. Therefore, the pixel area 2a and the storage area 3a are connected by the same number (in this example, 128 ⁇ 400) of pixel output lines 40 as the pixels 10 or the storage units 30 included in the areas 2a and 3a. Note that the outputs of all the storage units 30 arranged in the vertical direction in the storage area 3a are connected to a common vertical output line 41, and further connected to a common output line 43 via a vertical transfer gate 42. It is connected to the outside through 44.
- one pixel 10 includes a photodiode (PD) 11, a transfer transistor 12, a reset transistor 13, a floating diffusion (FD) 14, a first stage buffer transistor 15, and a first stage bias.
- the photodiode 11 generates light charges upon receiving light.
- the floating diffusion 14 temporarily accumulates photoelectric charges and converts them into voltage signals, and corresponds to a detection node in the present invention.
- the transfer transistor 12 is for transferring photocharge from the photodiode 11 to the floating diffusion 14 and corresponds to a transfer gate in the present invention.
- the reset transistor 13 is for discharging the charge accumulated in the floating diffusion 14, and corresponds to a reset element in the present invention.
- the first capacitor 18, the second capacitor 21, the first sampling transistor 19, and the second sampling transistor 20 constitute a correlated double sampling (CDS) circuit.
- the first stage buffer transistor 15 and the first stage bias transistor 17 are buffers that serve as an interface between the floating diffusion 14 and the correlated double sampling circuit.
- the source follower amplification transistor 22, the load current source transistor 24, and the output control transistor 25 are for outputting the charge signal accumulated in the floating diffusion 14 as a voltage signal to the pixel output line 40 through the CDS circuit. Yes, which corresponds to the buffer circuit in the present invention.
- Drive pulse signals ⁇ T, ⁇ R, ⁇ NS, ⁇ SS, and ⁇ X2 are respectively supplied to gate terminals of the transfer transistor 12, the reset transistor 13, the first sampling transistor 19, the second sampling transistor 20, and the output control transistor 25.
- a drive line for supplying (control signal) is connected. These drive lines are common to all the pixels 10 in the pixel region 2. As a result, simultaneous driving for charge accumulation operation or the like is performed in all the pixels 10 included in the pixel regions 2a and 2b.
- FIG. 5 is a schematic time chart of the operation from photoelectric conversion to signal transmission in one pixel 10. The operation in the pixel 10 will be described with reference to this.
- the floating diffusion 14 Before the signal charge is transferred from the photodiode 11 to the floating diffusion 14, the floating diffusion 14 is reset to the power supply voltage VR by turning on the reset transistor 13. However, after that, when the reset transistor 13 is turned off and the floating diffusion 14 is brought into a floating state, thermal noise is taken into the capacitor of the floating diffusion 14, so that the voltage of the floating diffusion 14 fluctuates, and the power supply voltage (reset voltage) It is not VR.
- reset noise When signal charges are transferred from the photodiode 11 to the floating diffusion 14 in the presence of this fluctuation component called reset noise, a signal in which the noise is superimposed on the signal charge is output as a voltage signal. . Therefore, the pixel signal is output while removing noise in the following procedure.
- the transfer transistor 12 is turned off, the photodiode 11 is in a floating state, and accumulation (exposure) of charges generated by photoelectric conversion is started.
- the floating diffusion 14 is reset to the reset voltage VR.
- the reset transistor is turned off at a time t2 ( ⁇ R: on ⁇ off) with a slight delay, the floating diffusion 14 enters a floating state.
- the voltage of the floating diffusion 14 at this time is the reset voltage VR + the reset noise voltage.
- the voltage applied to the gate terminal of the source follower amplification transistor 22 is determined.
- the voltage at this time is a voltage of [net signal voltage] ⁇ [gain of CDS circuit] from which the reset noise voltage is removed.
- the output control transistor 25 is turned on at time t7 ( ⁇ X2; off ⁇ on)
- the signal voltage not including reset noise in the floating diffusion 14 is output to the pixel via the source follower amplification transistor 22 as described above. Output to line 40.
- reset noise in the CDS circuit is not considered, but in reality, when the first capacitor 18 and the second capacitor 21 are in a floating state, reset noise can be generated as in the floating diffusion 14. . However, if the capacitances of the first capacitor 18 and the second capacitor 21 are made larger than the capacitance of the floating diffusion 14, the effect of the reset noise becomes relatively small and can be ignored in practice.
- the capacitor 37 is formed by, for example, a double polysilicon gate structure or a stack structure.
- a driving line for supplying a driving pulse signal of ⁇ WS that is common to all the storage units 30 is connected to the gate terminal of the writing transistor 31.
- a driving line for supplying a driving pulse signal of ⁇ VSR which is common to the vertical row units and is different for each row is connected to the gate terminal of the reading transistor 35. Further, the gate terminal of the sampling transistor 36 is different for each of the L sampling transistors included in one storage unit 30 and is common to the sampling transistors in the same order in all the storage units 30.
- a drive line for supplying a drive pulse signal is connected.
- the reading transistor 35 when a signal is output from the corresponding pixel 10 to the pixel output line 40, the reading transistor 35 is turned off to turn on the writing transistor 31, and further 128 sampling samples are output.
- any one of the transistors 36 is selectively turned on, a signal present on the signal line 32 in the storage unit can be written to the capacitor 37 connected to the turned-on sampling transistor.
- the sampling transistors 36 that are turned on by the drive pulse signal ⁇ VSR1 are sequentially scanned, whereby pixel signals corresponding to a continuous image of a maximum of 128 frames can be held in the capacitors 37, respectively.
- the read transistor 35 is turned on while the write transistor 31 is in the off state, and any one of the 128 sampling transistors 36 is selectively turned on, the sampling is performed.
- the pixel signal held in the capacitor 37 connected to the transistor for reading 36 can be read out on the signal line 32 in the storage unit and output to the outside through the reading buffer transistor 33 and the reading transistor 35.
- the sampling transistors 36 that are turned on by the drive pulse signal ⁇ VSR1 are sequentially scanned, so that pixel signals corresponding to continuous images of up to 128 frames respectively held in the capacitors 37 are sequentially That is, it can be read serially.
- a load current source transistor 24 that is a load current source of the source follower amplification transistor 22 is arranged inside each pixel 10. Therefore, even when the output control transistor 25 is turned on in the pixel 10 and the writing transistor 31 is turned on in the storage unit 30, the source follower amplification transistor 22 is connected to the pixel output line 40 connecting the pixel 10 and the storage unit 30. No bias current flows. Further, immediately after the output control transistor 25 is turned on, a current for charging / discharging the capacity of the pixel output line 40 and the capacity of the capacitor 37 of the write destination flows in the pixel output line 40. Does not flow at all. Therefore, no voltage drop occurs even if the resistance of the pixel output line 40 is somewhat large.
- the high-resistance pixel output line 40 is not arranged inside the source follower amplifier circuit, there is no reduction in gain characteristics caused by it, and the load current source transistors 24 are arranged in a distributed manner so that the ground potential can be reduced. Since the rise and fluctuation can be suppressed, the deterioration of the gain characteristic caused by the rise is negligible.
- FIG. 6 shows the input voltage-output voltage characteristics of a 12 pixel source follower amplifier.
- FIG. 6A shows the conventional configuration
- FIG. 6B shows the configuration of the above embodiment.
- the output voltage varies greatly due to the voltage drop due to the resistance of the pixel output line and the fluctuation of the bias current due to the potential rise of the feedback current path in the current source region.
- the potential drop due to the resistance of the pixel output line is very small, and the bias current fluctuation due to the potential rise of the feedback current path in the pixel area becomes the main factor of variation. Since the current is not concentrated locally, the potential rise is small. Therefore, the variation in output voltage is also reduced.
- FIG. 7 simulates the differential gain characteristic of the source follower amplifier of four pixels located farthest from the lower end in the pixel region 2a.
- the gain is less than 0.8, and the gain curve has almost no flat portion, resulting in a large gain error for each pixel.
- the gain remains almost flat and the gain value exceeds 0.8 when the input voltage is in the range of 1.0 to 3.5V. From these results, it can be confirmed that in the configuration of this embodiment, there is almost no gain error for each pixel and a high gain can be achieved.
- FIG. 8 is a schematic diagram illustrating a connection state between a pixel and a storage unit in the solid-state image sensor of the present embodiment.
- FIG. 9 is a circuit configuration diagram of one pixel in a pixel region in the solid-state image sensor of the present embodiment. These are schematic time charts of the operation from photoelectric conversion to signal transmission in one pixel 10. Since the circuit configuration of one storage unit 30 in the storage area is the same as that described with reference to FIG. 4 of the first embodiment, description thereof is omitted.
- each of the four pixels 10 arranged in the vertical direction and the same four storage units 30 are set as a set, and both are connected by one pixel output line 40 for each set.
- the number of pixel output lines 40 disposed between the pixel area 2a and the storage area 3a is reduced from 128 in the first embodiment to 32, that is, 1/4 of the number in the vertical direction. Become.
- the aperture ratio is improved, which is effective for improving sensitivity and SN ratio.
- the signal to the pixel output line 40 is selectively selected from the four pixels 10 sharing one pixel output line 40, that is, the signals are not output from the plurality of pixels 10 at the same time. It is necessary to adjust the output timing.
- the first current blocking transistor is connected in series with the first-stage buffer transistor 15.
- a transistor 16 is connected, and a second current cutoff transistor 23 is connected in series with the source follower amplification transistor 22.
- a drive line for supplying a drive pulse signal of ⁇ X1 is connected to the gate terminal of the first current cutoff transistor 16.
- a drive line for supplying the same drive pulse signal ⁇ X2 as that of the gate terminal of the output control transistor 25 is connected to the gate terminal of the second current cutoff transistor 23.
- the first current cut-off transistor 16 is turned on at the time t3, that is, almost at the same time as the sampling transistors 19 and 20 are turned on, and the output of the signal through the output control transistor 25 is started at the time t7, that is, the output control transistor 25. It is turned off immediately before. That is, the first current cut-off transistor 16 is turned on only during a period in which the voltage of the floating diffusion 14 needs to be applied to the first capacitor 18 or the second capacitor 21 at the subsequent stage, thereby operating the first-stage buffer transistor 15. Let In other words, during a period when the first stage buffer transistor 15 does not need to be operated, the first current cutoff transistor 16 is turned off and no bias current is supplied to the first stage buffer transistor 15. Power consumption is reduced.
- the second current cutoff transistor 23 is turned on / off simultaneously with the output control transistor 25. In other words, during the period when the voltage signal is not output to the pixel output line 40, the second current cutoff transistor 23 is turned off so that the bias current is not supplied to the source follower amplification transistor 22. This suppresses power consumption.
- the output control transistors 25 of the four pixels 10 Drive pulse signals ⁇ X2 ⁇ 0 ⁇ , ⁇ X2 ⁇ 1 ⁇ , ⁇ X2 ⁇ 2 ⁇ , and ⁇ X2 ⁇ 3 ⁇ are supplied to the gate terminals, respectively.
- a drive pulse signal of ⁇ X2 ⁇ 0 ⁇ is input to the gate terminal of the output control transistor 25 of the first pixel 10 among the four pixels 10 sharing one pixel output line 40, and this ⁇ X2 During a period when ⁇ 0 ⁇ is at a high level, the output control transistor 25 is turned on, and a pixel signal is output from the pixel 10 to the pixel output line 40.
- the writing transistor 31 of the corresponding storage unit 30 is turned on in synchronization with the signal transmission from each pixel 10, and the signal is sent to the capacitor 37 connected to the sampling transistor 36 that is turned on. Is retained.
- a burst / full pixel use mode in which all pixels are used to obtain a high resolution image (corresponding to the first drive mode in the present invention).
- the burst half pixel use mode (second in the present invention) is capable of acquiring an image at a higher speed than the burst full pixel use mode.
- Drive mode and the solid-state imaging device can be driven in two modes.
- FIG. 11 and FIG. 12A are timing charts of driving pulse signals of main parts in the burst / full pixel use mode.
- FIG. 12A is a continuation of FIG.
- the drive pulse signal ⁇ X1 is omitted.
- drive pulse signals ( ⁇ R, ⁇ T, ⁇ NS, ⁇ SS) for all the pixels 10 operate at the same timing for all the pixels, and perform a global shutter operation.
- the pixel signals from the four pixels 10 are sequentially connected to one pixel output line 40. This is as described above.
- One pixel output line 40 is connected to each of the four storage units 30 via a write transistor 31 that is turned on / off by a drive pulse signal ⁇ WS.
- the drive pulse signals ⁇ X2 ⁇ 1 ⁇ and ⁇ X2 ⁇ 3 ⁇ are always at a low level, and two of the four pixels are substantially equal. You can see that it was not used (ie it was skipped).
- the storage unit 30 side there are timings at which the drive pulse signals ⁇ VSR1 ⁇ 0 ⁇ to ⁇ VSR1 ⁇ 3 ⁇ each become high level, and the storage unit 30 corresponding to the pixel skipped as described above is also used. It can be seen that a signal is written to the memory cell in the memory unit 30. As a result, the number of frames that can be continuously shot without reading a signal to the outside is 256 frames, which is twice the normal number, so that twice the shooting time can be secured.
- the driving pulse signals ⁇ X2 ⁇ 0 ⁇ and ⁇ X2 ⁇ 1 ⁇ , ⁇ X2 ⁇ 2 ⁇ and ⁇ X2 ⁇ 3 ⁇ are wired in a staggered manner in the even-numbered columns and the odd-numbered columns, respectively.
- the thinning can be a checkered pattern as shown in FIG. Thereby, substantial deterioration of the resolution in the vertical direction and the horizontal direction can be suppressed.
- the pixel output line 40 directly connects the pixel 10 in the pixel region 2a and the storage unit 30 in the storage region 3a.
- the area of the element chip is increased in order to increase the number of pixels.
- the pixel output line 40 becomes longer, and the drive capability of the source follower amplification transistor 22 in the pixel 10 may be insufficient.
- a signal follower source follower amplifier 60 may be inserted in the middle of the pixel output line 40 (40a, 40b).
- the signal relay source follower amplifier 60 includes two transistors 61 and 62, but the configuration is not limited thereto.
- the signal relay source follower amplifiers 60 inserted into the pixel output lines 40 are not concentrated in one place, but are stored from the viewpoint of equalization of power distribution and load sharing between the source follower amplifiers in the pixels 10.
- a plurality of strip-like relay source follower amplifier regions 6 extending in the horizontal direction are provided on the region 3a, and the number of signal relay source follower amplifiers 60 included in each of the plurality of regions 6 is substantially the same.
- the relay source follower amplifiers 60 are distributed.
- one pixel output line 40 is not driven only by the source follower amplifier in the pixel 10, but is driven by sharing with the relay source follower amplifier arranged in the storage area 3 (3a, 3b). Since the load per amplifier is reduced, it can be driven at higher speed. Alternatively, it is possible to select to reduce the bias current without increasing the speed. In this case, the gain characteristic is further improved, and the current consumption of the pixel region is also reduced.
- the current consumption in the memory area where the source follower amplifier is arranged increases as the current consumption in the pixel area decreases, but this means that the total power is distributed over the entire element chip, and the ground potential is increased. It is preferable in that power concentration that causes an increase in power can be improved.
- the various numerical values used in the above description are merely examples, and do not limit the configuration / structure of the solid-state imaging device according to the present invention.
- the circuit configuration in one pixel as long as it has only basic components such as a photodiode, a detection node, a transfer gate, and a buffer circuit, other components such as the above-described CDS circuit are provided. Of course, it is not always necessary.
- SYMBOLS 1 Semiconductor substrate 2, 2a, 2b ... Pixel region 3, 3a, 3b ... Memory region 4a, 4b ... Vertical scanning circuit region 5a, 5b ... Horizontal scanning circuit region 6 ... Relay source follower amplifier region 10 ... Pixel 11 ... Photo Diode 12 ... Transfer transistor 13 ... Reset transistor 14 ... Floating diffusion (FD) DESCRIPTION OF SYMBOLS 15 ... 1st stage buffer transistor 16 ... 1st electric current cutoff transistor 17 ... 1st stage bias transistor 18 ... 1st capacitor
- Source follower amplification transistor 23 ... second current cutoff transistor 24 ... load current source transistor 25 ... output control transistor 30 ... storage unit 31 ... write transistor 32 ... in-storage unit signal line 33 ... read buffer transistor 34 ... Biasing transistor 36 ... Sampling transistor 37 ... Capacitor 40 ... Pixel output line 41 ... Vertical output line 42 ... Vertical transfer gate 43 ... Output line 44 ... Output buffer 60 ... Signal follower source follower amplifier
Abstract
Description
a)フォトダイオード、該フォトダイオードで生成された光電荷を電荷信号から電圧信号に変換するための検出ノード、前記フォトダイオードから前記検出ノードへの光電荷の転送を制御する転送ゲート、及び、前記検出ノードによる電圧信号を後記画素出力線に送出するバッファ回路、を含む画素が複数個配置された画素領域と、
b)前記画素領域とは分離された領域であって、各画素に一対一に対応し且つその内部に複数の記憶セルがそれぞれ設けられた、画素数と同数である記憶ユニットが配置された記憶領域と、
c)前記画素領域内の1個の画素と前記記憶領域内の1個の記憶ユニットとをそれぞれ独立に接続する画素数及び記憶ユニット数と同数である画素出力線と、
を備え、前記バッファ回路は前記画素出力線を駆動する少なくとも1個の電流駆動部を含み、該電流駆動部は当該画素の内部に配置された負荷となる電流源を含むことを特徴としている。
a)フォトダイオード、該フォトダイオードで生成された光電荷を電荷信号から電圧信号に変換するための検出ノード、前記フォトダイオードから前記検出ノードへの光電荷の転送を制御する転送ゲート、及び、前記検出ノードによる電圧信号を画素出力線に送出するバッファ回路、を含む画素が複数個配置された画素領域と、
b)前記画素領域とは分離された領域であって、各画素に一対一に対応し且つその内部に複数の記憶セルがそれぞれ設けられた記憶ユニットが配置された記憶領域と、
c)前記画素領域内のN個(Nは2以上の整数)の画素とそのN個の画素に対応付けられた前記記憶領域内のN個の記憶ユニットとをN個の画素及び記憶ユニット毎にそれぞれ独立に接続する画素数/N本の画素出力線と、を備え、
前記バッファ回路は、前記画素出力線を駆動する少なくとも1個の電流駆動部と、同一の画素出力線に接続されたN個の画素のうちの1個を選択的に該画素出力線に接続するための少なくとも1個の画素選択スイッチとを含み、前記電流駆動部は当該画素の内部に配置された負荷となる電流源を含み、同一の前記画素出力線に接続されるN個の画素の画素選択スイッチにはそれぞれ独立にN本の画素選択信号線が配線されてなることを特徴としている。
この構成によれば、上述のように1組のN個の画素の中の或る1個の画素から画素出力線に信号が送出されているとき、他のN-1個の画素の電流駆動部を切替スイッチによりオフすることができる。オフされた電流駆動部では負荷電流が流れなくなるので消費電流が減少し、素子全体で消費電力を削減するのに有効である。
前記N本の画素選択信号線を通した制御信号によって前記N個の画素選択スイッチを順番に選択して前記N個の画素を順次、共通の画素出力線に接続させる第1駆動モードと、
前記N本の画素選択信号線の一部のみを用いて前記N個の画素選択スイッチの一部のみを選択し、前記N個の画素の一部を共通の画素出力線に接続させる第2駆動モードと、
が選択可能であることを特徴としている。
以下、本発明の第1実施例である固体撮像素子及びその駆動方法について、添付図面を参照して説明する。
次に、本発明に係る第2実施例による固体撮像素子の構成及び動作を説明する。
上記第1実施例の固体撮像素子では、画素毎に独立した画素出力線で画素と記憶ユニットとを接続していたため、全画素一斉に信号転送が可能であるものの、半導体基板1上で画素出力線の占める領域の割合が多く、フォトダイオード11の面積を広く確保するのが難しい。これに対し、この第2実施例の固体撮像素子では、撮影速度を若干犠牲にしながら画素出力線の占める領域を減らし、それによってフォトダイオードの面積、つまりは開口率を上げるようにしたものである。
このモードでは、全ての画素10に対する駆動パルス信号(φR、φT、φNS、φSS)は全画素一斉に同一のタイミングで動作し、グローバルシャッタ動作をする。一方、出力制御用トランジスタ25をオン・オフする駆動パルス信号φX2は画素出力線40を共にする4個の画素10にそれぞれ対応してφX2{0}~φX2{3}の4つあり、それぞれ異なるタイミングで4個の画素10による画素信号を1本の画素出力線40へ順番に接続する。これは上述した通りである。
2、2a、2b…画素領域
3、3a、3b…記憶領域
4a、4b…垂直走査回路領域
5a、5b…水平走査回路領域
6…中継用ソースフォロア増幅器領域
10…画素
11…フォトダイオード
12…転送用トランジスタ
13…リセット用トランジスタ
14…フローティングディフュージョン(FD)
15…第1段バッファ用トランジスタ
16…第1電流遮断用トランジスタ
17…第1段バイアス用トランジスタ
18…第1コンデンサ
19…第1サンプリング用トランジスタ
20…第2サンプリング用トランジスタ
21…第2コンデンサ
22…ソースフォロア増幅用トランジスタ
23…第2電流遮断用トランジスタ
24…負荷電流源用トランジスタ
25…出力制御用トランジスタ
30…記憶ユニット
31…書き込み用トランジスタ
32…記憶ユニット内信号線
33…読み出しバッファ用トランジスタ
34…バイアス用トランジスタ
36…サンプリング用トランジスタ
37…コンデンサ
40…画素出力線
41…垂直出力線
42…垂直転送ゲート
43…出力線
44…出力バッファ
60…信号中継用ソースフォロア増幅器
Claims (8)
- a)フォトダイオード、該フォトダイオードで生成された光電荷を電荷信号から電圧信号に変換するための検出ノード、前記フォトダイオードから前記検出ノードへの光電荷の転送を制御する転送ゲート、及び、前記検出ノードによる電圧信号を後記画素出力線に送出するバッファ回路、を含む画素が複数個配置された画素領域と、
b)前記画素領域とは分離された領域であって、各画素に一対一に対応し且つその内部に複数の記憶セルがそれぞれ設けられた、画素数と同数である記憶ユニットが配置された記憶領域と、
c)前記画素領域内の1個の画素と前記記憶領域内の1個の記憶ユニットとをそれぞれ独立に接続する画素数及び記憶ユニット数と同数である画素出力線と、
を備え、前記バッファ回路は前記画素出力線を駆動する少なくとも1個の電流駆動部を含み、該電流駆動部は当該画素の内部に配置された負荷となる電流源を含むことを特徴とする固体撮像素子。 - a)フォトダイオード、該フォトダイオードで生成された光電荷を電荷信号から電圧信号に変換するための検出ノード、前記フォトダイオードから前記検出ノードへの光電荷の転送を制御する転送ゲート、及び、前記検出ノードによる電圧信号を画素出力線に送出するバッファ回路、を含む画素が複数個配置された画素領域と、
b)前記画素領域とは分離された領域であって、各画素に一対一に対応し且つその内部に複数の記憶セルがそれぞれ設けられた記憶ユニットが配置された記憶領域と、
c)前記画素領域内のN個(Nは2以上の整数)の画素とそのN個の画素に対応付けられた前記記憶領域内のN個の記憶ユニットとをN個の画素及び記憶ユニット毎にそれぞれ独立に接続する画素数/N本の画素出力線と、を備え、
前記バッファ回路は、前記画素出力線を駆動する少なくとも1個の電流駆動部と、同一の画素出力線に接続されたN個の画素のうちの1個を選択的に該画素出力線に接続するための少なくとも1個の画素選択スイッチとを含み、前記電流駆動部は当該画素の内部に配置された負荷となる電流源を含み、同一の前記画素出力線に接続されるN個の画素の画素選択スイッチにはそれぞれ独立にN本の画素選択信号線が配線されてなることを特徴とする固体撮像素子。 - 請求項2に記載の固体撮像素子であって、
前記バッファ回路は前記電流駆動部の動作をオン・オフする切替スイッチを含むことを特徴とする固体撮像素子。 - 請求項1に記載の固体撮像素子であって、
前記画素出力線のそれぞれの途中に中継増幅器が挿入され、該中継増幅器を配置するために、前記記憶領域内であって複数の前記画素出力線の延伸方向に沿って複数の中継増幅器領域が用意されることを特徴とする固体撮像素子。 - 請求項2又は3に記載の固体撮像素子であって、
前記画素出力線のそれぞれの途中に中継増幅器が挿入され、該中継増幅器を配置するために、前記記憶領域内であって複数の前記画素出力線の延伸方向に沿って複数の中継増幅器領域が用意されることを特徴とする固体撮像素子。 - 請求項2、3又は5のいずれかに記載の固体撮像素子の駆動方法であって、
前記N本の画素選択信号線を通した制御信号によって前記N個の画素選択スイッチを順番に選択して前記N個の画素を順次、共通の画素出力線に接続させる第1駆動モードと、
前記N本の画素選択信号線の一部のみを用いて前記N個の画素選択スイッチの一部のみを選択し、前記N個の画素の一部を共通の画素出力線に接続させる第2駆動モードと、
が選択可能であることを特徴とする固体撮像素子の駆動方法。 - 請求項6に記載の固体撮像素子の駆動方法であって、
同一の画素出力線に接続される前記N個の画素は垂直方向に隣接する偶数個の画素であり、第2駆動モードにおいては、前記N個の画素のうち垂直方向に1個おきの全部でN/2個の画素のみを使用し、且つ、画素領域内において、水平方向に隣接する画素でも使用される画素が1個おきとなるようにして、画素領域全体で市松模様の一色の部分の画素が選択されるように駆動することを特徴とする固体撮像素子の駆動方法。 - 請求項6又は7に記載の固体撮像素子の駆動方法であって、
第2駆動モードにおいて、選択された一部の画素に対して元々該画素に対応付けられていた記憶ユニットに加え、選択されなかった画素に対応する記憶ユニットをも割り当て、選択された一部の画素に対する記憶容量を拡大したことを特徴とする固体撮像素子の駆動方法。
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