DE602006021001D1 - Umkonfigurierbares anweisungs-zellen-array - Google Patents

Umkonfigurierbares anweisungs-zellen-array

Info

Publication number
DE602006021001D1
DE602006021001D1 DE602006021001T DE602006021001T DE602006021001D1 DE 602006021001 D1 DE602006021001 D1 DE 602006021001D1 DE 602006021001 T DE602006021001 T DE 602006021001T DE 602006021001 T DE602006021001 T DE 602006021001T DE 602006021001 D1 DE602006021001 D1 DE 602006021001D1
Authority
DE
Germany
Prior art keywords
instruction
cells
program instructions
processor
reconfigurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006021001T
Other languages
English (en)
Inventor
Tughrul Sati Arslan
Mark John Millward
Sami Khawam
Ioannis Nousias
Ying Yi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Edinburgh
Original Assignee
University of Edinburgh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0508589A external-priority patent/GB0508589D0/en
Priority claimed from GB0604428A external-priority patent/GB0604428D0/en
Application filed by University of Edinburgh filed Critical University of Edinburgh
Publication of DE602006021001D1 publication Critical patent/DE602006021001D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/04—Clock gating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Devices For Executing Special Programs (AREA)
  • Logic Circuits (AREA)
  • Executing Machine-Instructions (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE602006021001T 2005-04-28 2006-04-28 Umkonfigurierbares anweisungs-zellen-array Active DE602006021001D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0508589A GB0508589D0 (en) 2005-04-28 2005-04-28 Reconfigurable instruction cell array
GB0604428A GB0604428D0 (en) 2006-03-06 2006-03-06 Reconfigurable instruction cell array
PCT/GB2006/001556 WO2006114642A1 (en) 2005-04-28 2006-04-28 Reconfigurable instruction cell array

Publications (1)

Publication Number Publication Date
DE602006021001D1 true DE602006021001D1 (de) 2011-05-12

Family

ID=36685859

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006021001T Active DE602006021001D1 (de) 2005-04-28 2006-04-28 Umkonfigurierbares anweisungs-zellen-array

Country Status (6)

Country Link
US (1) US20100122105A1 (de)
EP (1) EP1877927B1 (de)
JP (1) JP6059413B2 (de)
AT (1) ATE504043T1 (de)
DE (1) DE602006021001D1 (de)
WO (1) WO2006114642A1 (de)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7330050B2 (en) 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7679401B1 (en) 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US8365111B2 (en) * 2008-02-29 2013-01-29 Et International, Inc. Data driven logic simulation
KR101553655B1 (ko) * 2009-01-19 2015-09-17 삼성전자 주식회사 재구성가능 프로세서에 대한 명령어 스케줄링 장치 및 방법
CN101782893B (zh) * 2009-01-21 2014-12-24 上海芯豪微电子有限公司 可重构数据处理平台
US8856791B2 (en) * 2009-01-23 2014-10-07 Imec Method and system for operating in hard real time
KR101515568B1 (ko) * 2009-02-03 2015-04-28 삼성전자 주식회사 재구성 가능 어레이의 스케줄러, 스케줄링 방법 및 이를 이용한 컴퓨팅 장치
KR101553652B1 (ko) * 2009-02-18 2015-09-16 삼성전자 주식회사 이종 프로세서에 대한 명령어 컴파일링 장치 및 방법
GB2471067B (en) 2009-06-12 2011-11-30 Graeme Roy Smith Shared resource multi-thread array processor
US8990783B1 (en) 2009-08-13 2015-03-24 The Mathworks, Inc. Scheduling generated code based on target characteristics
US8566804B1 (en) * 2009-08-13 2013-10-22 The Mathworks, Inc. Scheduling generated code based on target characteristics
US8281274B1 (en) 2010-01-08 2012-10-02 Altera Corporation Method and apparatus for performing efficient incremental compilation
EP2553815A1 (de) * 2010-04-02 2013-02-06 Tabula, Inc. System und verfahren zur reduzierung der nutzung von neukonfigurationsenergie
WO2011125174A1 (ja) * 2010-04-06 2011-10-13 トヨタ自動車株式会社 動的再構成プロセッサ及びその動作方法
US8760193B2 (en) 2011-07-01 2014-06-24 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
US10983947B2 (en) * 2011-11-21 2021-04-20 Robert Keith Mykland Method and dynamically reconfigurable processor adapted for management of persistence of information across multiple instruction cycles
US9058860B2 (en) * 2012-03-29 2015-06-16 Memoir Systems, Inc. Methods and apparatus for synthesizing multi-port memory circuits
KR20130125036A (ko) * 2012-05-08 2013-11-18 삼성전자주식회사 시스템 온 칩, 이의 동작 방법, 및 이를 포함하는 시스템
US9280395B2 (en) * 2012-05-30 2016-03-08 Intel Corporation Runtime dispatching among a heterogeneous group of processors
US9210486B2 (en) * 2013-03-01 2015-12-08 Qualcomm Incorporated Switching fabric for embedded reconfigurable computing
US8860457B2 (en) * 2013-03-05 2014-10-14 Qualcomm Incorporated Parallel configuration of a reconfigurable instruction cell array
KR101962250B1 (ko) * 2013-03-05 2019-03-26 삼성전자주식회사 재구성가능 아키텍처를 위한 스케줄러 및 스케줄링 방법
GB2514392B (en) 2013-05-22 2015-06-17 Khodor Ahmad Fawaz Methods for operating and configuring a reconfigurable processor
US9465758B2 (en) 2013-05-29 2016-10-11 Qualcomm Incorporated Reconfigurable instruction cell array with conditional channel routing and in-place functionality
US9330040B2 (en) 2013-09-12 2016-05-03 Qualcomm Incorporated Serial configuration of a reconfigurable instruction cell array
GB2526018B (en) * 2013-10-31 2018-11-14 Silicon Tailor Ltd Multistage switch
US20150268963A1 (en) * 2014-03-23 2015-09-24 Technion Research & Development Foundation Ltd. Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware
US9503093B2 (en) * 2014-04-24 2016-11-22 Xilinx, Inc. Virtualization of programmable integrated circuits
US20160004617A1 (en) * 2014-07-03 2016-01-07 Qualcomm Incorporated Automatic test pattern generation for a reconfigurable instruction cell array
GB2529170B (en) 2014-08-11 2021-06-16 Ahmad Fawaz Khodor Circuit design generator
US9749548B2 (en) 2015-01-22 2017-08-29 Google Inc. Virtual linebuffers for image signal processors
US9965824B2 (en) 2015-04-23 2018-05-08 Google Llc Architecture for high performance, power efficient, programmable image processing
US10095479B2 (en) 2015-04-23 2018-10-09 Google Llc Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
US10291813B2 (en) 2015-04-23 2019-05-14 Google Llc Sheet generator for image processor
US9756268B2 (en) 2015-04-23 2017-09-05 Google Inc. Line buffer unit for image processor
US9772852B2 (en) 2015-04-23 2017-09-26 Google Inc. Energy efficient processor core architecture for image processor
US9769356B2 (en) 2015-04-23 2017-09-19 Google Inc. Two dimensional shift array for image processor
US9785423B2 (en) 2015-04-23 2017-10-10 Google Inc. Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
NL2015114B1 (en) * 2015-07-07 2017-02-01 Univ Delft Tech Scalable computation architecture in a memristor-based array.
US20170083313A1 (en) * 2015-09-22 2017-03-23 Qualcomm Incorporated CONFIGURING COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRAs) FOR DATAFLOW INSTRUCTION BLOCK EXECUTION IN BLOCK-BASED DATAFLOW INSTRUCTION SET ARCHITECTURES (ISAs)
US9804849B2 (en) 2015-10-20 2017-10-31 International Business Machines Corporation Space reduction in processor stressmark generation
US9830150B2 (en) 2015-12-04 2017-11-28 Google Llc Multi-functional execution lane for image processor
US10313641B2 (en) 2015-12-04 2019-06-04 Google Llc Shift register with reduced wiring complexity
US20170177542A1 (en) * 2015-12-16 2017-06-22 Cognitive Systems Corp. Operating a VLIW Processor in a Wireless Sensor Device
US10387988B2 (en) 2016-02-26 2019-08-20 Google Llc Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
US10204396B2 (en) 2016-02-26 2019-02-12 Google Llc Compiler managed memory for image processor
US10380969B2 (en) 2016-02-28 2019-08-13 Google Llc Macro I/O unit for image processor
US20180005059A1 (en) 2016-07-01 2018-01-04 Google Inc. Statistics Operations On Two Dimensional Image Processor
US20180005346A1 (en) 2016-07-01 2018-01-04 Google Inc. Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
US20180007302A1 (en) 2016-07-01 2018-01-04 Google Inc. Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register
US10546211B2 (en) 2016-07-01 2020-01-28 Google Llc Convolutional neural network on programmable two dimensional image processor
US10437946B1 (en) * 2016-09-01 2019-10-08 Xilinx, Inc. Using implemented core sources for simulation
KR20200031625A (ko) 2017-06-22 2020-03-24 아이씨에이티 엘엘씨 고성능 프로세서
CN109725904B (zh) * 2017-10-31 2021-10-22 中国科学院微电子研究所 一种低功耗程序指令编译方法及系统
US11003429B1 (en) * 2019-02-04 2021-05-11 Amazon Technologies, Inc. Compile-time scheduling
US10853541B1 (en) * 2019-04-30 2020-12-01 Xilinx, Inc. Data processing engine (DPE) array global mapping
US10839121B1 (en) * 2019-04-30 2020-11-17 Xilinx, Inc. Data processing engine (DPE) array detailed mapping
EP4004724A1 (de) * 2019-08-22 2022-06-01 Google LLC Kompilierung für einen synchronen prozessor
US11900156B2 (en) 2019-09-24 2024-02-13 Speedata Ltd. Inter-thread communication in multi-threaded reconfigurable coarse-grain arrays
CN112905525B (zh) * 2019-11-19 2024-04-05 中科寒武纪科技股份有限公司 控制运算装置进行计算的方法及设备
US11354157B2 (en) 2020-04-28 2022-06-07 Speedata Ltd. Handling multiple graphs, contexts and programs in a coarse-grain reconfigurable array processor
US11175922B1 (en) 2020-04-28 2021-11-16 Speedata Ltd. Coarse-grain reconfigurable array processor with concurrent handling of multiple graphs on a single grid
EP4315045A1 (de) * 2021-03-26 2024-02-07 Ascenium, Inc. Parallelverarbeitungsarchitektur mit spekulativer kodierung
US20230251993A1 (en) * 2022-02-10 2023-08-10 SambaNova Systems, Inc. Two-Level Arbitration in a Reconfigurable Processor
US11815935B2 (en) 2022-03-25 2023-11-14 Micron Technology, Inc. Programming a coarse grained reconfigurable array through description of data flow graphs
US20230305848A1 (en) * 2022-03-25 2023-09-28 Micron Technology, Inc. Schedule Instructions of a Program of Data Flows for Execution in Tiles of a Coarse Grained Reconfigurable Array
CN117348930A (zh) * 2022-06-29 2024-01-05 中科寒武纪科技股份有限公司 指令处理装置、指令执行方法、片上系统和板卡

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60215248A (ja) * 1984-03-12 1985-10-28 Nippon Telegr & Teleph Corp <Ntt> 情報処理方式
US5933642A (en) * 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US5646545A (en) * 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US7444531B2 (en) * 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7155708B2 (en) * 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation

Also Published As

Publication number Publication date
ATE504043T1 (de) 2011-04-15
JP6059413B2 (ja) 2017-01-11
EP1877927A1 (de) 2008-01-16
WO2006114642A1 (en) 2006-11-02
EP1877927B1 (de) 2011-03-30
JP2008539485A (ja) 2008-11-13
US20100122105A1 (en) 2010-05-13

Similar Documents

Publication Publication Date Title
ATE504043T1 (de) Umkonfigurierbares anweisungs-zellen-array
Gobieski et al. Snafu: an ultra-low-power, energy-minimal cgra-generation framework and architecture
TW200632742A (en) Method and apparatus for varying energy per instruction according to the amount of available parallelism
Singh et al. Evolution of processor architecture in mobile phones
WO2007089499A3 (en) Power consumption management
WO2009037731A1 (ja) 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
TW200640138A (en) Pipelined datapath with dynamically reconfigurable pipeline stages
US20140137123A1 (en) Microcomputer for low power efficient baseband processing
Rossi et al. Energy efficient parallel computing on the PULP platform with support for OpenMP
Schoeberl Leros: A tiny microcontroller for FPGAs
Garofalo et al. Darkside: A heterogeneous risc-v compute cluster for extreme-edge on-chip dnn inference and training
Hinkelmann et al. A domain-specific dynamically reconfigurable hardware platform for wireless sensor networks
US7263621B2 (en) System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback
Liu A hardware and software cooperative design of SoC IP
Pham-Quoc et al. Hybrid interconnect design for heterogeneous hardware accelerators
Pasha et al. System level synthesis for ultra low-power wireless sensor nodes
Sato et al. Importance of single-core performance in the multicore era
CN110045989B (zh) 一种动态切换式低功耗处理器
Matus et al. A GFLOPS vector-DSP for broadband wireless applications
Marcinek et al. AGATE-towards designing a low-power chip multithreading processor for mobile software defined radio systems
Flores et al. Sim-PowerCMP: a detailed simulator for energy consumption analysis in future embedded CMP architectures
KR20130091113A (ko) 재구성 기반 컴퓨팅 장치의 제1메모리 제어기 및 제2메모리 제어기와, 디버깅용 트레이스 데이터 처리가 가능한 재구성 기반 컴퓨팅 장치
Pullini Design of energy efficient microcontrollers
Rossi Sub-pJ per operation scalable computing: The PULP experience
Yue-Li et al. Design of a high performance microcontroller