WO2009037731A1 - 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ - Google Patents

翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ Download PDF

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Publication number
WO2009037731A1
WO2009037731A1 PCT/JP2007/001028 JP2007001028W WO2009037731A1 WO 2009037731 A1 WO2009037731 A1 WO 2009037731A1 JP 2007001028 W JP2007001028 W JP 2007001028W WO 2009037731 A1 WO2009037731 A1 WO 2009037731A1
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WO
WIPO (PCT)
Prior art keywords
translating
parallel
processor
code
control
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Application number
PCT/JP2007/001028
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English (en)
French (fr)
Inventor
Koichiro Yamashita
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Fujitsu Limited
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07805864A priority Critical patent/EP2202638A4/en
Priority to PCT/JP2007/001028 priority patent/WO2009037731A1/ja
Priority to JP2009532967A priority patent/JP5067425B2/ja
Publication of WO2009037731A1 publication Critical patent/WO2009037731A1/ja
Priority to US12/726,526 priority patent/US8543993B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/451—Code distribution
    • G06F8/452—Loops
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4432—Reducing the energy consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)

Abstract

　複数のプロセッサから構成されるシステムやマルチコアプロセッサチップにより並列処理を行う場合に、並列処理を行うプロセッサ数および各プロセッサの動作クロックを動的に変更することにより消費電力を低減可能とする技術を提供する。ソースコードから、予め設定された繰り返し回数だけ内部処理を実行するループ処理コードであり、繰り返しごとに実行される前記内部処理に互いに依存関係がない、並列処理可能な並列ループ処理コードを検出する並列ループ処理検出部と、並列ループ処理コードにおける前記繰り返し回数を制御するための制御コア用コードと、該制御コア用コード側からの制御に対応して繰り返し回数を変更するための並列処理用コードとを生成する動的並列変換部と、を具備する翻訳装置である。また、翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサである。
PCT/JP2007/001028 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ WO2009037731A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP07805864A EP2202638A4 (en) 2007-09-21 2007-09-21 TRANSLATION FACILITY, TRANSLATION PROCEDURE AND TRANSLATION PROGRAM AND PROCESSOR CONTROL SYSTEM AND PROCESSOR
PCT/JP2007/001028 WO2009037731A1 (ja) 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
JP2009532967A JP5067425B2 (ja) 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
US12/726,526 US8543993B2 (en) 2007-09-21 2010-03-18 Compiler, compile method, and processor core control method and processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001028 WO2009037731A1 (ja) 2007-09-21 2007-09-21 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ

Related Child Applications (1)

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US12/726,526 Continuation US8543993B2 (en) 2007-09-21 2010-03-18 Compiler, compile method, and processor core control method and processor

Publications (1)

Publication Number Publication Date
WO2009037731A1 true WO2009037731A1 (ja) 2009-03-26

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Country Status (4)

Country Link
US (1) US8543993B2 (ja)
EP (1) EP2202638A4 (ja)
JP (1) JP5067425B2 (ja)
WO (1) WO2009037731A1 (ja)

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JP2013500515A (ja) * 2009-07-21 2013-01-07 マイクロソフト コーポレーション コンポーネントの電力監視およびワークロードの最適化
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JP2017102790A (ja) * 2015-12-03 2017-06-08 富士通株式会社 情報処理装置、演算処理装置および情報処理装置の制御方法

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JP2017102790A (ja) * 2015-12-03 2017-06-08 富士通株式会社 情報処理装置、演算処理装置および情報処理装置の制御方法

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Publication number Publication date
US8543993B2 (en) 2013-09-24
US20100235611A1 (en) 2010-09-16
JP5067425B2 (ja) 2012-11-07
JPWO2009037731A1 (ja) 2010-12-24
EP2202638A4 (en) 2011-12-14
EP2202638A1 (en) 2010-06-30

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