TW200640138A - Pipelined datapath with dynamically reconfigurable pipeline stages - Google Patents

Pipelined datapath with dynamically reconfigurable pipeline stages

Info

Publication number
TW200640138A
TW200640138A TW094115696A TW94115696A TW200640138A TW 200640138 A TW200640138 A TW 200640138A TW 094115696 A TW094115696 A TW 094115696A TW 94115696 A TW94115696 A TW 94115696A TW 200640138 A TW200640138 A TW 200640138A
Authority
TW
Taiwan
Prior art keywords
pipeline
pipeline stages
register
datum
pipelined datapath
Prior art date
Application number
TW094115696A
Other languages
Chinese (zh)
Other versions
TWI259659B (en
Inventor
Tay-Jyi Lin
Chein-Wei Jen
Chih-Wei Liu
Po-Han Huang
Wei-Sheng Huang
Chan Hao Chang
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW094115696A priority Critical patent/TWI259659B/en
Priority to US11/229,616 priority patent/US7406588B2/en
Application granted granted Critical
Publication of TWI259659B publication Critical patent/TWI259659B/en
Publication of TW200640138A publication Critical patent/TW200640138A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.
TW094115696A 2005-05-13 2005-05-13 Pipelined datapath with dynamically reconfigurable pipeline stages TWI259659B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094115696A TWI259659B (en) 2005-05-13 2005-05-13 Pipelined datapath with dynamically reconfigurable pipeline stages
US11/229,616 US7406588B2 (en) 2005-05-13 2005-09-20 Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094115696A TWI259659B (en) 2005-05-13 2005-05-13 Pipelined datapath with dynamically reconfigurable pipeline stages

Publications (2)

Publication Number Publication Date
TWI259659B TWI259659B (en) 2006-08-01
TW200640138A true TW200640138A (en) 2006-11-16

Family

ID=37420568

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094115696A TWI259659B (en) 2005-05-13 2005-05-13 Pipelined datapath with dynamically reconfigurable pipeline stages

Country Status (2)

Country Link
US (1) US7406588B2 (en)
TW (1) TWI259659B (en)

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WO2005088442A2 (en) * 2004-03-10 2005-09-22 Koninklijke Philips Electronics N.V. Pipeline circuit
US7317348B2 (en) * 2006-01-27 2008-01-08 International Business Machines Corporation Noise reduction in digital systems
US8099583B2 (en) * 2006-08-23 2012-01-17 Axis Semiconductor, Inc. Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US7797561B1 (en) * 2006-12-21 2010-09-14 Nvidia Corporation Automatic functional block level clock-gating
US7802118B1 (en) 2006-12-21 2010-09-21 Nvidia Corporation Functional block level clock-gating within a graphics processor
US7958483B1 (en) 2006-12-21 2011-06-07 Nvidia Corporation Clock throttling based on activity-level signals
KR100887238B1 (en) * 2007-08-10 2009-03-06 삼성전자주식회사 Apparatus and method for adaptive time borrowing technique in pipeline system
JP2009075973A (en) * 2007-09-21 2009-04-09 Canon Inc Electronic apparatus and power control method therefor
US8037337B2 (en) * 2007-11-28 2011-10-11 International Business Machines Corporation Structures including circuits for noise reduction in digital systems
US7917793B2 (en) * 2008-02-11 2011-03-29 National Chung Cheng University Apparatus providing locally adaptive retiming pipeline with swing structure
US8145874B2 (en) * 2008-02-26 2012-03-27 Qualcomm Incorporated System and method of data forwarding within an execution unit
US8078833B2 (en) * 2008-05-29 2011-12-13 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
US9143139B1 (en) * 2013-11-11 2015-09-22 Liming Xiu Microelectronic system using time-average-frequency clock signal as its timekeeper
CN108334338B (en) * 2017-12-25 2022-04-12 新岸线(北京)科技集团有限公司 Real-time back pressure method supporting assembly line
CN109936441B (en) * 2019-01-28 2022-07-05 湖北大学 Pipelined SHA256 hardware implementation method based on data storage
US10565036B1 (en) 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication
CN110045989B (en) * 2019-03-14 2023-11-14 合肥雷芯智能科技有限公司 Dynamic switching type low-power-consumption processor
TWI768543B (en) * 2020-11-13 2022-06-21 新唐科技股份有限公司 Integrated circuit and in-system programming circuit thereof

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* Cited by examiner, † Cited by third party
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US5168499A (en) * 1990-05-02 1992-12-01 California Institute Of Technology Fault detection and bypass in a sequence information signal processor
WO1995009390A1 (en) * 1993-09-28 1995-04-06 Namco Ltd. Pipeline processor, clipping processor, three-dimensional simulator and pipeline processing method
JPH08147163A (en) * 1994-11-24 1996-06-07 Toshiba Corp Method and device for operation processing
US6247134B1 (en) 1999-03-31 2001-06-12 Synopsys, Inc. Method and system for pipe stage gating within an operating pipelined circuit for power savings
US7653807B2 (en) * 2005-09-19 2010-01-26 Synopsys, Inc. Removing a pipeline bubble by blocking clock signal to downstream stage when downstream stage contains invalid data

Also Published As

Publication number Publication date
US7406588B2 (en) 2008-07-29
TWI259659B (en) 2006-08-01
US20060259748A1 (en) 2006-11-16

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