CN108334338B - Real-time back pressure method supporting assembly line - Google Patents
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Abstract
The application discloses a real-time back pressure method supporting a production line, which adopts the technical scheme that: adding a corresponding number of registers on a preset stage of the N-stage production line to form a register group with a ping-pong structure; and the collected data are sequentially stored in a register group of the ping-pong structure. The technical scheme of the invention aims at the N-level pipeline real-time back pressure situation, adds the corresponding register, ensures the continuity of pipeline starting, adapts the buffer capacity of the ping-pong register group to the length of the pipeline, and realizes uninterrupted pipeline processing.
Description
Technical Field
The invention relates to the field of chip design, in particular to a real-time back pressure method supporting a production line.
Background
The computer Pipeline (Pipeline) technology is a key technology widely used in chip design (ASIC or FPGA), and refers to an aspect of execution modes of instructions inside a CPU. The technology can improve the hardware processing speed (or improve the system clock frequency) on the basis of sacrificing partial power consumption and area, and meanwhile, the timing sequence convergence is easier. And the ultra-high performance ASIC or FPGA chip development is met.
In the signal transmission process, when a receiving party successfully receives data sent by a sending party, an ACK is returned to the sending party, and because the sending real-time change of a feedback ACK signal under each clock does not have certain buffering capacity, the receiving party can generate real-time back pressure, and the condition that a production line is interrupted continuously can be caused when the real-time back pressure situation is met in the prior art.
Disclosure of Invention
In order to overcome the defect that the assembly line is continuously interrupted due to real-time back pressure in the prior art, the application provides a real-time back pressure method supporting the assembly line.
The technical scheme adopted by the invention is as follows: a real-time backpressure method to support a pipeline, comprising: adding a corresponding number of registers on a preset stage of the N-stage production line to form a register group with a ping-pong structure;
and the collected data are sequentially stored in a register group of the ping-pong structure.
Aiming at the real-time back pressure situation of an N-stage production line of an RAM reading channel, adding (N-1) registers on the second stage of the N-stage production line, and forming N ping-pong register groups with the original registers of the second-stage production line.
Enabling the RAM read enabling signal to be effective, starting the assembly line, enabling the next beat of clock of the RAM read enabling signal to be effective, and starting the first-stage assembly line; then, the next beat of clock is valid, a second-stage production line is started, and data are collected and stored to a first register in the register groups of the N ping-pong structures; and then sequentially starting the rest (N-2) stages of pipelines along with the effective increment of the RAM read enabling clock, and sequentially storing the collected data into (N-1) registers of the ping-pong structure.
The RAM read enable signal is valid for one of the following conditions: (1) read RAM data FF1 register pre-full invalid; (2) read RAM data FF1 register is active full and the feedback ACK signal is active at the same time.
Aiming at the general N-stage pipeline real-time back pressure situation except the RAM read path, a (N-1) register is added on the first stage of the N-stage pipeline, and the register and the original register of the first stage pipeline form N ping-pong register groups.
Enabling an RAM read enabling signal to be effective, starting a production line, enabling a next-beat clock of the RAM read enabling signal to be effective, starting a first-stage production line, and collecting data and storing the data to a first register in N ping-pong register groups; then, the next beat of clock is valid, a second-stage production line is started, and the collected data is stored in a second register; and then sequentially starting the (N-2) stage pipelines along with the effective increment of the RAM read enabling clock, and sequentially storing the collected data into (N-2) registers of the ping-pong structure.
Registers with preset quantity are arranged on each stage of the N stages of pipelines, and each stage of pipeline and the register of the pipeline form a register group with the preset quantity plus 1 ping-pong structure.
The preset number is an integer of 1 or more and (N-1) or less.
On a preset level pipeline, data is controlled to determine whether to perform handshake transaction through an ACK signal, if the ACK signal is effective, the data handshake transaction is successful, and if the ACK signal is ineffective, the data handshake transaction is failed, and the next clock rising edge is waited until the ACK is effective.
If the ACK signal is not active on the pre-set level pipeline, the condition that RAM read enable is active includes data inside the RAM and read RAM data FF1 register is not active.
The read RAM data FF1 register pre-full state is read RAM enabled valid and handshake transaction valid.
If the ACK signal is not effective at a certain moment, the read RAM data FF1 register pre-full state is effective, the pipeline is interrupted, and the read RAM enable is started in advance at the current moment when the ACK signal is effective by adopting a pre-starting strategy.
Preferably, N > is 2.
The beneficial effects obtained by the invention are as follows: aiming at the N-stage pipeline real-time back pressure scene, the N-stage pipeline is adopted, the corresponding registers are added, the continuity of starting the read enable flow is ensured, the cache capacity of the ping-pong register group is equal to the length of the pipeline, the seamless butt joint of reading and writing of the ping-pong register is met, and the flow treatment is not interrupted.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a diagram of a pipeline real-time backpressure scenario depiction;
FIG. 2 is an N-stage pipeline timing diagram;
FIG. 3 is a diagram of an on-chip RAM read path two-stage pipeline architecture without real-time backpressure requirements;
FIG. 4 is a timing diagram of a two-stage pipeline to support real-time backpressure requirements;
FIG. 5 is a pipeline pre-start timing diagram.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 illustrates an existing pipeline real-time backpressure scenario, which includes a sending party (module 1) and a receiving party (module 2), where the module 1 reads an output RAM and sends data in the RAM to hardware logic of the module 2; the module 2 is provided with a back pressure signal for judging whether to receive the data sent by the module 1. Because the hardware logic received in the module 2 does not have a cache function (for example, bus write operation is performed after data is received) or only has a single-port RAM (only one set of address bus and data bus, and therefore read and write operations cannot be performed simultaneously), if the read priority of the module 2 is higher than the write priority of the module 1, a feedback effective or ineffective real-time back pressure exists in each clock cycle, and continuous start enabling of the pipeline cannot be ensured through the cache residual space of the module 2.
Example one
Based on the above-described existing defects, in an embodiment of the present invention, a hardware design scheme is provided for supporting real-time backpressure in units of pipeline units, where registers of a corresponding number are added to preset stages of an N-stage pipeline to form a ping-pong register group; preferably, N > is 2.
For the real-time back pressure scene of the RAM reading channel and the general real-time back pressure scene except the RAM reading channel, because the RAM reading has self limiting conditions (only one period can be kept stable after the read data is effective, and even if the read data is not read, the next period can not be ensured to also keep the data), different hardware design schemes are adopted for the two real-time back pressure scenes;
(1) RAM read path N-stage pipeline real-time back pressure scenario
On the second stage of the N-stage production line, (N-1) registers are added to form N ping-pong register groups together with the original registers of the second-stage production line;
FIG. 2 is a schematic diagram showing an N-stage pipeline structure of a RAM read path, wherein a RAM read enable signal is asserted to enable the pipeline, and a next beat of a clock of the RAM read enable signal is asserted to enable the first stage pipeline; then, the next beat of clock is valid, a second-stage production line is started, and data are collected and stored to a first register in the register groups of the N ping-pong structures; then, with the effective increment of the RAM read enabling clock, sequentially starting the rest (N-2) stages of pipelines, and sequentially storing the collected data in (N-1) registers of the ping-pong structure;
the RAM read enable signal is valid for one of the following conditions: (1) read RAM data FF1 register pre-full invalid; (2) read RAM data FF1 register is active full and the feedback ACK signal is active at the same time.
(2) General purpose N-stage pipeline real-time backpressure scenarios other than RAM read path
On the first stage of the N-stage production line, (N-1) registers are added to form N ping-pong register groups together with the original registers of the first-stage production line;
enabling an RAM read enabling signal to be effective, starting a production line, enabling a next-beat clock of the RAM read enabling signal to be effective, starting a first-stage production line, and collecting data and storing the data to a first register in N ping-pong register groups; then, the next beat of clock is valid, a second-stage production line is started, and the collected data is stored in a second register; then sequentially starting an (N-2) stage pipeline along with the effective increment of the RAM read enabling clock, and sequentially storing the collected data into (N-2) registers of the ping-pong structure;
further, the present application also provides a hardware design scheme applicable to both the RAM read channel real-time backpressure scenario and the general real-time backpressure scenario except for the RAM read channel, specifically including:
the method comprises the steps that registers with preset number are arranged on each stage of pipeline of an N-stage pipeline, the registers of each stage of pipeline and the registers of the pipeline form register groups with the preset number plus 1 ping-pong structure, the preset number is preferably 1, and the preset number can be an integer which is greater than 1 and less than or equal to (N-1);
after a first-stage pipeline is started, collecting data are stored in a first register of the first-stage pipeline, then after a second-stage pipeline is started, the collecting data are stored in a second register of the first-stage pipeline, after a third-stage pipeline is started, data in the first register of the first-stage pipeline are sequentially sent to the first register of the second-stage pipeline, the collecting data are updated in the first register of the first-stage pipeline, and so on until N stages of pipelines are all started, and the data are stored in the registers of each stage of pipeline;
for example, in the four-stage pipeline structure, a register is additionally added to each of the first-stage, second-stage, third-stage and fourth-stage pipelines, and the register of each stage and the added register form a ping-pong structure.
On a preset-level pipeline, data is controlled to determine whether to perform handshake transaction through an ACK signal, if the ACK signal is effective, the data handshake transaction is successful, and if the ACK signal is ineffective, the data handshake transaction is failed, and the next clock rising edge is waited until the ACK is effective;
if the ACK signal is not valid on the predetermined pipeline, the condition that the RAM read enable is valid includes that data is in the RAM and the register FF1 is not valid, and the register full state FF1 is read RAM enable valid and the handshake transaction is valid.
By adopting the general N-level pipeline mode of the first embodiment, N register groups are correspondingly added to form a ping-pong structure, so that certain caching capacity is achieved in the data reading process, the caching capacity is just matched with the length of the pipeline, and normal pipeline operation of the pipeline is guaranteed without interruption.
Example two
In this embodiment, N is 2, that is, a two-stage pipeline is taken as an example to illustrate, it should be noted that, in the case that the amount of the existing collected data is not very large, the two-stage pipeline is set, so that normal running of the pipeline can be realized without interruption, and the design is simple and the operation is convenient.
The embodiment is suitable for the situation that the secondary pipeline has no real-time backpressure requirement, and fig. 3 shows a schematic diagram of the structure of the secondary pipeline of the on-chip RAM read channel under the condition of no real-time backpressure requirement;
enabling a RAM read enable signal to be effective, and starting a production line; enabling a next beat of clock of the RAM read enabling signal to be effective, and starting a first stage of the assembly line; and the RAM reads the enabling signal and then the next beat of clock is effective, and the second stage of the assembly line is started. The RAM read enable signal valid is required to satisfy both RAM null invalidate and read RAM data FF1 register invalidate, i.e. no valid data inside.
And in the second stage of the pipeline, the data determines whether to perform handshake transaction through ACK signal control, if the ACK signal is effective, the data handshake transaction is successful, and if the ACK signal is ineffective, the data handshake transaction fails, and the next clock rising edge is waited until the ACK is effective.
It should be noted that, since the first stage of the pipeline, i.e., the read RAM data is valid, the data can only be held valid for one clock cycle, and the next cycle is indefinite, the condition for determining that the RAM read enable signal is valid in the second embodiment is the read RAM data FF1 register pre-full state.
For example, assuming the ACK signal is inactive at the second stage of the pipeline, the condition that RAM read enable is active includes data inside the RAM and read RAM data FF1 register is pre-full inactive, i.e., no valid data inside; where the read RAM data FF1 register pre-full state is read RAM enabled valid and the handshake transaction valid.
It should be noted that, if whether to read the RAM is determined according to the true empty and full state of the read RAM data FF1 register, it is determined across one-stage pipeline, two times of consecutive read RAM enable are valid, two data are read, and if ACK is invalid, the first valid data is overwritten by the second read data, so that an error occurs, and therefore, a "pre-full" policy is adopted.
EXAMPLE III
The third embodiment of the invention is improved on the basis of the second embodiment, because the second embodiment is only suitable for the situation without real-time back pressure, if the ACK signal is fed back and then real-time change is sent in each clock, namely real-time back pressure, the situation of pipeline interruption can occur; therefore, on the second-level pipeline, a register FF1_1 is added to form a ping-pong register structure together with FF1, and the condition of judging the validity of the RAM read enable signal is improved to judge the pre-full state of the ping-pong register.
In this embodiment, the RAM read enable effectively satisfies one of the following conditions:
(1) read RAM data FF1 register pre-full state invalid;
(2) the read RAM data FF1 register pre-full state is valid and the ACK signal is valid.
As shown in fig. 4, after the pipeline is started, the RAM read enable signal is always in an active state, data is continuously collected and transmitted along with the rising edge of the clock, and two registers of the ping-pong structure are in the second stage on the pipeline and are continuously read and written in sequence.
And the second stage of the pipeline is started, data 0 is stored into the first register FF1, data 1 is sequentially stored into the second register FF1_1, and then when data 2 is read, the data in the first register FF1 is updated into data 2, at the moment, the original data 0 is also read, so that the continuity of read enabling is ensured, and the seamless docking ping-pong register read-write is met.
Furthermore, if the ACK signal is fed back at a certain moment and is invalid, namely when the back pressure is valid, the RAM reading data FF1 register pre-full state is valid, namely the ping-pong register is pre-full, the pipeline is interrupted, a pre-starting strategy is adopted, the RAM reading enabling is started in advance at the current moment when the ACK signal is valid, the RAM reading enabling is started one period in advance, and the transmission efficiency is improved.
The essence of the pre-boot strategy is the simultaneous read and write process of the ping-pong register, no overflow occurs, and the register pre-full state (RAM _ rdat _ FF1_ pre _ full) of the RAM data FF1 is still read all the time effectively. The specific analysis is as follows, after the read enable is effective simultaneously with the ACK, the data of the ping-pong register is kept stable for one period for the next beat, data acquisition is carried out, and the data of the ping-pong register is just written and updated for the next beat, so that the data in the ping-pong register is also read out at the moment, and the requirement of seamless docking ping-pong register reading and writing is met.
The pipeline pre-start timing diagram is shown in fig. 5, the ACK signal is only valid on the rising edge of the clock 7, the ACK signal is always back-pressed before the rising edge, the pipeline automatically stops after reading twice continuously, and the ping-pong register reaches the pre-full state and the true full state. After the clock 7 and the ACK are valid, the read RAM is enabled to be valid, the ping-pong register pre-read and write are simultaneously read and written on the rising edge of the clock 7, and the pre-full state is always valid.
The application adopts the three embodiments to obtain the beneficial effects that:
(1) aiming at a real-time back pressure scene of an on-chip RAM reading data pipeline, the pipeline is ensured not to be interrupted, and for an N-level pipeline, N-1 registers are required to be added on a second-level pipeline to form a ping-pong structure in the form of a register group;
2, aiming at a real-time back pressure scene of a general N-level pipeline structure (each level of pipeline registers have a data registering function), adding N-1 registers on a first level of pipeline to form a ping-pong structure in the form of a register group;
3 in order to ensure the transmission efficiency, the flow restarting under the patent scene adopts a 'pre-starting' strategy, namely, the ping-pong register of the second stage is 'pre-full' invalid or is 'pre-full' valid and is pre-started under the ACK valid;
while the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (9)
1. A real-time backpressure method for supporting a pipeline, comprising: adding a corresponding number of registers on a preset stage of the N-stage production line to form a register group with a ping-pong structure;
the collected data are sequentially stored in a register group of the ping-pong structure; aiming at the real-time back pressure situation of an N-stage production line of an RAM reading channel, adding (N-1) registers on the second stage of the N-stage production line, and forming N register groups with a ping-pong structure with the original registers of the second-stage production line; enabling the RAM read enabling signal to be effective, starting the assembly line, enabling the next beat of clock of the RAM read enabling signal to be effective, and starting the first-stage assembly line; then, the next beat of clock is valid, a second-stage production line is started, and data are collected and stored to a first register in the register groups of the N ping-pong structures; then, with the effective increment of the RAM read enabling clock, sequentially starting the rest (N-2) stages of pipelines, and sequentially storing the collected data in (N-1) registers of the ping-pong structure; the RAM read enable signal is valid for one of the following conditions: (1) read RAM data FF1 register pre-full invalid; (2) read RAM data FF1 register pre-full is active and the feedback ACK signal is active at the same time, where FF1 register pre-full state is read RAM enabled active and handshake transaction active.
2. The pipeline-enabled real-time backpressure method of claim 1,
aiming at the general N-stage pipeline real-time back pressure situation except the RAM read path, a (N-1) register is added on the first stage of the N-stage pipeline, and the register and the original register of the first stage pipeline form N ping-pong register groups.
3. The real-time backpressure method for supporting pipelines as claimed in claim 2, wherein the RAM read enable signal is valid, the pipeline is started, the next beat of clock of the RAM read enable signal is valid, the first-stage pipeline is started, and data is collected and stored to a first register in a register group of N ping-pong structures; then, the next beat of clock is valid, a second-stage production line is started, and the collected data is stored in a second register; and then sequentially starting the (N-2) stage pipelines along with the effective increment of the RAM read enabling clock, and sequentially storing the collected data into (N-2) registers of the ping-pong structure.
4. The method of claim 1, wherein a predetermined number of registers are provided in each stage of the pipeline in the N stages, and each stage of the pipeline and the register of the pipeline constitute a register group with a predetermined number plus 1 ping-pong structure.
5. The pipeline-capable real-time backpressure method of claim 1, wherein the predetermined number is an integer greater than or equal to 1 and less than or equal to (N-1).
6. The method for real-time backpressure supporting pipeline according to claim 1, characterized in that on the pipeline of the preset stage, data is controlled by the ACK signal to decide whether to perform handshake transaction, if the ACK signal is valid, the data handshake transaction is successful, if the ACK signal is invalid, the data handshake transaction is failed, and the next clock rising edge is waited until the ACK is valid.
7. The method of claim 6, wherein if the ACK signal is not valid on the pipeline of the predetermined level, the condition that the RAM read enable is valid comprises data in RAM and read RAM data FF1 register is not valid.
8. The method of claim 7, wherein if the ACK signal is not asserted at a certain time, the read RAM data FF1 register pre-full state is asserted, the pipeline is interrupted, and the read RAM enable is pre-asserted at the current time that the ACK signal is asserted, using a pre-assertion strategy.
9. A pipeline enabled real-time backpressure method as claimed in any one of claims 1 to 8, wherein N > -2.
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| CN201716564U (en) * | 2010-06-25 | 2011-01-19 | 中国科学院沈阳自动化研究所 | Processor architecture special for high-performance programmable logic controller (PLC) |
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| US20060259748A1 (en) * | 2005-05-13 | 2006-11-16 | Tay-Jyi Lin | Pipelined datapath with dynamically reconfigurable pipeline stages |
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Address after: 100084 16 Floors, Block A, Science and Technology Building, Tsinghua Science Park, No. 1 East Zhongguancun Road, Haidian District, Beijing Applicant after: New Shoreline (Beijing) Science and Technology Group Co.,Ltd. Address before: 100084 16 Floors, Block A, Science and Technology Building, Tsinghua Science Park, No. 1 East Zhongguancun Road, Haidian District, Beijing Applicant before: Beijing New Shoreline Technology Co.,Ltd. Address after: 100084 16 Floors, Block A, Science and Technology Building, Tsinghua Science Park, No. 1 East Zhongguancun Road, Haidian District, Beijing Applicant after: Beijing New Shoreline Technology Co.,Ltd. Address before: 100084 16 Floors, Block A, Science and Technology Building, Tsinghua Science Park, No. 1 East Zhongguancun Road, Haidian District, Beijing Applicant before: BEIJING PUJIXIN TECHNOLOGY CO.,LTD. |
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