JPH08147163A - Method and device for operation processing - Google Patents

Abstract

PURPOSE: To reduce the power consumption of the whole of the microprocessor which performs the pipeline processing by eliminating the unnecessary power consumption in stage units. CONSTITUTION: This operation processing device performs the pipeline processing of instructions and is provided with data processing parts 13 and 14 which perform prescribed data processings of instructions in respective stages of the pipeline, plural registers 15, 17, and 19 where processing contents inputted to and outputted from respective stages of data processing parts 13 and 14 are held, bypass lines which bypass these registers 15, 17, and 19 respectively, and a controller 21. When the frequency of the operation clock is set to the low clock frequency mode or the flow of data processings in respective stages of data processing parts 13 and 14 is monitored to find that held contents at this time of registers are stably held even in the next unit processing time because of branch instruction execution or the like, the controller bypasses pertinent one of registers 15, 17, and 19 by the bypass line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit and method which avoids wasteful power consumption.

[0002]

2. Description of the Related Art Conventionally, various kinds of electronic devices such as laptop or palmtop type personal computers, word processors, portable personal information devices, mobile phones, etc., which are supposed to be used for mobile use, require the operating time of a battery as a power source. A lot of efforts have been made on how to lengthen the battery, and various attempts have been made to solve this problem in two directions: increasing the capacity of the battery and reducing the power consumption.

Among these, in the direction of increasing the capacity of the battery, the development of a high-performance secondary battery in which the energy density of the battery is improved has been actively developed, and nickel, which is widely spread, is widely used. A nickel-hydrogen battery having an energy density of about 1.5 times that of a cadmium battery has already been put into practical use, and a lithium-ion battery having an energy density of about 2 to 3 times that of a nickel-cadmium battery has been gradually put into practical use. .

In order to reduce power consumption, a method of controlling power supply can be considered first. This is to finely control the power for each module and to suppress the power or stop the clock supply for those not used.

Further, since the power consumption is proportional to the square of the power supply voltage, the voltage of the power supply and the circuit operated by this power supply is being reduced, and generally 5 [V] to 3.3 is used.
Various attempts have been made to [V], and further to 2 [V] or less.

In the case of a CMOS logic circuit, the power consumption is proportional to the frequency of the operating clock. Therefore, when the processor load is light or in the waiting state, the clock frequency is lowered to save the average power consumption. There is an attempt to reduce the power consumption without degrading the processing performance by parallelizing the processing instead of suppressing the power consumption.

[0007]

However, particularly in a data processing device such as a personal computer, the processing performance of the processor has been remarkably improved year by year, and the power consumption required thereby has been increased, while the battery is made of a material. Since it is gradually increasing the density by improving the above, it is not possible to expect a dramatic improvement, and as a result it is difficult to significantly extend the operating time of the battery with the method of expanding the capacity of the battery. Is the current situation.

On the other hand, in the direction of reducing power consumption, the methods for lowering the voltage and lowering the frequency of the operating clock are currently limited in the possible range, and there is a trade-off with processing performance. The operating voltage and operating clock frequency cannot be reduced in general.

As for the method of controlling the power supply, the control of merely suppressing the power supply to the unused module has already been exhausted, and a new control method is required.

The present invention has been made in view of the above circumstances, and an object of the present invention is to eliminate unnecessary power consumption in units of stages, especially in a microprocessor for pipeline processing. An object of the present invention is to provide an arithmetic processing device and method capable of reducing the power consumption of the entire processor.

[0011]

That is, the present invention is an arithmetic processing unit for pipeline processing an instruction, the data processing section performing predetermined data processing for the instruction at each stage of the pipeline, and the data processing section. A register group consisting of a plurality of registers for holding the processing contents input / output to / from each stage, a bypass path for bypassing each register of the register group, and an operation clock frequency of the arithmetic processing unit in a low clock frequency mode. When it is reached or when the flow of data processing at each stage of the data processing unit is monitored, the contents held in the register at that time are stably held within the next unit processing time as when executing a branch instruction. When this occurs, a controller is provided to judge this and bypass the relevant register in the register group by the bypass path. In which was to so that.

[0012]

With the above-mentioned configuration, it is possible to reduce the power wasted in the processor without degrading the processing performance, and to improve the processing speed by the setup time of the bypassed register. It is also possible.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the system circuit configuration of the processor. The range indicated by the alternate long and short dash line is the pipeline processing unit 11, and 12 is the processor main body that performs processing corresponding to instructions other than pipeline processing.

Here, in order to simplify the structure of the pipeline processing unit 11, the processing for one instruction is divided into two stages. For example, the first data processing unit 13 performs the first stage of the pipeline. Fetching and decoding of instructions as the data processing of the second data processing unit 14
Then, as the data processing of the second stage of the pipeline, the execution of the instruction and the writing of the result to the corresponding memory are performed.

However, an instruction given from the processor main body 12 receives a register (reg.) In the pipeline processing unit 11.
Used for 15 and multiplexer (MPX) 16, register
The contents held in 15 are supplied to the multiplexer 16.

The multiplexer 16 selects one of the instruction directly given from the processor main body 12 and the content held in the register 15 in accordance with a register enable signal RE1 from the controller 21, which will be described later, and selects the first data processing section.
Send to 13.

The first data processing unit 13 performs the data processing of the first stage of the above-mentioned pipeline. The processing result is provided to the register 17 and the multiplexer 18, and the content held in the register 17 is provided to the multiplexer 18. It

The multiplexer 18 includes a first data processing unit 13
One of the processing result directly given from the register 17 and the content held in the register 17 is selected according to a register enable signal RE2 from the controller 21 which will be described later and is sent to the second data processing unit 14.

The second data processing unit 14 performs the data processing of the second stage of the above-mentioned pipeline. The processing result is provided to the register 19 and the multiplexer 20, and the content held in the register 19 is provided to the multiplexer 20. It

The multiplexer 20 includes a second data processing unit 14
One of the processing result directly given from the register 19 and the content held in the register 19 is selected according to a register enable signal RE3 from the controller 21, which will be described later, and sent to the processor body 12.

The controller 21 is a pipeline processing unit according to the frequency of the operation clock and the usage state of the pipeline.
Registers 15, 17, to reduce unnecessary power consumption in 11
The register enable signal RE1 is supplied to the register 15 and the multiplexer 16, the register enable signal RE2 is supplied to the register 17 and the multiplexer 18, and the register enable signal RE2 is supplied to the register 19 and the multiplexer 20. While each RE3 is sent, a status display signal S indicating the status of the pipeline at that time is also sent to the processor body 12.

Further, the register 17 and the processor main body 12 have an operation clock φ1 amplified by the clock driver 22.
However, the operating clock φ2 amplified by the clock driver 23 is supplied as an operating clock to the registers 15 and 19 and the processor main body 12, respectively.
And the operation clock φ2 constitute two-phase clocks which are mutually inverted.

Further, the charge discharge circuit (e) 24 is provided to connect the input and output ends of the clock drivers 22 and 23.
Is provided. The charge discharge circuit 24 is constructed as shown in FIG.

That is, in FIG. 2, the input end of the clock driver 22 is an NPN transistor TR2 via a resistor R1.
The base of the transistor TR2, the emitter of the transistor TR2 and the anode of the diode D1 are connected to the clock driver 22.
The collector of the transistor TR2 is connected to the cathode of the diode D2 at the output terminal of the transistor TR2.

On the other hand, the input end of the clock driver 23 is connected to the base of the NPN transistor TR1 via the resistor R2, and the emitter of this transistor TR1 and the anode of the diode D2 are connected to the output end of the clock driver 23.
The collector of the transistor TR1 is connected to the cathode of the diode D1.

Next, the operation of the above embodiment will be described. First, when the processor of FIG. 1 operates at a normal frequency, the controller 21 determines whether or not it is in the low clock mode as shown in FIG. 4, and the instruction to be processed is a branch instruction or the like that interrupts the continuous state of the instruction by the pipeline. It is continuously judged whether or not there is any (steps S1 and S2), and after confirming that these states are not satisfied, register enable signals RE1 to R1 to the registers 15, 17, 19 and multiplexers 16, 18, 20 are confirmed.
E3 is set to the active state "H", and at the same time, the state display signal S indicating the normal operation is sent to the processor main body 12 (step S3).

In response to this, the processor main body 12 requests the pipeline processing unit 11 to execute data processing and gives the register 15 and the multiplexer 16 instructions to be processed. At this time, the register 15 receives the instruction to be processed at the rising edge of the amplified operation clock φ2 output from the clock driver 23 from the processor main body 12, holds the instruction, and sends the held content to the multiplexer 16.

Since the register enable signal RE1 from the controller 21 is "H", the multiplexer 16 selects the content held in the register 15 as being enabled and sends it to the first data processing unit 13.

The first data processing unit 13 includes a multiplexer 16
The data sent from the first stage of the above-mentioned pipeline is processed with respect to the instruction sent from, and the processing result is sent to the register 17 and the multiplexer 18.

At this time, the register 17 is a clock driver.
An instruction to be processed at the rising edge of the amplified operation clock φ1 output from 22 is received from the first data processing unit 13 and held, and the held content is sent to the multiplexer 18.

Since the register enable signal RE2 from the controller 21 is "H", the multiplexer 18 selects the content held in the register 17 as being enabled and sends it to the second data processing section 14.

The second data processing section 14 includes a multiplexer 18
The data processing of the second stage of the above-mentioned pipeline is performed on the processing contents sent from the above, and the processing result is sent to the register 19 and the multiplexer 20.

At this time, the register 19 is a clock driver.
At the rising edge of the amplified operation clock φ2 output from 23, the processing result is received from the second data processing unit 14 and held, and the held content is sent to the multiplexer 20.

Since the register enable signal RE3 from the controller 21 is "H", the multiplexer 20 selects the content held in the register 19 as being enabled and sends it to the processor body 12. The processor body 12 receives the processing result from the multiplexer 20 and completes the data processing in the pipeline processing unit 11 for one instruction.

The operation in the charge discharge circuit 24 while operating at the normal clock frequency as described above will be described. As shown in FIG. 3, the operation clock φ1 and the operation clock φ2 are two-phase clocks, which are mutually inverted.

If the operation clock φ1 input to the clock driver 22 is "H" and the operation clock φ2 input to the clock driver 22 is "L", the output end of the clock driver 22 is "H". The output end of the clock driver 23 becomes "L".

Therefore, a reverse voltage is applied to the diode D2 and no current flows. On the other hand, although a forward voltage is applied to the diode D1, the transistor TR1 is off because the base is "L" by the operation clock φ2, and no current flows. In this state, positive charges are accumulated on the output line of the clock driver 22, and negative charges are accumulated on the output line of the clock driver 23.

Here, the operation clock φ1 input to the clock driver 22 changes from “H” to “L”, and the operation clock φ2 input to the clock driver 23 changes from “L” to “H”.
, The output end of the clock driver 23 becomes "L" and the output end of the clock driver 23 becomes "H".

As a result, the transistor TR1 is turned on, and the diode D1 goes from the output end line of the clock driver 22 toward the output end line of the clock driver 23.
When a current flows through the clock driver 22, the positive charge on the output line of the clock driver 22 is absorbed by the clock driver 22 and at the same time passes through the charge discharge circuit 24 to the clock driver.
It is sucked into the line at the output end of 23.

Therefore, the positive charge flows from the clock driver 23 to the output end line of the clock driver 23, and at the same time, the positive charge also flows from the output end line of the clock driver 22. Therefore, the charge discharging circuit 24 Can assist the transfer of charges and save the power consumed by the clock drivers 22 and 23.

When the movement of the charges is completed, the line at the output end of the clock driver 22 becomes "L" and the line at the output end of the clock driver 23 becomes "H", and the state is stabilized. Further, the operation clock φ1 input to the clock driver 22
Also changes from “L” to “H” and the operation clock φ2 input to the clock driver 23 changes from “H” to “L”, the movement directions of the charges are opposite. Since the same operation as described above is performed only by doing so, the description of the operation will be omitted.

Next, the processor of FIG. 1 sets the operation clocks φ1, φ in the low clock mode to save power consumption.
2 operates at a lower frequency or executes an instruction such as a branch instruction which interrupts the continuous state of the instruction by the pipeline, the controller 21 confirms this in the flowchart of FIG. 4 (step S1 and S2), after judging these states, for example, register
The register enable signals RE1 and RE3 to 15 and 19 and the multiplexers 16 and 20 are set to the active state "H", and the register enable signal RE2 to the register 17 and the multiplexer 18 is set to the inactive state "L", and at the same time for one stage. A status display signal S indicating bypassing the pipeline is sent to the processor main body 12 (step S
4).

In response to this, the processor main body 12 requests the pipeline processing unit 11 to execute data processing and gives the instruction to be processed to the register 15 and the multiplexer 16. At this time, the register 15 receives the instruction to be processed at the rising edge of the amplified operation clock φ2 output from the clock driver 23 from the processor main body 12, holds the instruction, and sends the held content to the multiplexer 16.

Since the register enable signal RE1 from the controller 21 is "H", the multiplexer 16 selects the content held in the register 15 as being enabled and sends it to the first data processing unit 13.

The first data processing section 13 includes a multiplexer 16
The data sent from the first stage of the above-mentioned pipeline is processed with respect to the instruction sent from, and the processing result is sent to the register 17 and the multiplexer 18.

At this time, the register 17 stops the operation of the internal flip-flop because the register enable signal RE2 from the controller 21 is inactive.
Do not hold.

Since the register enable signal RE2 from the controller 21 is "L", the multiplexer 18 directly selects the processing result from the first data processing unit 13 as being disabled and sends it to the second data processing unit 14. To do.

The second data processing section 14 includes a multiplexer 18
The data processing of the second stage of the above-mentioned pipeline is performed on the processing contents sent from the above, and the processing result is sent to the register 19 and the multiplexer 20.

At this time, the register 19 is a clock driver.
At the rising edge of the amplified operation clock φ2 output from 23, the processing result is received from the second data processing unit 14 and held, and the held content is sent to the multiplexer 20.

Since the register enable signal RE3 from the controller 21 is "H", the multiplexer 20 selects the content held in the register 19 as being enabled and sends it to the processor body 12. The processor body 12 receives the processing result from the multiplexer 20 and completes the data processing in the pipeline processing unit 11 for one instruction.

By the above operation, the register 17 is bypassed and the operation is temporarily stopped, so that wasteful power consumption is suppressed but the processing performance is not deteriorated. The processing speed can be improved by just that much.

Even in the low clock mode or during the execution of an instruction that interrupts the continuous state of the instruction by the pipeline, the charge discharge circuit 24 assists the movement of the charge in the same manner as in the normal operation, and the clock driver 22, Since the power consumed by 23 is saved, the power consumption can be further reduced.

In the above embodiment, the clock driver 2 assists the movement of charges in the structure shown in the charge discharge circuit 24 for the operation clocks φ1 and φ2 which are two-phase clocks.
Although the power consumption in 2 and 23 is suppressed, it is needless to say that the invention is not limited to this and can be applied to a more multiphase clock.

[0054]

As described above, according to the present invention, it is possible to reduce the power wasted by the processor without degrading the processing performance, and to reduce the processing speed by the setup time of the bypassed register. It is possible to provide an arithmetic processing device and method capable of improving the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

2 is a diagram showing a detailed circuit configuration in the charge discharge circuit of FIG.

FIG. 3 is a diagram showing an operation clock according to the embodiment.

FIG. 4 is a flowchart showing the processing contents by the controller of FIG.

[Explanation of symbols]

11 ... Pipeline processing unit, 12 ... Processor body, 13 ... First data processing unit, 14 ... Second data processing unit, 15, 17, 19 ...
Registers (reg.), 16, 18, 20 ... Multiplexer (MPX), 21 ... Controller, 22, 23 ... Clock driver, 24 ... Charge discharge circuit (e).

Claims (6)

[Claims] 1. An arithmetic processing unit for pipeline processing an instruction, comprising: data processing means for performing predetermined data processing for an instruction at each stage of the pipeline; and processing input / output to / from each stage of the data processing means. A register group consisting of a plurality of registers for holding contents, a bypass means for bypassing each register of this register group, and a judgment made when the operation clock frequency of the arithmetic processing unit becomes a low clock frequency mode. An arithmetic processing unit comprising: a control unit that bypasses a predetermined register in the register group by the bypass unit. 2. An arithmetic processing unit for pipeline processing an instruction, comprising: data processing means for performing predetermined data processing for an instruction at each stage of the pipeline; and processing input / output to / from each stage of the data processing means. A register group consisting of a plurality of registers for holding contents, a bypass means for bypassing each register of this register group, a flow of data processing at each stage of the above data processing means is monitored, and the register at that time is held Arithmetic processing, characterized in that when the contents are held stably within the next unit processing time, it is judged and the bypass means bypasses the corresponding register in the register group. apparatus. 3. The arithmetic processing unit according to claim 2, wherein the control means determines that the instruction processed by the data processing means is a branch instruction and bypasses the register. 4. An arithmetic processing method for pipeline processing an instruction, wherein processing contents input / output at each stage of a data processing unit for performing predetermined data processing for an instruction at each stage of the pipeline are processed from a plurality of registers. The arithmetic processing method is characterized in that each of the registers is held in a different register group, and when the operating clock frequency becomes a low clock frequency mode, this is judged and a predetermined register in the register group is bypassed. 5. An arithmetic processing method for pipeline processing an instruction, wherein processing contents input / output at each stage of a data processing unit which performs predetermined data processing for an instruction at each stage of the pipeline are registered from a plurality of registers. Each register group holds the data and monitors the flow of data processing at each stage of the above data processing unit. When the contents held in the register at that point are stably held within the next unit processing time, And a predetermined register in the register group is bypassed. 6. An arithmetic processing unit for pipeline processing an instruction, comprising: a first stage and a second stage for respectively performing predetermined data processing.
Stage, a first line for guiding the processing result of the first stage, a register for holding the processing result of the first stage guided by the first line, and the contents held in the register And a second line for outputting the above operation line, and the second line is selected when the operation clock frequency of the arithmetic processing is the normal clock frequency mode, and the first line is selected when the operation clock frequency is the low clock frequency mode. An arithmetic processing unit, comprising: a selecting unit for outputting to two stages.