US20170278856A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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US20170278856A1
US20170278856A1 US15/509,148 US201515509148A US2017278856A1 US 20170278856 A1 US20170278856 A1 US 20170278856A1 US 201515509148 A US201515509148 A US 201515509148A US 2017278856 A1 US2017278856 A1 US 2017278856A1
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gate electrode
region
silicide layer
film
metal
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Tadashi Yamaguchi
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L27/11563—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and is preferably applicable to, for example, a semiconductor device having a nonvolatile memory and a method for manufacturing the same.
  • a memory cell including a conductive floating gate electrode surrounded by an oxide film or a trapping insulating film sandwiched by an oxide film below the gate electrode of the MISFET is widely used.
  • the latter is referred to as a MONOS (Metal Oxide Nitride Oxide Semiconductor) type including a single gate type cell and a split gate type cell, and is used as a nonvolatile memory of a microcomputer.
  • MONOS Metal Oxide Nitride Oxide Semiconductor
  • a transistor including a metal gate electrode and a high dielectric constant film (high-k film) is used in a logic portion.
  • a gate-last process As a method for forming such a transistor, so-called a gate-last process is known, the gate-last process forming a source/drain region by using a dummy gate electrode made of a polycrystalline silicon film on a substrate, and then, replacing the dummy gate electrode with a metal gate electrode.
  • Patent Document 1 Japanese Patent Application Laid-open Publication No. 2014-154790 describes a case of mixedly mounting the memory cell and the MISFET of the logic portion, in which a silicide layer is formed on a source/drain region of the MISFET, subsequently a metal gate electrode of the MISFET is formed by the gate-last process, and then, a silicide layer is formed on the gate electrode of the memory cell.
  • Patent Document 2 Japanese Patent Application Laid-Open Publication No. 2007-335834 describes a configuration in which in order to set an appropriate threshold value voltage in an n-type FET and a p-type FET having a full silicide gate, in the n-type FET, a gate electrode made of nickel silicide having a nickel content higher than a silicon content is formed on the gate insulating film with an aluminum layer being interposed therebetween. Moreover, it is described that in the p-type FET, a gate electrode made of nickel silicide having a nickel content higher than a silicon content is formed on the gate insulating film. Furthermore, on the surface of the source/drain region of the n-type FET and the p-type FET, a silicide layer is formed.
  • Patent Document 1 Japanese Patent Application Laid-Open Publication No. 2014-154790
  • Patent Document 2 Japanese Patent Application Laid-Open Publication No. 2007-335834
  • the gate electrode of the MISFET of the logic part is formed by using the gate last process. That is, a first silicide layer is formed on the memory cell and the source/drain region of the MISFET of the logic part, and the metal gate electrode of the MISFET of the logic part is formed, and then, a second silicide layer is formed on the gate electrode of the MISFET of the memory cell. Meanwhile, the first silicide layer and the second silicide layer have the same composition as each other.
  • An object of the present application is to ensure reliability of a semiconductor device. Moreover, another object is to improve a performance of the semiconductor device.
  • the MISFET has a gate electrode formed on a semiconductor substrate via a gate insulating film and a source/drain region formed inside the semiconductor substrate so as to sandwich the gate electrode.
  • a first silicide layer is formed on a surface of the source/drain region, and a second silicide layer is formed on a surface of the gate electrode.
  • Each of the first silicide layer and the second silicide layer is made of a first metal and silicon, and contains a second metal different from the first metal.
  • a concentration of the second metal in the second silicide layer is lower than a concentration of the second metal in the first silicide layer.
  • the reliability of the semiconductor device can be ensured. Moreover, the performance of the semiconductor device can be improved.
  • FIG. 1 is a cross-sectional view of a principal part of a semiconductor device according to one embodiment
  • FIG. 2 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device of one embodiment
  • FIG. 3 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 2 ;
  • FIG. 4 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 3 ;
  • FIG. 5 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 4 ;
  • FIG. 6 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 5 ;
  • FIG. 7 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 6 ;
  • FIG. 8 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 7 ;
  • FIG. 9 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 8 ;
  • FIG. 10 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 9 ;
  • FIG. 11 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 10 ;
  • FIG. 12 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 11 ;
  • FIG. 13 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 12 ;
  • FIG. 14 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 13 ;
  • FIG. 15 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 14 ;
  • FIG. 16 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 15 ;
  • FIG. 17 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 16 ;
  • FIG. 18 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 17 ;
  • FIG. 19 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 18 ;
  • FIG. 20 is a cross-sectional view of a principal part during a manufacturing process of the semiconductor device, continued from FIG. 19 .
  • symbols “ ⁇ ” and “+” represent relative concentrations of impurities whose conductivity type is n-type or p-type.
  • the impurity concentrations increase in the order of “n ⁇ ” to “n + ”.
  • a semiconductor device (semiconductor integrated circuit device) of the present embodiment is a semiconductor device including a nonvolatile memory (a nonvolatile storage element, a flash memory) such as a microcomputer.
  • the microcomputer includes a CPU (Central Processing Unit), a RAM (Random Access Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), a flash memory and an I/O (Input/Output) circuit, etc.
  • the CPU requires high-speed operations and low power consumption, and therefore, is configured by a MISFET (MISFET: Metal Insulator Semiconductor Field Effect Transistor) being driven at a low voltage (for example, 5V or less) and having a low breakdown voltage with a low threshold value.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the EEPROM or the flash memory has a plurality of nonvolatile memory cells disposed into a matrix form, and a control circuit for performing writing, erasing and reading operations on the nonvolatile memory cells. Particularly, in the writing and erasing operations, since a high voltage is applied to the nonvolatile memory cells, a MISFET being driven at a high voltage (for example, 10V or more) and having a high breakdown voltage is included in the control circuit.
  • a high voltage for example, 10V or more
  • the nonvolatile memory will be explained while exemplifying a memory cell based on an n-channel type MISFET.
  • a p-channel type MISFET may be exemplified.
  • the CPU and control circuit are configured by an n-channel type MISFET and a p-channel type MISFET.
  • the explanation will be made while exemplifying an n-channel type MISFET.
  • FIG. 1 is a cross-sectional view of a principal part of the semiconductor device of the present embodiment.
  • FIG. 1 shows a memory cell region 1 A on the left side, a peripheral circuit region 1 B at the center, and a peripheral circuit region 1 C on the right side.
  • a memory cell MC of a nonvolatile memory is formed in the memory cell region 1 A
  • a low breakdown voltage MISFET (Q 1 ) is formed in the peripheral circuit region 1 B
  • the high breakdown voltage MISFET (Q 2 ) is formed in the peripheral circuit region 1 C.
  • the reference symbol portion is indefinite, parentheses are given to the reference symbol.
  • the semiconductor device is formed on the main surface of the semiconductor substrate SB.
  • the semiconductor substrate SB is a semiconductor wafer made of, for example, a p-type single crystal silicon or others having a specific resistance in a range of about 1 to 10 ⁇ cm.
  • the channel direction (direction connecting the source region and the drain region) of the p-channel type MISFET on the (100) plane of the single crystal silicon substrate is set to ⁇ 110> or ⁇ 100>.
  • the channel direction of the n-channel type MISFET (direction connecting the source region and the drain region) thereon is also set to ⁇ 110> or ⁇ 100>.
  • the semiconductor device has an active region and an element isolation region ST formed on the main surface of the semiconductor substrate SB.
  • the element isolation region ST is used for isolating elements (memory cells) formed in the active region.
  • an element isolation film made of a silicon oxide film or others is formed in the element isolation region ST.
  • the active region is surrounded by the element isolation region ST, and is defined, that is, partitioned by the element isolation region ST.
  • the memory cell region 1 A has a plurality of the active regions, and the plurality of active regions are electrically isolated from each other by the element isolation region ST.
  • a p-type well PW 1 having a p-conductivity type on which the plurality of memory cells MC are disposed is formed.
  • the memory cell MC is a memory cell of a split gate type.
  • the memory cell MC is formed inside the p-type well PW 1 , and has the control gate electrode CG and the memory gate electrode MG.
  • the memory cell MC has an n-type extension region (n ⁇ -type semiconductor region, low concentration region, impurity diffusion region) EX, an n-type diffusion region (n′-type semiconductor region, a high concentration region, an impurity diffusion region) DF, a control gate electrode CG, and a memory gate electrode MG.
  • Each of the n-type extension region EX and the n-type diffusion region DF has an n-conductivity type that is an opposite conductivity type to the p-conductivity type.
  • the memory cell MC has a silicide layer (gate silicide layer) S 2 formed on the upper surface of the control gate electrode CG and the upper surface of the memory gate electrode MG, and also has a silicide layer (SD silicide layer) S 1 formed on the upper surface of the diffusion region DF.
  • gate silicide layer gate silicide layer
  • SD silicide layer silicide layer
  • the memory cell MC has a gate insulating film GIt formed between the control gate electrode CG and the semiconductor substrate SB (or the p-type well PW 1 ) and a gate insulating film GIm formed between the memory gate electrode MG and the semiconductor substrate SB (or the p-type well PW 1 ) and between the memory gate electrode MG and the control gate electrode CG.
  • the control gate electrode CG and the memory gate electrode MG are extended along the main surface of the semiconductor substrate SB and disposed side by side between their opposed side surfaces to each other, that is, between their sidewalls, via the gate insulating film GIm.
  • Each extending direction of the control gate electrode CG and the memory gate electrode MG is a direction perpendicular to the drawing sheet of FIG. 1 .
  • the control gate electrode CG is integrally formed in common with one another.
  • the memory gate electrode MG is integrally formed in common with one another. In other words, in order to achieve the high-speed operations of the nonvolatile memory, it is important to achieve the low resistances of the control gate electrode CG and the memory gate electrode MG.
  • the control gate electrode CG and the memory gate electrode MG are adjacent to each other via the gate insulating film GIm therebetween, and the memory gate electrode MG is formed in a sidewall spacer form on the side surfaces, that is, the sidewalls of the control gate electrode CG via the gate insulating film GIm. Moreover, the gate insulating film GIm is extended over a region between the memory gate electrode MG and the semiconductor substrate SB and a region between the memory gate electrode MG and the control gate electrode CG.
  • the gate insulating film GIt is made of an insulating film IF 1 .
  • the insulating film IF 1 is made of a silicon oxide film, a silicon nitride film, an oxynitride silicon film, or a high dielectric constant film having a dielectric constant (relative permittivity) higher than that of the silicon nitride film, that is, a so-called High-k film.
  • the High-k film or the high dielectric constant film is described, note that this means a film having a dielectric constant (relative permittivity) higher than that of the silicon nitride film.
  • a metal oxide film such as a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film or a lanthanum oxide film can be used.
  • the gate insulating film GIm is made of an insulating film ON.
  • the insulating film ON is configured by a stacked film including a silicon oxide film OX 1 , a silicon nitride film NT formed on the silicon oxide film OX 1 and a silicon oxide film OX 2 formed on the silicon nitride film NT.
  • the gate insulating film GIm located between the memory gate electrode MG and the control gate electrode CG functions as an insulating film for insulating a gap between the memory gate electrode MG and the control gate electrode CG, that is, for electrically isolating these electrodes from each other. Therefore, the insulating film between the memory gate electrode MG and the control gate electrode CG may be formed as an insulating film that is separated or different from the insulating film between the memory gate electrode MG and the semiconductor substrate SB.
  • the silicon nitride film NT of the insulating films ON is an insulating film for storing charges, and functions as a charge storage portion. That is, the silicon nitride film NT is a trapping insulating film formed in the insulating film ON. For this reason, the insulating film ON can be regarded as an insulating film having a charge storage portion therein.
  • the silicon oxide film OX 1 and the silicon oxide film OX 2 located on the upper and lower sides of the silicon nitride film NT are allowed to function as charge block layers for trapping the charges inside. That is, by providing a configuration in which the silicon nitride film NT is sandwiched by the silicon oxide film OX 1 and the silicon oxide film OX 2 , leakage of the charges stored in the silicon nitride film NT can be prevented.
  • the control gate electrode CG is made of a silicon film PS 1 .
  • the silicon film PS 1 is made of silicon, and is made of, for example, an n-type polysilicon film or others serving as a polycrystal silicon film to which an n-type impurity is introduced. More specifically, the control gate electrode CG is made of a patterned silicon film PS 1 .
  • a silicide layer S 2 is formed on the upper surface of the silicon film PS 1 forming the control gate electrode CG.
  • the silicide layer S 2 is also extended in a direction perpendicular to the surface sheet of FIG. 1 as similar to the control gate electrode CG.
  • the memory gate electrode MG is made of a silicon film PS 2 .
  • the silicon film PS 2 is made of silicon, and is made of, for example, a p-type polysilicon film or others serving as a polycrystal silicon film to which a p-type impurity is introduced.
  • the memory gate electrode MG is formed in a sidewall spacer form on one sidewall of the control gate electrode CG adjacent to this memory gate electrode MG via the gate insulating film GIm.
  • a silicide layer S 2 is formed on the upper surface of the silicon film PS 2 forming the memory gate electrode MG.
  • the silicide layer S 2 is also extended in a direction perpendicular to the surface sheet of FIG. 1 as similar to the memory gate electrode MG.
  • FIG. 1 separately shows the control gate electrode CG and the silicide layer S 2 . However, they are sometimes referred to as control gate electrode so as to include the silicide layer S 2 . A relation between the memory gate electrode MG and the silicide layer S 2 is similarly described.
  • the silicide layer S 2 formed on each upper surface of the control gate electrode CG and the memory gate electrode MG is an alloy layer of nickel (Ni) and silicon (Si) containing platinum (Pt) as an additive.
  • the content (content rate) of platinum is preferably less than 5% (including 0%).
  • the extension region EX and the diffusion region DF are semiconductor regions functioning as a source region or a drain region.
  • Each of the extension region EX and the diffusion region DF is made of a semiconductor region to which an n-type impurity is introduced, and both of them form an LDD (Lightly doped drain) structure.
  • the diffusion region DF has a concentration higher than that of the extension region EX, and also has a large junction depth relative to the well region PW 1 .
  • the paired extension region EX and the diffusion region DF are disposed on both ends of the control gate electrode CG and the memory gate electrode MG so as to sandwich the control gate electrode CG and the memory gate electrode MG therebetween.
  • the extension regions EX are disposed between one of the diffusion regions DF and the control gate electrode CG and between the other diffusion region DF and the memory gate electrode MG.
  • a silicide layer S 1 is formed on the diffusion region DF, that is, on the upper surface (surface) of the diffusion region DF.
  • the silicide layer S 1 formed on the upper surface of the diffusion region DF is an alloy layer of nickel (Ni) and silicon (Si) that contains platinum (Pt) as an additive.
  • the content (content rate) of the platinum (Pt) is 5% or more (more preferably, 5% or more and 10% or less).
  • a region including the extension region EX, the diffusion region DF and the silicide layer S 1 is sometimes represented as the source region or the drain region.
  • each of the silicide layers S 1 and S 2 may be a cobalt silicide layer containing the additive, and the additive may be aluminum (Al) or carbon (C).
  • a sidewall spacer SW made of an insulating film such as a silicon oxide film, a silicon nitride film or a stacked film of these films is formed.
  • the semiconductor device has an active region and an element isolation region ST formed on the main surface of the semiconductor substrate SB.
  • the structure and the functions of the element isolation region ST are as described above.
  • the active region is defined, that is, partitioned by the element isolation region ST, is electrically isolated from other active region in the peripheral circuit region 1 B by the element isolation region ST, and a p-type well PW 2 having a p-conductivity type is formed in the active region.
  • the p-type well PW 1 in the memory cell region 1 A is surrounded by an n-type well not shown, and is electrically isolated from the p-type well PW 2 . That is, a potential different from that of the p-type well PW 2 can be applied to the p-type well PW 1 .
  • the low breakdown voltage MISFET (Q 1 ) which is formed in the peripheral circuit region 1 B, has an n-type extension region (n ⁇ -type semiconductor region, low concentration region, impurity diffusion region) EX and an n-type diffusion region (n + -type semiconductor region, high concentration region, impurity diffusion region) DF that are formed inside the p-type well PW 2 and serve as the gate electrode G 1 and the source region or the drain region.
  • the low breakdown voltage MISFET (Q 1 ) has the silicide layer (SD silicide layer) S 1 formed on the upper surface of the diffusion region DF.
  • the silicide layer (SD silicide layer) S 1 has the same composition as the silicide layer S 1 formed in the source region and the drain region of the memory cell MC. However, on the upper surface of the gate electrode G 1 , no silicide layer S 2 is formed. Moreover, the low breakdown voltage MISFET (Q 1 ) has a gate insulating film GIL formed between the gate electrode G 1 and the semiconductor substrate SB (or p-type well PS 2 ).
  • the gate insulating film GIL has a stacked structure configured by an insulating film IF 4 and an insulating film HK formed on the insulating film IF 4 .
  • the insulating film IF 4 is, for example, a silicon oxide film
  • the insulating film HK is, for example, an insulating material film having a dielectric constant (relative permittivity) higher than those of silicon oxide and silicon nitride, which is a so-called high-k film (high dielectric constant film).
  • a metal oxide film such as a hafnium oxide (HfO) film, a zirconium oxide (ZrO) film, an aluminum oxide (AlO) film, a tantalum oxide (TaO) film or a lanthanum oxide (LaO) film may be used.
  • the hafnium oxide (HfO) film is a film containing hafnium (Hf) and oxygen (O), and its composition ratio is not particularly limited. The same goes for the zirconium oxide (ZrO) film, the aluminum oxide (AlO) film, the tantalum oxide (TaO) film or the lanthanum oxide (LaO) film.
  • a gate electrode G 1 is formed via a metal film TN.
  • the metal film TN is a film for use in adjusting the threshold voltage of the low breakdown voltage MISFET (Q 1 ).
  • the metal film TN for example, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium carbide (TiC) film, a tantalum carbide (TaC) film, a tungsten carbide (WC) film, a tantalum carbide nitride (TaCN) film, a titanium (Ti) film, a tantalum (Ta) film, a titanium aluminum (TiAl) film, an aluminum (Al) film or others can be used.
  • TiN titanium nitride
  • TaN tantalum nitride
  • WN tungsten nitride
  • TiC titanium carbide
  • TaC tanta
  • the gate electrode G 1 is made of a metal film.
  • the metal film means a conductive film having metal conductivity, and is not only a single metal film (pure metal film) or an alloy film but also includes a metal compound film having metal conductivity.
  • a titanium aluminum (TiAl) film can selected as the metal film TN
  • an aluminum (Al) film can be selected as the gate electrode G 1 on the metal film TN.
  • the extension region EX and the diffusion region DF are semiconductor regions functioning as a source region or a drain region.
  • Each of the extension region EX and the diffusion region DF is made of a semiconductor region to which an n-type impurity is introduced, and both of them form an LDD structure.
  • the diffusion region DF has a concentration higher than that of the extension region EX, and also has a large junction depth relative to the well region PW 2 .
  • the extension regions EX are disposed between one of the diffusion regions DF and the gate electrode G 1 and between the other diffusion region DF and the gate electrode G 1 .
  • the above-described silicide layer S 1 is formed on the diffusion region DF, that is, on the upper surface (surface) of the diffusion region DF.
  • a sidewall spacer SW made of an insulating film such as a silicon oxide film, a silicon nitride film or a stacked film of these films is formed. Note that they are sometimes referred to as the source region or the drain region so as to include the extension region EX, the diffusion region DF and the silicide layer S 1 .
  • the semiconductor device has an active region and an element isolation region ST formed on the main surface of the semiconductor substrate SB.
  • the structure and the functions of the element isolation region ST are as described above.
  • the active region is defined, that is, partitioned by the element isolation region ST, is electrically isolated from other active region in the peripheral circuit region 1 C by the element isolation region ST, and a p-type well PW 3 having a p-conductivity type is formed in the active region.
  • the p-type well PW 1 is surrounded by an n-type well not shown, and therefore, is electrically isolated from the p-type well PW 3 . That is, a potential different from that of the p-type well PW 3 can be applied to the p-type well PW 1 .
  • the high breakdown voltage MISFET (Q 2 ) which is formed in the peripheral circuit region 1 C, has an n-type extension region (n 31 -type semiconductor region, low concentration region, impurity diffusion region) EX and an n-type diffusion region (n + -type semiconductor region, high concentration region, impurity diffusion region) DF that are formed inside the p-type well PW 3 and serve as the gate electrode G 2 and the source region or the drain region.
  • the high breakdown voltage MISFET (Q 2 ) has the silicide layer (SD silicide layer) S 1 formed on the upper surface of the diffusion region DF, and has the silicide layer (gate silicide layer) S 2 formed on the upper surface of the gate electrode G 2 .
  • the silicide layers S 1 and S 2 are the same as the above-described silicide layers S 1 and S 2 .
  • the high breakdown voltage MISFET (Q 2 ) has agate insulating film GIH formed between the gate electrode G 2 and the semiconductor substrate SB (or p-type well PW 3 ).
  • the breakdown voltage between the source region and the drain region can be improved.
  • the gate length means a length of the gate electrode in a direction connecting the source region and the drain region with each other. That is, the length is the length of the gate electrode in a lateral direction of the drawing sheet of FIG. 1 .
  • the gate insulating film GIH is made of an insulating film IF 1 .
  • the insulating film IF 1 is made of a silicon oxide film, a silicon nitride film or a silicon oxynitride film, and more preferably, is thicker than the gate insulating film GIt.
  • a thickness of the insulating film IF 1 is preferably larger than that of the gate insulating film GIL of the low breakdown voltage MISFET (Q 1 ) in equivalent oxide thickness, and more preferably, thicker than at least the insulating film IF 4 .
  • a gate electrode G 2 is disposed on the gate insulating film GIH, and the gate electrode G 2 is made of the above-described silicon film PS 1 . Moreover, on the upper surface of the gate electrode G 2 , the above-described silicide layer S 2 is formed.
  • the source region and drain region of the high breakdown voltage MISFET (Q 2 ) have the LDD structure configured by an extension region EX and a diffusion region DF as similar to the low breakdown voltage MISFET (Q 1 ). However, more preferably, the impurity concentration of the extension region EX of the high breakdown voltage MISFET (Q 2 ) may be lower than the impurity concentration of the extension region EX of the low breakdown voltage MISFET (Q 1 ).
  • the silicide layer S 1 formed on the upper surface of the diffusion region DF of the high breakdown voltage MISFET (Q 2 ) is the same as the silicide layer S 1 formed on the upper surface of the diffusion region DF of the low breakdown voltage MISFET (Q 1 ) and the memory cell MC.
  • the silicide layer S 2 formed on the upper surface of the gate electrode G 2 of the high breakdown voltage MISFET (Q 2 ) is the same as the silicide layer S 2 formed on the upper surface of the control gate electrode CG and the memory gate electrode MG of the memory cell MC.
  • the channel direction that is, a direction from the source region toward the drain region
  • the high breakdown voltage MISFET (Q 2 ) is set to a ⁇ 110> or ⁇ 100> direction
  • whisker defects which expands the silicide layer S 1 formed on the upper surface of the diffusion region DF in the channel direction tends to easily occur.
  • platinum (Pt) is contained in the silicide layer S 1 , the occurrence of the whisker defects can be prevented.
  • a sidewall spacer SW made of an insulating film such as a silicon oxide film, a silicon nitride film or a stacked film of these films is formed on the sidewalls of the gate electrode G 2 . Note that they are sometimes referred to as the source region or the drain region so as to include the extension region EX, the diffusion region DF and the silicide layer S 1 .
  • a stacked film of an insulating film IF 7 and an interlayer insulating film IL 1 is formed so as to fill gaps between the control gate electrode CG and the memory gate electrode MG of the memory cell MC and between the gate electrode G 1 of the low breakdown voltage MISFET (Q 1 ) and the gate electrode G 2 of the high breakdown voltage MISFET (Q 2 ).
  • the upper surface of the stacked film of the insulating film IF 7 and the interlayer insulating film IL 1 has almost the same height as the upper surfaces of the control gate electrode CG, the memory gate electrode MG and the gate electrodes G 1 and G 2 .
  • the insulating film IF 7 is made of, for example, a silicon nitride film
  • the interlayer insulating film IL 1 is made of, for example, a silicon oxide film.
  • an interlayer insulating film IL 2 made of, for example, a silicon oxide film is formed on the interlayer insulating film IL 1 .
  • an insulating film IF 9 made of a silicon oxide film is interposed between the interlayer insulating film IL 1 and the interlayer insulating film IL 2 .
  • contact holes each of which exposes, for example, a part of the silicide layer S 1 on the surface of the diffusion region DF are formed in the insulating film IF 7 , the interlayer insulating film IL 1 and the interlayer insulating film IL 2 , and a conductive contact plug CP is formed inside each of the contact holes.
  • the contact plug CP is configured by a main conductor made of tungsten (W) or others and a barrier conductor film (for example, a titanium film, a titanium nitride film or a stacked film of these films), and the barrier conductor film is interposed between the main conductor and the silicide layer S 1 .
  • the contact hole also penetrates the insulating film IF 9 .
  • a wiring layer M 1 serving as a first layer is disposed on each of the contact plugs CP, and the wiring layer M 1 is connected to the silicide layer S 1 via the contact plug CP. That is, the wiring layer M 1 is electrically connected to the diffusion region DF.
  • the wiring layer M 1 is formed by a conductor film containing, for example, aluminum (Al) or copper (Cu) as a main conductor.
  • a concentration (content) of an additive contained in the silicide layer S 1 formed on the upper surface of the diffusion region DF it is important to make a concentration (content) of an additive contained in the silicide layer S 1 formed on the upper surface of the diffusion region DF to be higher than a concentration (content) of an additive contained in the silicide layer S 2 formed on the upper surfaces of the control gate electrode CG, the memory gate electrode MG and the gate electrode G 2 .
  • the resistance of the gate electrode including the silicide layer S 2 is increased by the increase in the sheet resistance of the silicide layer S 2 , and therefore, the high-speed operation is prevented. Since crystal grains of a silicide layer having a high additive concentration are miniaturized, a possibility of grain-boundary scattering of the electric current (electrons) flowing through the silicide layer becomes higher. Moreover, because the additive is contained, the possibility of the electron scattering becomes higher. It is considered that the sheet resistance of the silicide layer is increased because of these factors.
  • the crystal grain size of the silicide layer S 2 can be made larger than the crystal grain size of the silicide layer S 1 .
  • This manner has such a feature as reducing the sheet resistance of the silicide layer S 2 . That is, this manner is effective for operating the MISFET at the high speed because of the reduction of the resistance of the gate electrode of the MISFET.
  • the sheet resistance of the silicide layer S 2 can be reduced.
  • the control gate electrode CG or the memory gate electrode MG of the memory cell MC is also used as a common wiring for a plurality of memory cells MC, and therefore, the length of each of the control gate electrode CG and the memory gate electrode MG in the gate width direction becomes longer than that of the low breakdown voltage MISFET (Q 1 ) formed in the peripheral circuit region 1 B. For this reason, the reduction in the resistance of the silicide layer S 2 on the upper surface of the control gate electrode CG or the memory gate electrode MG is effective for operating the nonvolatile memory at the high speed.
  • the concentration of the additive contained in each of the silicide layers S 1 and S 2 means, for example, a concentration thereof per unit area of the surface of each of the silicide layers S 1 and S 2 .
  • relative comparison in a content rate between the first metal (for example, Ni) and the second metal (for example, Pt) that is an additive contained in the silicide layers S 1 and S 2 containing silicon can be made by, for example, an energy dispersive X-ray spectroscopy (EDX) method.
  • EDX energy dispersive X-ray spectroscopy
  • the element analysis and composition analysis of the silicide layers S 1 and S 2 can be executed by detecting the characteristic X-ray caused by irradiating the surface (upper surface) of each of the silicide layers S 1 and S 2 with an electron beam, and performing the spectroscopy based on energy.
  • each of the control gate electrode CG and the memory gate electrode MG forming the memory cell MC is configured by a polysilicon film and a silicide layer S 2 formed on the surface (upper surface) of the polysilicon film, and the control gate electrode CG and the memory gate electrode MG are isolated from each other by a gate insulating film GIm.
  • a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 2 to 20 .
  • FIGS. 2 to 20 are cross-sectional views during manufacturing processes of the semiconductor device of the present embodiment. Each cross-sectional view of FIGS. 2 to 20 corresponds to the cross-sectional view of FIG. 1 .
  • the memory cell region 1 A is shown on the left side in each of the drawings, the peripheral circuit region 1 B is shown at the center therein, and the peripheral circuit region 1 C is shown on the right side therein.
  • the drawings show the formation of the memory cell MC of the nonvolatile memory in the memory cell region 1 A and the formation of the low breakdown voltage MISFET (Q 1 ) and the high breakdown voltage MISFET (Q 2 ) in the peripheral circuit regions 1 B and 1 C, respectively.
  • a semiconductor substrate (semiconductor wafer) SB made of a p-type single crystal silicon (Si) or others is prepared as shown in FIG. 2 . Then, on the main surface of the semiconductor substrate SB, a plurality of element isolation regions ST for defining the active regions are formed.
  • Each of the element isolation regions ST is made of an insulator such as silicon oxide, and can be formed by using, for example, an STI method, an LOCOS method or others. Here, the formation of the element isolation regions by using the STI method will be described.
  • the silicon nitride film and the silicon oxide film are etched by using a photolithography technique and a dry etching method so that patterned silicon nitride film and silicon oxide film that selectively cover the active regions are formed.
  • trenches are formed on the upper surface of the semiconductor substrate SB exposed from the patterned silicon nitride film and silicon oxide film. A plurality of the trenches are formed.
  • the respective insulating films on the silicon nitride film are removed by a polishing process or others, so that a plurality of element isolation regions ST are formed.
  • the element isolation regions ST are formed so as to surround the active region, and are formed among the memory cell region 1 A, the peripheral circuit region 1 B and the peripheral circuit region 1 C. Thus, a configuration shown in FIG. 2 is obtained.
  • p-type wells PW 1 , PW 2 and PW 3 are formed on the main surface of the semiconductor substrate SB in the memory cell region 1 A, the peripheral circuit region 1 B and the peripheral circuit region 1 C.
  • the p-type wells PW 1 , PW 2 and PW 3 can be formed by ion-implanting a p-type impurity such as boron (B) to the semiconductor substrate SB.
  • a p-type impurity such as boron (B)
  • the p-type wells PW 1 , PW 2 and PW 3 to be formed in the respective formation regions of the memory cell MC, the high breakdown voltage MISFET (Q 2 ), the low breakdown voltage MISFET (Q 1 ) or others can be formed by using the same ion-implanting process.
  • the concentration of the p-type well PW 3 in the peripheral circuit region 1 C is preferably set to be higher than the concentration of the p-type well PW 2 in the peripheral circuit region 1 B.
  • an insulating film IF 1 for the gate insulating film is formed on the upper surface (surface) of the semiconductor substrate SB in the memory cell region 1 A and the peripheral circuit regions 1 B and 1 C.
  • the insulating film IF 1 for example, a silicon oxide film can be used.
  • the respective insulating films IF 1 in the memory cell region 1 A and the peripheral circuit regions 1 B and 1 C may be formed by using different processes from each other so as to have different film thicknesses. More preferably, the insulating film IF 1 in the peripheral circuit region 1 C is made thicker than the insulating film IF 1 in the memory cell region 1 A.
  • a silicon film PS 1 made of a polycrystal silicon film is formed on the semiconductor substrate SB by using, for example, a CVD (Chemical Vapor Deposition) method so as to cover the upper surface of the insulating film IF 1 .
  • the silicon film PS 1 can be formed as a low-resistance semiconductor film (a doped polysilicon film) by introducing an impurity at the time of film formation, by ion-implanting an impurity after the film formation, or by others.
  • phosphorus (P) can be preferably used as the n-type impurity to be introduced into the silicon film PS 1 .
  • an insulating film IF 2 is formed by using, for example, a CVD method.
  • the insulating film IF 2 is a cap insulating film made of, for example, silicon nitride (SiN).
  • the film thickness of the insulating film IF 2 can be set in a range of, for example, about 20 to 50 nm.
  • the stacked film, made of the insulating film IF 2 , the silicon film PS 1 and the insulating film IF 1 in the memory cell region 1 A, is patterned by using a photolithography technique and an etching technique.
  • a stacked body of a gate insulating film GIt made of the insulating film IF 1 , a control gate electrode CG made of the silicon film PS 1 and a cap insulating film made of the insulating film IF 2 is formed in the memory cell region 1 A.
  • the control gate electrode CG forms a pattern extending in a gate width direction.
  • the gate width direction corresponds to a depth direction of the drawing sheet of FIG. 3 .
  • the stacked film made of the insulating film IF 2 , the silicon film PS 1 and the insulating film IF 1 is processed also between the peripheral circuit regions 1 B and 1 C by using the photolithography technique and the etching technique.
  • the stacked bodies each made of the insulating film IF 2 , the silicon film PS 1 and the insulating film IF 1 are separated from one another, and is also separated from the stacked body made of the insulating film IF 2 , the silicon film PS 1 and the insulating film IF 1 in the memory cell region 1 A.
  • the insulating film IF 2 in the peripheral circuit region 1 B is selectively removed.
  • the upper surface of the silicon film PS 1 in the peripheral circuit region 1 B is exposed.
  • the insulating films IF 2 in the memory cell region 1 A and the peripheral circuit region 1 C are not removed but left.
  • the above-described wet-etching process is performed by using, as a mask, a resist film having a pattern that covers the memory cell region 1 A and the peripheral circuit region 1 C and exposes the peripheral circuit region 1 B although not shown, so that the resist film not shown is removed after the above-described wet etching process.
  • an insulating film ON for forming the above-described gate insulating film GIm is formed on the main surface of the semiconductor substrate SB.
  • the insulating film ON covers the upper surface of the semiconductor substrate SB in the memory cell region 1 A and the sidewalls and the upper surface of a stacked body made of the gate insulating film GIt, the control gate electrode CG and the insulating film IF 2 .
  • the insulating film ON is an insulating film having a charge storage portion therein. More specifically, the insulating film ON is made of a stacked film configured by a silicon oxide film OX 1 formed on the semiconductor substrate SB, a silicon nitride film NT formed on the silicon oxide film OX 1 and a silicon oxide film OX 2 formed on the silicon nitride film NT.
  • the silicon oxide films OX 1 and OX 2 can be formed by, for example, an oxidation treatment (thermal oxidation treatment), a CVD method, or a combination of them. Particularly, for forming the silicon oxide film OX 2 , an ISSG (In-Situ Steam Generation) oxidation treatment can be also used.
  • the silicon nitride film NT can be formed by, for example, a CVD method.
  • the memory cell is formed, and the silicon nitride film NT is formed as an insulating film (charge storage layer) having a trap level.
  • a silicon nitride film is preferable from the viewpoint of reliability or others.
  • the film is not limited to the silicon nitride film, and a high dielectric constant film (high dielectric constant insulating film) such as an aluminum oxide film (alumina), a hafnium oxide film, a tantalum oxide film having a dielectric constant higher than that of the silicon nitride film maybe used as the charge storage layer or the charge storage portion.
  • the thickness of the silicon oxide film OX 1 can be set in a range of, for example, about 2 to 10 nm
  • the thickness of the silicon nitride film NT can be set in a range of, for example, about 5 to 15 nm
  • the thickness of the silicon oxide film OX 2 can be set in a range of, for example, about 2 to 10 nm.
  • a polycrystal silicon film PS 2 is formed on the main surface of the semiconductor substrate SB so as to cover the surface of the insulating film ON by using, for example, a CVD method.
  • the upper surface of the insulating film ON in the memory cell region 1 A is covered with the silicon film PS 2 . That is, on the sidewalls of the control gate electrode CG, the silicon film PS 2 is formed via the insulating film ON.
  • the film thickness of the silicon film PS 2 is, for example, 40 nm. After the silicon film PS 2 is formed as an amorphous silicon film at the time of the film formation, this silicon film PS 2 can be changed to the silicon film PS 2 made of a polycrystal silicon film by a subsequent thermal treatment.
  • the silicon film PS 2 is a film to which, for example, a p-type impurity (for example, boron (B)) is introduced at a comparatively high concentration.
  • the silicon film PS 2 is a film for use in forming the memory gate electrode MG.
  • the film thickness described here means a thickness of the film in a direction perpendicular to the main surface of the semiconductor substrate SB.
  • FIG. 4 shows the insulating film ON having a stacked layer structure of three layers formed of the silicon oxide film OX 1 , the silicon nitride film NT and the silicon nitride film NT.
  • the illustration of the stacked layer structure of the insulating film ON is omitted in order to easily understand the drawing. That is, although the insulating film ON has the stacked layer structure, the insulating film ON is illustrated as a single film GIm in the drawings used for the following explanation.
  • the silicon film PS 2 is left in a sidewall shape via the insulating film ON on both of sidewalls of the stacked body made of the gate insulating film GIt, the control gate electrode CG and the insulating film IF 2 .
  • a memory gate electrode MG made of the sidewall-shaped silicon film PS 2 that is left via the insulating film ON is formed on one sidewall of the sidewalls of the above-described stacked body. Moreover, by the above-described etching back process, the upper surface of the insulating film ON in each of the peripheral circuit regions 1 B and 1 C is exposed.
  • a resist film (not shown) is formed on the semiconductor substrate SB so as to cover the memory gate electrode MG adjacent to one sidewall of the control gate electrode CG and so as to expose the silicon film PS 2 adjacent to the other sidewall of the control gate electrode CG. Then, by performing an etching process while using the resist film as an etching mask, the silicon film PS 2 formed on the opposite side of the memory gate electrode MG across the control gate electrode CG is removed. Then, the resist film is removed. In this etching process, the memory gate electrode MG is covered with the resist film, and therefore, is not etched but left.
  • a part of the insulating film ON is removed by etching (for example, wet etching).
  • etching for example, wet etching.
  • the insulating film ON right below the memory gate electrode MG is not removed but left.
  • the insulating film ON located between the memory gate electrode MG and the stacked body including the gate insulating film GIt, the control gate electrode CG and the insulating film IF 2 is not removed but left.
  • the upper surface of the semiconductor substrate SB and the upper surface of the insulating film IF 2 in the memory cell region 1 A are exposed, and the upper surface of the silicon film PS 1 in the peripheral circuit region 1 B and the upper surface of the insulating film IF 2 in the peripheral circuit region 1 C are further exposed.
  • the gate insulating film GIm made of the insulating film ON having the charge storage portion therein and the memory gate electrode MG on the gate insulating film GIm are formed on the semiconductor substrate SB so as to be adjacent to the control gate electrode CG.
  • an insulating film IF 3 is formed by using, for example, a CVD method.
  • the insulating film IF 3 is made of, for example, a silicon nitride film.
  • the silicon film PS 1 in the peripheral circuit region 1 B and the silicon film PS 1 and the insulating film IF 2 in the peripheral circuit region 1 C are covered with the insulating film IF 3 .
  • the stacked body made of the gate insulating film GIt in the memory cell region 1 A, the control gate electrode CG and the insulating film IF 2 , the gate insulating film GIm and the memory gate electrode MG adjacent to the sidewalls of the stacked body, and the main surface of the semiconductor substrate SB in the memory cell region 1 A are covered with the insulating film IF 3 .
  • the insulating film IF 3 may be formed as a stacked film of a silicon oxide film and a silicon nitride film on the silicon oxide film.
  • the peripheral circuit region 1 C is exposed, and a resist film PR 1 that covers the insulating films IF 3 in the memory cell region 1 A and the peripheral circuit region 1 C is formed.
  • a resist film PR 1 that covers the insulating films IF 3 in the memory cell region 1 A and the peripheral circuit region 1 C is formed.
  • each insulating film IF 3 adjacent to the upper surface and the sidewalls of the silicon film PS 1 is exposed from the resist film PR 1 .
  • the insulating film IF 3 exposed from the resist film PR 1 is removed by a wet etching method, and then, the resist film PR 1 is removed.
  • the silicon film PS 1 in the peripheral circuit region 1 B is exposed.
  • the main surface of the semiconductor substrate SB is exposed by removing the silicon film PS 1 and the insulating film IF 1 in the peripheral circuit region 1 B by using, for example, a wet etching method while using the insulating film IF 3 as a mask.
  • the stacked body configured by the gate insulating film GIt, the control gate electrode CG and the insulating film IF 2 , and the gate insulating film GIm in the memory cell region 1 A and the memory gate electrode MG that are adjacent to the sidewalls of the stacked body are covered with the insulating film IF 3 , and therefore, are not removed.
  • the insulating film IF 2 , the silicon film PS 1 and the insulating film IF 1 in the peripheral circuit region 1 C are covered with the insulating film IF 3 , and therefore, are not removed.
  • insulating films IF 4 and HK, a metal film TN, a silicon film PS 3 and an insulating film IF 5 are sequentially formed on the main surface of the semiconductor substrate SB.
  • the insulating film IF 4 is made of, for example, a silicon oxide film, and is formed by using an oxidizing method such as a thermal oxidizing method, and therefore, the insulating film IF 4 is formed only on the main surface of the semiconductor substrate SB in the peripheral circuit region 1 B.
  • the stacked body configured by the gate insulating film GIt, the control gate electrode CG and the insulating film IF 2 in the memory cell region 1 A, and the gate insulating film GIm and the memory gate electrode MG that are adjacent to the sidewalls of the stacked body are also covered with the insulating films IF 3 and HK, the metal film TN, the silicon film PS 3 and the insulating film IF 5 .
  • the stacked body configured by the insulating film IF 1 , the silicon film PS 1 and the insulating film IF 2 in the peripheral circuit region 1 C are also covered with the insulating films IF 3 and HK, the metal film TN, the silicon film PS 3 and the insulating film IF 5 .
  • the insulating film HK is an insulating film for the gate insulating film. More specifically, the insulating film IF 4 and the insulating film HK are films that configure the gate insulating film of the MISFET (Q 1 ) to be formed later in the peripheral circuit region 1 B.
  • the insulating film HK is an insulating film having a dielectric constant (relative dielectric constant) higher than those of silicon oxide and silicon nitride, that is so called high-k film (high dielectric constant film).
  • a metal oxide film such as a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film, a lanthanum oxide film or others, can be used, and these metal oxide films can further contain either one or both of nitrogen (N) and silicon (Si).
  • the insulating film HK can be formed by, for example, an ALD (Atomic Layer Deposition) method or others.
  • the film thickness of the insulating film HK is, for example, 1.5 nm.
  • the physical film thickness of the gate insulating film can be larger than the case of the usage of the silicon oxide film, and therefore, the case can obtain such an advantage as reducing a leak current.
  • the metal film TN is made of, for example, a titanium nitride film, and can be formed by using, for example, a sputtering method.
  • the silicon film PS 3 is made of a polysilicon film, and can be formed by using, for example, a CVD method.
  • the film thickness of the silicon film PS 3 is, for example, 40 nm.
  • this silicon film PS 3 made of the amorphous silicon film can be also changed to the silicon film PS 3 made of a polycrystal silicon film by a subsequent thermal treatment.
  • the silicon film PS 3 is a film for use in forming a dummy gate electrode DG described later.
  • the insulating film IF 5 is a cap insulating film made of, for example, silicon nitride, and can be formed by using, for example, a CVD method.
  • insulating films IF 4 and HK, a metal film TN, a silicon film PS 3 and an insulating film IF 5 are selectively left in the peripheral circuit region 1 B. And, the insulating film IF 4 and HK, the metal film TN, the silicon film PS 3 and the insulating film IF 5 are removed from the memory cell region 1 A and the peripheral circuit region 1 C by, for example, a wet etching method.
  • the wet etching method is performed by selectively covering an upper surface of a stacked body configured by the insulating films IF 4 and HK, a metal film TN, a silicon film PS 3 and an insulating film IF 5 in the peripheral circuit region 1 B with an insulating film such as a silicon oxide film, and then, by using this insulating film as a mask.
  • the dummy gate electrode DG made of the silicon film PS 3 , the metal film TN and a gate insulating film GIL made of the insulating films HK and IF 4 , which configure the MISFET (Q 1 ) are formed.
  • a gate electrode G 2 and a gate insulating film GIH which configure the MISFET (Q 2 ), are formed.
  • the insulating film IF 5 in the peripheral circuit region 1 B and the insulating film IF 2 in the peripheral circuit region 1 C are patterned by a photolithography technique and an etching method.
  • the silicon film PS 3 , the metal film TN, and the insulating films HK, IF 4 and IF 1 are patterned by the etching process while using the patterned insulating film IF 5 as a hard mask, so that the gate insulating film GIL configured by the dummy gate electrode DG, the metal film TN and the insulating films HK and IF 4 is formed.
  • the silicon film PS 1 and the insulating film IF 4 are patterned by the etching process while using the patterned insulating film IF 2 as a hard mask, so that the gate electrode G 2 and the gate insulating film GIH are formed.
  • a plurality of extension regions (n ⁇ -type semiconductor regions, impurity diffusion regions) EX are formed by using an ion implantation method or others. That is, in the active region, while an n-type impurity such as arsenic (As) or phosphorus (P) is introduced into the surface of the semiconductor substrate SB, no impurity is introduced into the lower portions of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG and the gate electrode G 2 . That is, in the active region, the extension regions EX are formed on both sides of the control gate electrode CG and memory gate electrode MG, both sides of the dummy gate electrode DG and both sides of the gate electrode G 2 .
  • an n-type impurity such as arsenic (As) or phosphorus (P)
  • an offset spacer that covers each of the sidewalls of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG and the gate electrode G 2 may be formed of, for example, a silicon nitride film, a silicon oxide film or a stacked film of these films.
  • each of the memory cell region 1 A and the peripheral circuit regions 1 B and 1 C can be formed by the same ion implantation method as each other. However, they can be also formed by using a different ion implantation process. Although its illustration is omitted, note that, before or after the formation process of the extension regions EX, for example, a halo region may be formed on the main surface of the semiconductor substrate SB in the peripheral circuit region 1 B by implanting a p-type impurity (for example, boron (B)) while using the insulating film IF 5 and the dummy gate electrode DG as a mask. The halo region is closer to the center of the dummy gate electrode DG than the extension regions EX.
  • a p-type impurity for example, boron (B)
  • the halo region is formed at a portion close to the channel region of the low breakdown voltage MISFET (Q 1 ) formed in the peripheral circuit region 1 B.
  • the halo region may be formed at a portion close to the channel region of the high breakdown voltage MISFET (Q 2 ).
  • sidewalls SW made of an insulating film covering the sidewalls on both sides of the above-described structure including the control gate electrode CG and the memory gate electrode MG in the memory cell region 1 A are formed. Moreover, by this process, sidewalls SW covering the sidewalls on both sides of the stacked body configured by the gate insulating film GIL, the metal film TN, the dummy gate electrode DG and the insulating film IF 5 are formed in the peripheral circuit region 1 B. Furthermore, by this process, sidewalls SW covering the sidewalls on both sides of the stacked body configured by the gate insulating film GIH, the gate electrode G 2 and the insulating film IF 2 are formed in the peripheral circuit region 1 C.
  • the sidewalls SW after sequentially forming, for example, a silicon oxide film and a silicon nitride film on the semiconductor substrate SB by using a CVD method or others, a part of the silicon oxide film and the silicon nitride film is removed by an anisotropic etching process so that the upper surface of the semiconductor substrate SB and the upper surfaces of the insulating films IF 2 and IF 5 are exposed.
  • the sidewalls SW can be selectively formed on the sidewalls of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG and the gate electrode G 2 . While it is considered that the sidewalls SW are formed of a stacked film, the drawings do not show an interface between the films configuring the stacked film.
  • the sidewalls SW may be formed of, for example, a single layer film such as a silicon oxide film or a silicon nitride film.
  • diffusion regions (n + -type semiconductor regions, impurity diffusion regions) DF are formed in the memory cell region 1 A and the peripheral circuit regions 1 B and 1 C by using an ion implantation method or others. That is, while an n-type impurity such as arsenic (As) or phosphorus (P) is introduced into the surface of the semiconductor substrate SB in the active region, no impurity is introduced into the lower portions of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG, the gate electrode G 2 and the sidewalls SW.
  • n-type impurity such as arsenic (As) or phosphorus (P)
  • the diffusion regions DF are formed on both sides of the control gate electrode CG and memory gate electrode MG, both sides of the dummy gate electrode DG and both sides of the gate electrode G 2 , and besides, formed outside each sidewall SW.
  • the diffusion region DF has a higher impurity concentration and a larger junction depth than those of the extension region EX.
  • the source region and the drain region having an LDD structure configured by the extension region EX and a diffusion region DF having an impurity concentration higher than that of the extension region EX are formed.
  • the extension region EX and the diffusion region DF formed on the upper surface of the semiconductor substrate SB so as to sandwich the control gate electrode CG and the memory gate electrode MG configure the source region and the drain region of the memory cell MC.
  • the extension region EX and the diffusion region DF formed on the upper surface of the semiconductor substrate SB so as to sandwich the dummy gate electrode DG configure the source region and the drain region of the low breakdown voltage MISFET (Q 1 ).
  • the extension region EX and the diffusion region DF formed on the upper surface of the semiconductor substrate SB so as to sandwich the gate electrode G 2 configure the source region and the drain region of the high breakdown voltage MISFET (Q 2 ).
  • the diffusion region DF formed in each of the memory cell region 1 A and the peripheral circuit regions 1 B and 1 C can be formed by the same ion implantation process as each other. However, these diffusion regions DF can be also formed by using different ion implantation processes from each other.
  • an activation annealing process which is a thermal treatment for activating the impurity introduced into the semiconductor region (extension region EX and diffusion region DF) for the source and drain or others, is performed.
  • a silicide layer is formed by performing a so-called salicide (Salicide: Self-Aligned Silicide) process which is explained with reference to FIGS. 12 and 13 . More specifically, the silicide layer can be formed as follows.
  • a metal film MF 1 for use in forming a silicide layer is formed (deposited) on the main surface of the semiconductor substrate SB including the upper surface of the diffusion region DF and the upper surface of the memory gate electrode MG.
  • the film thickness of the metal film MF 1 is set to, for example, 20 to 25 nm.
  • the metal film MF 1 can be formed by a sputtering method using, for example, an alloy target formed by adding platinum (Pt) to nickel (Ni).
  • the content (concentration) of platinum (Pt) that is an additive to the alloy target is set to 5% or more (more preferably, 5% or more and 10% or less).
  • the additive may be aluminum (Al), carbon (C) or others.
  • the content (concentration) in this case is also set to 5% or more (more preferably, 5% or more and 10% or less).
  • platinum has higher heat resistance than that of aluminum, carbon or others, and therefore, can be preferably used for the alloy film.
  • the metal film MF 1 formed by the sputtering method using the alloy target is a nickel (Ni) film containing platinum (Pt), and the content of platinum (Pt) is 5% or more.
  • Ni nickel serving as a main material
  • platinum (Pt) serving as an additive is referred to as second metal.
  • This first thermal treatment is a thermal treatment for allowing the metal film MF 1 to react with silicon of the diffusion region DF and the memory gate electrode.
  • a silicide layer in which NiSi fine crystals and Ni 2 Si are dominant is formed on the respective upper portions of the diffusion region DF and the memory gate electrode MG.
  • the silicide layer is a silicide layer having comparatively high resistance which is different from the silicide layer S 1 shown in FIG. 1 .
  • the platinum (Pt) serving as the additive has a small content, no platinum silicide is formed, so that the crystals of the silicide layer and the silicide layer S 1 to be explained later are described as NiSi and Ni 2 Si so as not to contain Pt.
  • the unreacted portion of the metal film MF 1 with silicon is removed by wet etching or others, and then, second thermal treatment is performed onto the semiconductor substrate SB.
  • the second thermal treatment is executed in order to promote the crystal growth of the silicide layer having comparatively high resistance to form the silicide layer S 1 having comparatively low resistance in which NiSi is dominant.
  • the temperature of the second thermal treatment is higher than the temperature of the first thermal treatment.
  • the silicide layer S 1 made of NiSi is formed.
  • a thermal treatment apparatus for heating the semiconductor substrate SB by using a carbon heater is used.
  • the silicide layer having comparatively high resistance is formed by, for example, the heating at a temperature of about 260° C. for 30 to 60 seconds.
  • the second thermal treatment is further performed at 600° C. for 10 to 30 seconds, so that the silicide layer S 1 having the reduced resistance is grown.
  • the thermal treatments as described above, such abnormal growth of the silicide layer S 1 as extending inside the semiconductor substrate SB can be prevented.
  • the abnormal growth of the silicide layer S 1 can be suppressed by using nickel (Ni) metal containing platinum (Pt), so that a leak current in the diffusion region DF (in other words, the source region or the drain region) can be reduced.
  • Ni nickel
  • Pt platinum
  • the second thermal treatment is performed at, for example, a temperature of 450° C. or higher and 600° C. or lower. In the present embodiment, as described above, the second thermal treatment is performed at 600° C. Note that the second thermal treatment may be performed by using a laser, microwaves or a flash lamp.
  • the silicide layer S 1 formed by the thermal treatment has a comparatively high tensile stress.
  • this tensile stress to the memory cell MC and channels of the low breakdown voltage MISFET (Q 1 ) and the high breakdown voltage MISFET (Q 2 )
  • the mobility of electrons or positive holes is improved, so that the memory cell MC, the low breakdown voltage MISFET (Q 1 ) and the high breakdown voltage MISFET (Q 2 ) can be operated at a high speed.
  • the upper surfaces of the control gate electrode CG and the gate electrode G 2 are covered with the insulating film IF 2
  • the upper surface of the dummy gate electrode DG is covered with the insulating film IF 5 , and therefore, no silicide layer S 1 is formed on the upper portions of the control gate CG, the gate electrode G 2 and the dummy gate electrode DG. Since the upper portion of the sidewall-shaped memory gate electrode MG is exposed, the silicide layer S 1 is formed on the exposed portion. However, this silicide layer S 1 is completely removed by a polishing process based on a CMP (Chemical Mechanical Polishing) method to be performed in a later process.
  • CMP Chemical Mechanical Polishing
  • an insulating film (liner insulating film) IF 7 and an interlayer insulating film IL 1 are subsequently formed so as to cover the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG, the gate electrode G 2 and the sidewalls SW.
  • the insulating film IF 7 is made of, for example, a silicon nitride film, and can be formed by, for example, a CVD method.
  • the insulating film IF 7 can be used as an etching stopper film when a contact hole is formed in a later process.
  • the interlayer insulating film IL 1 is made of, for example, a single film of a silicon oxide film, and can be formed by, for example, a CVD method or others.
  • the interlayer insulating film IL 1 is formed with, for example, a film thickness larger than the film thickness of the control gate electrode CG.
  • the upper surface of the interlayer insulating film IL 1 is polished by using a CMP method or others. In this manner, the upper surface of each of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG, and the gate electrode G 2 is exposed. That is, in this polishing process, the interlayer insulating film IL 1 and the insulating film IF 7 are polished until the upper surface of each of the control gate electrode CG, the memory gate electrode MG, the dummy gate electrode DG, and the gate electrode G 2 is exposed. In this manner, the insulating films IF 2 and IF 5 are removed, and the upper portion of each of the sidewall SW and the gate insulating film GIm is partially removed.
  • the silicide layer 51 on the memory gate electrode MG is removed together with a part of the upper portion of the memory gate electrode MG.
  • the gate insulating film GIm and the sidewalls SW or others, located between the control gate electrode CG and the memory gate electrode MG, are polished all together, the heights of the gate insulating film GIm and the sidewalls SW are almost equal to the height of the control gate electrode CG or the memory gate electrode MG.
  • the insulating film IF 8 is processed by using a photolithography technique and an etching method.
  • the insulating film IF 8 covers the memory cell region 1 A and the peripheral circuit region 1 C, and exposes the dummy gate electrode DG in the peripheral circuit region 1 B. That is, the insulating film IF 8 covers the upper surfaces of the control gate electrode CG, the memory gate electrode MG, and the gate electrode G 2 , and exposes the upper surface of the dummy gate electrode DG.
  • the insulating film IF 8 is made of, for example, a silicon oxide film.
  • the dummy gate electrode DG is removed by a wet etching method.
  • the dummy gate electrode DG is removed by the wet etching process using, for example, alkaline aqueous solution while using the insulating film IF 8 as a mask for protecting the control gate electrode CG, the memory gate electrode MG and the gate electrode G 2 .
  • alkaline aqueous solution for example, ammonia hydrogen peroxide mixture (NH 4 OH+H 2 O 2 +H 2 O) is used.
  • a trench concave portion, hollow portion
  • the trench on the metal film TN in the peripheral circuit region 1 B is a region from which the dummy gate electrode DG is removed, and the sidewalls on both sides of the trench are formed of the sidewalls SW.
  • a metal film is formed as a conductive film for the gate electrode on the semiconductor substrate SB, that is, on the interlayer insulating film IL 1 including the upper portion of the inner surface (bottom surface and sidewalls) of the above-described trench so as to completely bury the trench.
  • the metal film is considered to have, for example, a stacked structure of two or more metal films. However, in the drawing, the illustration of the border between the two or more metal films is omitted, and the metal film is shown as a single film.
  • the metal film is also formed on the interlayer insulating film IL 1 .
  • the metal film for example, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium carbide (TiC) film, a tantalum carbide (TaC) film, a tungsten carbide (WC) film, a tantalum carbide nitride (TaCN) film, a titanium (Ti) film, a tantalum (Ta) film, a titanium aluminum (TiAl) film, an aluminum (Al) film, or others can be used.
  • TiN titanium nitride
  • TaN tantalum nitride
  • WN tungsten nitride
  • TiC titanium carbide
  • TaC tantalum carbide
  • WC tungsten carbide
  • TaCN tantalum carbide nitride
  • Ti titanium
  • metal film means a conductive film exhibiting metallic conduction, and includes not only a single metal film (pure metal film) or an alloy film, but also a metallic compound film exhibiting the metallic conduction.
  • the metal film can be formed by using, for example, a sputtering method or others.
  • the metal film can be formed of, for example, a stacked film of a titanium nitride (TiN) film and an aluminum (Al) film on the titanium nitride film.
  • TiN titanium nitride
  • Al aluminum
  • the aluminum film thicker than the titanium nitride film. Since the aluminum film has low resistance, the resistance of the gate electrode G 1 to be formed later can be reduced.
  • the gate electrode G 1 of the low breakdown voltage MISFET (Q 1 ) in the peripheral circuit region 1 B is formed.
  • the entire gate electrode G 1 is made of a metal film, and therefore, there is no problem for, for example, a depleted gate electrode as observed in the case of the usage of the polysilicon film.
  • the gate electrode of the p-type low breakdown voltage MISFET in the peripheral circuit region 1 B can be formed by burying a metal film different from that of the gate electrode G 1 of the low breakdown voltage MISFET (Q 1 ), by repeating the same processes as described above.
  • control gate electrode CG, the memory gate electrode MG and the gate electrode are exposed as shown in FIG. 17 .
  • a silicide layer is formed on each of the electrodes made of a polysilicon film by performing the salicide process. More specifically, the silicide layer can be formed as follows.
  • the pattern of an insulating film IF 9 that covers the peripheral circuit region 1 B is formed by using, for example, a CVD method, a photolithography technique and an etching technique.
  • the insulating film IF 9 is an insulating film which exposes the upper surfaces of the control gate electrode CG and the memory gate electrode MG in the memory cell region 1 A and the gate electrode G 2 in the peripheral circuit region 1 C and which covers the gate electrode G 1 in the peripheral circuit region 1 B, and is made of, for example, a silicon oxide film or others.
  • each excessive silicon oxide film or others on the control gate electrode CG, on the memory gate electrode MG, and on the gate electrode G 2 is removed so as to expose each surface of the control gate electrode CG, the memory gate electrode MG, and the gate electrode G 2 .
  • a metal film MF 2 for use in forming a silicide layer is formed (deposited) on the main surface of the semiconductor substrate SB including the upper surface of the memory gate electrode MG and the upper surface of the gate electrode G 2 .
  • the film thickness of the metal film MF 2 is set to, for example, 20 to 25 nm.
  • the metal film MF 2 can be formed by a sputtering method using, for example, an alloy target formed by adding platinum (Pt) to nickel (Ni).
  • the content (concentration) of platinum (Pt) that is an additive to the alloy target is set to less than 5%.
  • the additive may be aluminum (Al), carbon (C) or others.
  • the content (concentration) in this case is also set to less than 5%.
  • platinum has higher heat resistance than that of aluminum, carbon or others, and therefore, can be preferably used for the alloy film.
  • the metal film MF 2 formed by the sputtering method using the alloy target is a nickel (Ni) film containing platinum (Pt), and the content of platinum (Pt) is less than 5%.
  • nickel serving as a main material is referred to as first metal
  • platinum (Pt) serving as an additive is referred to as second metal.
  • third thermal treatment in order to be distinguished from the above-described first and second thermal treatments
  • This third thermal treatment is a thermal treatment for allowing the metal film MF 2 to react with silicon of the control gate electrode CG, the memory gate electrode MG, and the gate electrode G 2 .
  • a silicide layer in which NiSi fine crystals and Ni 2 Si are dominant is formed on the respective upper portions of the control gate electrode CG, the memory gate electrode MG, and the gate electrode G 2 .
  • the silicide layer is a silicide layer having comparatively high resistance which is different from the silicide layer S 2 shown in FIG. 1 .
  • the platinum (Pt) serving as the additive has a small content as described above, no platinum silicide is formed, so that the crystals of the silicide layer comparatively high resistance and the silicide layer S 2 to be explained later are described as NiSi and Ni 2 Si so as not to contain Pt.
  • the unreacted portion of the metal film MF 2 with silicon is removed by wet etching or others, and then, fourth thermal treatment is performed onto the semiconductor substrate SB.
  • the fourth thermal treatment is executed in order to promote the crystal growth of the silicide layer having comparatively high resistance to form the silicide layer S 2 having sufficiently reduced resistance in which NiSi is dominant.
  • the temperature of the fourth thermal treatment is higher than the temperature of the third thermal treatment.
  • the silicide layer S 2 made of NiSi is formed.
  • the silicide layer S 2 is selectively formed on the upper surfaces of the control gate electrode CG, the memory gate electrode MG and the gate electrode G 2 .
  • a thermal treatment apparatus for heating the semiconductor substrate by using a carbon heater is used. That is, in the fourth thermal treatment, the silicide layer S 2 containing NiSi fine crystals and Ni 2 Si is formed by, for example, the heating at a temperature of about 260° C. for 10 to 30 seconds. Then, after the unreacted part of the metal film MF 2 is removed by wet etching or others as described above, the fourth thermal treatment is further performed at 400° C. for 30 to 60 seconds, so that the NiSi crystals inside the silicide layer S 2 is grown.
  • the silicide layer S 2 formed in this manner is made of, for example, nickel silicide (NiSi) containing platinum.
  • the layer is not always required to contain platinum (Pt).
  • the third thermal treatment can be executed at a lower temperature, so that the short circuit between the silicide layers S 2 formed on the surfaces (upper surfaces) of the control gate electrode CG and the memory gate electrode MG can be prevented.
  • the upper surface of the control gate electrode CG, the upper surface of the memory gate electrode MG and the ends of the gate insulating film GIm have almost the same height as one another, and the silicide layer S 2 is formed on the upper surface of the control gate electrode CG and the upper surface of the memory gate electrode MG.
  • the silicide layer S 2 on the upper surface of the control gate electrode CG and the silicide layer S 2 on the upper surface of the memory gate electrode MG are configured to easily cause the short circuit therebetween.
  • platinum (Pt) is contained in the silicide layer S 2 , this configuration has such effect as preventing the above-described short circuit.
  • the temperature of the above-described third thermal treatment needs to be set to about 400° C.
  • the third thermal treatment is performed at such a high temperature, a problem of the short circuit between the control gate electrode CG and the memory gate electrode MG through the silicide layer is caused.
  • the above-described fourth thermal treatment is performed at, for example, a temperature of 400° C. or less.
  • each of the silicide layers S 2 formed on the surfaces (upper surfaces) of the control gate electrode CG, the memory gate electrode MG and the gate electrode G 2 can be formed as, for example, a film having tensile stress lower than that of the silicide layer S 1 formed on the surface of the diffusion region DF, and therefore, the silicide layer S 2 has such features as being difficult to disconnect and as having a small sheet resistance.
  • an interlayer insulating film and a plurality of contact plugs are formed.
  • an interlayer insulating film IL 2 that covers the upper surface of the semiconductor substrate SB including the memory cell region 1 A and the peripheral circuit regions 1 B and 1 C is formed by using, for example, a CVD method.
  • the interlayer insulating film IL 2 is made of, for example, a silicon oxide film, and covers the respective upper surfaces of the control gate electrode CG, the memory gate electrode MG, the gate electrodes G 1 and G 2 , and the interlayer insulating film IL 1 .
  • the insulating film IF 9 formed at the time of the formation of the silicide layer S 2 is left. If needed, the insulating film IF 9 may be removed before the formation of the interlayer insulating film IL 2 .
  • the interlayer insulating films IL 2 and IL 1 and the insulating films IF 9 and IF 7 are dry-etched while using the resist film (not shown) formed on the interlayer insulating film IL 2 as an etching mask.
  • a plurality of contact holes (openings, through holes) that penetrate the interlayer insulating film IL 2 and a plurality of contact holes that penetrate the interlayer insulating films IL 1 and IL 2 and the insulating film IF 7 are formed. Note that the contact holes in the peripheral circuit region 1 B penetrate the insulating film IF 9 .
  • a part of the main surface of the semiconductor substrate SB such as a part of the silicide layer S 1 on the surface of the diffusion region DF, a part of the silicide layer S 2 on the surface of the control gate electrode CG, a part of the silicide layer S 2 on the surface of the memory gate electrode MG or a part of the gate electrodes G 1 and G 2 are exposed.
  • the contact holes on the respective gate electrodes are formed in regions not shown in FIG. 20 .
  • conductive contact plugs CP made of tungsten (W) or others are formed as conductors for connection.
  • a barrier conductor film for example, titanium film, titanium nitride film or stacked film of them
  • a main conductor film made of a tungsten film or others is formed on this barrier conductor film so as to completely fill the inside of the respective contact holes, and then, the unnecessary main conductor film and barrier conductor film outside each contact hole are removed by using a CMP method, an etching back method or others, so that the contact plugs CP can be formed.
  • FIG. 20 shows the barrier conductor film and the main conductor film (tungsten film) configuring the contact plug CP so as to be integrated.
  • the contact plug CP filled inside the contact hole is formed so as to be respectively connected to each upper portion of the diffusion region DF, the control gate electrode CG, the memory gate electrode MG, and the gate electrode G 1 or the gate electrode G 2 .
  • the contact plug CP is connected to the upper surface of each of the diffusion regions DF of the memory cell MC, the low breakdown voltage MISFET (Q 1 ) and the high breakdown voltage MISFET (Q 2 ), via the silicide layer S 1 .
  • the contact plug CP is connected to the upper surface of each of the control gate electrode CG, the memory gate electrode MG and the gate electrode G 2 , via the silicide layer S 2 .
  • a first wiring layer M 1 including a first-layer wiring is formed on the interlayer insulating film IL 2 into which the contact plug CP is buried.
  • a plurality of first-layer wirings are connected to the respective upper surfaces of the contact plugs CP shown in FIG. 1 .
  • a second wiring layer, a third wiring layer or others are subsequently formed on the first wiring layer to form a stacked wiring layer, and then, the semiconductor wafer is divided into individual pieces by a dicing process, so that a plurality of semiconductor chips are obtained.
  • the semiconductor device of the present embodiment is manufactured.
  • diffusion regions DF configuring a source region and a drain region are formed so as to sandwich a gate electrode G 2 therebetween, and next, a silicide layer S 1 is formed on the surfaces of the diffusion regions DF while the gate electrode G 2 is covered with an insulating film IF 2 . Then, the insulating film IF 2 on the gate electrode G 2 is removed, and a silicide layer S 2 is formed on the surface (upper surface) of the exposed gate electrode G 2 .
  • the silicide layers S 1 and S 2 are formed of a first metal (for example, nickel) and silicon, and contain a second metal (for example, platinum) as an additive.
  • the additive concentration of the silicide layer S 2 can be made lower than the additive concentration of the silicide layer S 1 . That is, a leak current in the source region or the drain region of the MISFET (Q 2 ) can be reduced, and the sheet resistance of the silicide layer S 2 on the gate electrode G 2 can also be reduced.
  • the fourth thermal treatment temperature for forming the silicide layer S 2 to a temperature lower than the second thermal treatment temperature for forming the silicide layer S 1 , the tensile stress exerted inside the silicide layer S 2 can be reduced, so that the prevention of the disconnection of the gate electrode G 2 and the reduction of the resistance can be achieved.
  • the above-described semiconductor device further has the MISFET (Q 1 ) having the metal gate electrode G 1 .
  • the MISFET (Q 2 ) diffusion regions DF forming the source region and the drain region are formed on both ends of the dummy electrode DG, and next, the silicide layer S 1 is formed on the surface of the diffusion regions D while the dummy gate electrode DG is covered with the insulating film IF 5 .
  • the insulating film IF 5 on the dummy gate electrode DG is removed, the dummy gate electrode DG is removed, and the metal gate electrode G 1 is formed.
  • the process for forming the silicide layer S 1 of the MISFET (Q 2 ) is performed by the same process as the process for forming the silicide layer S 1 of the MISFET (Q 1 ). Furthermore, the process for removing the insulating film IF 2 on the gate electrode G 2 of the MISFET (Q 2 ) is performed by the same process as the process for removing the insulating film IF 5 on the dummy gate electrode DG. That is, by utilizing (sharing) the process for forming the MISFET (Q 1 ) having the metal gate electrode G 1 , the silicide layers S 1 and S 2 of the MISFET (Q 2 ) are formed by different processes.
  • the diffusion regions DF for forming the source region and the drain region are formed so as to sandwich the control gate electrode CG and the memory gate MG, and next, a silicide layer S 1 is formed on the surfaces of the memory gate electrode MG and the diffusion layers DF while the control gate electrode CG is covered with the insulating film IF 2 . Then, by removing the insulating film IF 2 on the control gate electrode CG and the silicide layer S 1 on the memory gate electrode MG, a silicide layer S 2 is formed on the surfaces (upper surfaces) of the exposed control gate electrode CG and memory gate electrode MG.
  • the silicide layers S 1 and S 2 are formed of a first metal (for example, nickel) and silicon, and contain a second metal (for example, platinum) as an additive.
  • the additive concentration of the silicide layer S 2 can be made lower than the additive concentration of the silicide layer S 1 . That is, a leak current in the source region or the drain region of the nonvolatile memory cell can be reduced, the sheet resistance of the silicide layer S 2 on each of the control gate electrode CG and on the memory gate electrode MG can also be reduced, and the high-speed operation of the semiconductor device having the nonvolatile memory cell MC can be achieved.
  • the fourth thermal treatment temperature for forming the silicide layer S 2 to a temperature lower than the second thermal treatment temperature for forming the silicide layer S 1 , the tensile stress exerted inside the silicide layer S 2 can be reduced, so that the prevention of the disconnection of the control gate electrode CG and the memory gate electrode MG and the reduction of the resistance can be achieved.
  • the third thermal treatment temperature can be lower than that in the usage of the nickel film not containing platinum, the short circuit between the silicide layer S 2 on the control gate electrode CG and the silicide layer S 2 on the memory gate electrode MG can be prevented.
  • the silicide layer S 1 is formed by performing the above-described first and second thermal treatments on the semiconductor substrate SB.
  • a metal film MF 3 is formed by a sputtering method or a CVD method using a nickel (Ni) target not containing platinum (Pt)
  • platinum (Pt) is introduced into the metal film MF 3 by using an ion implantation method.
  • the silicide layer S 1 can be formed.
  • the content (concentration) of platinum (Pt) contained in the silicide layer S 1 is set to 5% or more (more preferably, 5% or more and 10% or less).
  • the silicide layer S 2 in the formation of the silicide layer S 2 , as similar to the above description, after a metal film MF 4 is formed by a sputtering method or a CVD method using a nickel (Ni) target not containing platinum (Pt), platinum (Pt) may be introduced into the metal film MF 4 by using an ion implantation method. Then, by performing the above-described third and fourth thermal treatments on the metal film MF 4 to which platinum (Pt) has been introduced, the silicide layer S 2 can be formed. Of course, the content (concentration) of platinum (Pt) contained in the silicide layer S 2 is set to less than 5%.
  • both of the silicide layer S 1 and the silicide layer S 2 may not be formed by using the method of the first modified example.
  • one of them may be formed by using the method of the first modified example, and the other may be formed by using the method of the first embodiment.
  • the above-described first and second thermal treatments are performed, so that the silicide layer S 1 is formed.
  • platinum (Pt) is introduced into the silicide layer S 1 by using the ion implantation method. That is, a silicide layer (referred to as “sub-silicide layer”) not containing platinum (Pt) is formed by the above-described first and second thermal treatments, and platinum (Pt) is ion implanted into the sub-silicide layer, so that a silicide layer S 1 containing platinum (Pt) is formed.
  • the content (concentration) of platinum (Pt) contained in the silicide layer S 1 is set to 5% or more (more preferably, 5% or more and 10% or less).
  • platinum (Pt) is introduced into the silicide layer S 2 by using the ion implantation method. That is, a sub-silicide layer not containing platinum (Pt) is formed by the above-described third and fourth thermal treatments, and platinum (Pt) is ion implanted into the sub-silicide layer, so that a silicide layer S 2 containing platinum (Pt) is formed.
  • the content (concentration) of platinum (Pt) contained in the silicide layer S 2 is set to less than 5%.
  • the abnormal growth of the silicide layer relative to a thermal load after the formation of the silicide layer S 1 can be suppressed, and so that the leak current in the source region and the drain region can be reduced.
  • both of the silicide layer S 1 and the silicide layer S 2 may not be formed by using the method of the second modified example.
  • one of them may be formed by using the method of the second modified example, and the other may be formed by using the method of the first embodiment or the first modified example.
  • the memory cell in this case has: a source region and a drain region formed inside a semiconductor substrate; a gate electrode; and a stacked film which is formed between the semiconductor substrate and the gate electrode and which includes a silicon oxide film OX 1 , a silicon nitride film NT formed on the silicon oxide film OX 1 and a silicon oxide film OX 2 formed on the silicon nitride film NT.
  • the above-described silicide layer S 1 is formed on the surfaces of the source region and the drain region, and the silicide layer S 2 is formed on the gate electrode, and the content (concentration) of an additive (for example, platinum) contained in the silicide layer S 2 is set to be lower than the content (concentration) of an additive (for example, platinum) contained in the silicide layer S 1 .
  • nickel (Ni) is exemplified as the first metal.
  • titanium (Ti) or cobalt can be also used.
  • platinum (Pt) is exemplified as the second metal.
  • tantalum (Ta), palladium (Pd), aluminum (Al), manganese (Mn) or tungsten (W) can be also used.
  • the first MISFET includes: a first gate insulating film formed on the semiconductor substrate in the first region; a first gate electrode formed on the first gate insulating film; first impurity regions which are formed inside the semiconductor substrate so as to sandwich the first gate electrode in the first region and which configure a part of a first source region and a part of a first drain region; a first silicide layer which is formed on the first impurity region and which contains a first metal and silicon; and a second silicide layer which is formed in an upper portion of the first gate electrode and which contains the first metal and silicon.
  • a second metal different from the first metal is added into the first silicide layer, and a concentration of the second metal inside the second silicide layer is lower than a concentration of the second metal inside the first silicide layer.

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180006048A1 (en) * 2013-02-12 2018-01-04 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US10062705B1 (en) * 2017-04-13 2018-08-28 United Microelectronics Corp. Method of manufacturing a flash memory
KR20190006142A (ko) * 2017-07-07 2019-01-17 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
US20190027484A1 (en) * 2017-07-19 2019-01-24 Cypress Semiconductor Corporation Embedded non-volatile memory device and fabrication method of the same
US20210328035A1 (en) * 2020-04-16 2021-10-21 Samsung Electronics Co., Ltd. Semiconductor devices
US11183510B2 (en) 2016-12-22 2021-11-23 Renesas Electronics Corporation Manufacturing method of semiconductor device and semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI704675B (zh) 2016-10-31 2020-09-11 新加坡商馬維爾亞洲私人有限公司 製造具有優化的柵極氧化物厚度的記憶體器件
US10242996B2 (en) * 2017-07-19 2019-03-26 Cypress Semiconductor Corporation Method of forming high-voltage transistor with thin gate poly
US11637046B2 (en) * 2021-02-23 2023-04-25 Taiwan Semiconductor Manufacturing Company Limited Semiconductor memory device having composite dielectric film structure and methods of forming the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090081836A1 (en) * 2007-09-24 2009-03-26 International Business Machines Corporation Method of forming cmos with si:c source/drain by laser melting and recrystallization
US20090243002A1 (en) * 2008-03-28 2009-10-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20100075481A1 (en) * 2008-07-08 2010-03-25 Xiao (Charles) Yang Method and structure of monolithically integrated ic-mems oscillator using ic foundry-compatible processes
US20120292708A1 (en) * 2011-05-20 2012-11-22 Broadcom Corporation Combined Substrate High-K Metal Gate Device and Oxide-Polysilicon Gate Device, and Process of Fabricating Same
US20140022784A1 (en) * 2011-04-04 2014-01-23 Ceram Tec Gmbh Led lamp comprising an led as the luminaire and a glass or plastic lampshade

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006129637A1 (ja) * 2005-06-01 2006-12-07 Nec Corporation 半導体装置
JP2007335834A (ja) 2006-05-15 2007-12-27 Toshiba Corp 半導体装置およびその製造方法
JP5420345B2 (ja) * 2009-08-14 2014-02-19 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5663278B2 (ja) * 2010-11-19 2015-02-04 ルネサスエレクトロニクス株式会社 半導体装置
JP5847537B2 (ja) 2011-10-28 2016-01-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US8466058B2 (en) * 2011-11-14 2013-06-18 Intermolecular, Inc. Process to remove Ni and Pt residues for NiPtSi applications using chlorine gas
US9059096B2 (en) * 2012-01-23 2015-06-16 International Business Machines Corporation Method to form silicide contact in trenches
JP2014093422A (ja) * 2012-11-02 2014-05-19 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP6026914B2 (ja) * 2013-02-12 2016-11-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6022377B2 (ja) 2013-02-28 2016-11-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090081836A1 (en) * 2007-09-24 2009-03-26 International Business Machines Corporation Method of forming cmos with si:c source/drain by laser melting and recrystallization
US20090243002A1 (en) * 2008-03-28 2009-10-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20100075481A1 (en) * 2008-07-08 2010-03-25 Xiao (Charles) Yang Method and structure of monolithically integrated ic-mems oscillator using ic foundry-compatible processes
US20140022784A1 (en) * 2011-04-04 2014-01-23 Ceram Tec Gmbh Led lamp comprising an led as the luminaire and a glass or plastic lampshade
US20120292708A1 (en) * 2011-05-20 2012-11-22 Broadcom Corporation Combined Substrate High-K Metal Gate Device and Oxide-Polysilicon Gate Device, and Process of Fabricating Same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180006048A1 (en) * 2013-02-12 2018-01-04 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US10263005B2 (en) * 2013-02-12 2019-04-16 Renesas Electronics Corporation Method of manufacturing a semiconductor device
US11183510B2 (en) 2016-12-22 2021-11-23 Renesas Electronics Corporation Manufacturing method of semiconductor device and semiconductor device
US10062705B1 (en) * 2017-04-13 2018-08-28 United Microelectronics Corp. Method of manufacturing a flash memory
KR20190006142A (ko) * 2017-07-07 2019-01-17 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
KR102421766B1 (ko) 2017-07-07 2022-07-18 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
US20190027484A1 (en) * 2017-07-19 2019-01-24 Cypress Semiconductor Corporation Embedded non-volatile memory device and fabrication method of the same
US10872898B2 (en) * 2017-07-19 2020-12-22 Cypress Semiconductor Corporation Embedded non-volatile memory device and fabrication method of the same
US20210328035A1 (en) * 2020-04-16 2021-10-21 Samsung Electronics Co., Ltd. Semiconductor devices

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US20190341395A1 (en) 2019-11-07
CN107155369A (zh) 2017-09-12

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