US20170123250A1 - Liquid crystal device and electronic apparatus - Google Patents
Liquid crystal device and electronic apparatus Download PDFInfo
- Publication number
- US20170123250A1 US20170123250A1 US15/331,007 US201615331007A US2017123250A1 US 20170123250 A1 US20170123250 A1 US 20170123250A1 US 201615331007 A US201615331007 A US 201615331007A US 2017123250 A1 US2017123250 A1 US 2017123250A1
- Authority
- US
- United States
- Prior art keywords
- light shielding
- shielding layer
- layer
- liquid crystal
- disposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 221
- 239000000758 substrate Substances 0.000 claims abstract description 221
- 230000002093 peripheral effect Effects 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims description 138
- 239000000463 material Substances 0.000 claims description 35
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 706
- 239000010408 film Substances 0.000 description 107
- 239000011229 interlayer Substances 0.000 description 97
- 239000003990 capacitor Substances 0.000 description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 25
- 238000000034 method Methods 0.000 description 24
- 238000007789 sealing Methods 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 20
- 239000002184 metal Substances 0.000 description 20
- 230000000149 penetrating effect Effects 0.000 description 19
- 230000007423 decrease Effects 0.000 description 17
- 238000002834 transmittance Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 14
- 230000010287 polarization Effects 0.000 description 13
- 238000007689 inspection Methods 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000003287 optical effect Effects 0.000 description 9
- 230000008859 change Effects 0.000 description 8
- 238000005286 illumination Methods 0.000 description 8
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 229910010272 inorganic material Inorganic materials 0.000 description 5
- 239000011147 inorganic material Substances 0.000 description 5
- 230000000644 propagated effect Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 101000822028 Homo sapiens Solute carrier family 28 member 3 Proteins 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 102100021470 Solute carrier family 28 member 3 Human genes 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 2
- 229910052753 mercury Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000001579 optical reflectometry Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000002194 synthesizing effect Effects 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 101000685663 Homo sapiens Sodium/nucleoside cotransporter 1 Proteins 0.000 description 1
- 101000821827 Homo sapiens Sodium/nucleoside cotransporter 2 Proteins 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 102100023116 Sodium/nucleoside cotransporter 1 Human genes 0.000 description 1
- 102100021541 Sodium/nucleoside cotransporter 2 Human genes 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum (Al) Chemical class 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
- G02F1/13685—Top gates
-
- G02F2001/136218—
-
- G02F2001/13685—
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/16—Materials and properties conductive
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2203/00—Function characteristic
- G02F2203/02—Function characteristic reflective
Definitions
- the present invention relates to a liquid crystal device and an electronic apparatus.
- liquid crystal device for example, an active driving type liquid crystal device in which a transistor for switching and controlling a pixel electrode is provided for each pixel, is known.
- the liquid crystal device is used, for example, as a liquid crystal light bulb of a liquid crystal projector as an electronic apparatus.
- the liquid crystal device includes an element substrate, a counter substrate disposed opposite to the element substrate, and a liquid crystal layer interposed by the element substrate and the counter substrate.
- the transistor and a light shielding layer for shielding light from the liquid crystal projector to the transistor are provided.
- a method of shielding light toward the transistor is disclosed, by providing the transistor on a substrate of a pixel region and providing a first light shielding film and a second light shielding film between the substrate and the transistor (active layer).
- the amount of light of the liquid crystal projector increases, it is required to improve light shielding properties.
- JP-A-2003-131261 discloses a configuration in which a scanning line (gate wiring) that is formed by stacking a metal light shielding film A, an insulating film (metal oxide film or metal nitride film) B, and a metal light shielding film C is disposed in the lower layer of the semiconductor layer of a reverse staggered (bottom gate) type TFT.
- JP-A-2004-5302475 discloses a configuration in which a first light shielding film and a second light shielding film that interpose an insulating film therebetween are stacked in the lower layer of the semiconductor layer and the potential of the second light shielding film is set to a gate potential or a constant voltage.
- JP-A-2011-158700 discloses a configuration in which a scanning line that is formed by stacking the three layers of a metal film is disposed in the lower layer of the semiconductor layer.
- JP-A-2003-131261 although the configuration of the light shielding film in the pixel region is disclosed, the configuration of the light shielding film in the peripheral region around the pixel region is not disclosed. Further, when light is incident to the transistor in the peripheral region, there is a problem that light negatively affects the characteristics of the transistor such as the change in the characteristics of the transistor or the like.
- JP-A-2004-5302475 and JP-A-2011-238835 since two layers of the light shielding layer are insulated from each other, the wiring resistance of the scanning line is not considered.
- JP-A-2011-158700 since the light shielding layer (scanning line) is made of the three layers of a metal film that are stacked being in contact with each other, there is a concern that the light shielding properties are insufficient compared to a case where a layer having a different refractive index such as an insulating film or the like is interposed between the light shielding layers. Therefore, there is a demand for a display apparatus capable of improving the light shielding properties compared to the related art and decreasing the wiring resistance of the scanning line.
- a liquid crystal device including: a substrate; a liquid crystal layer disposed on the substrate; a first light shielding layer disposed between the substrate and the liquid crystal layer; a second light shielding layer disposed between the first light shielding layer and the liquid crystal layer; a first transistor provided between the second light shielding layer and the liquid crystal layer in a display region; and a second transistor provided between the first light shielding layer and the liquid crystal layer in a peripheral region that is a region around the display region, in which the first transistor is disposed so as to overlap with at least the second light shielding layer in a plan view, and in which the second transistor is disposed so as to overlap with at least the first light shielding layer in a plan view.
- the first transistor of the pixel disposed in the display region overlaps with the second light shielding layer in a plan view, and thus, even in a case where light is incident to the display region, it is possible to shield the first transistor from light.
- the second transistor disposed in the peripheral region overlaps with the first light shielding layer in a plan view, and thus, for example, even in a case where light leaked from the outside is incident to the peripheral region, it is possible to shield the second transistor from light.
- the second light shielding layer is disposed in the layer closer to the first transistor than the first light shielding layer, and thus it is possible to further prevent light from being incident to the first transistor in a transmission region through which light is transmitted. Further, it is possible to improve the light shielding properties of light that is incident at an angle.
- the first transistor is disposed so as to overlap with the first light shielding layer and the second light shielding layer in a plan view.
- the first transistor is disposed so as to overlap with the two layers of the first light shielding layer and the second light shielding layer in a plan view, and thus it is possible to further improve the light shielding properties of the first transistor in the region (display region) through which light is transmitted.
- the first light shielding layer and the second light shielding layer are electrically connected to a gate electrode of the first transistor by one contact hole.
- the first light shielding layer and the second light shielding layer are electrically connected to the gate electrode, and thus it is possible to prevent a change in characteristics of the transistor such as a potential change or a floating. Further, the first light shielding layer and the second light shielding layer are electrically connected to the gate electrode by one contact hole, and thus it is possible to prevent a significant decrease in the aperture ratio. In addition, it is also possible to effectively correspond to a case where the pitch between pixels is narrowed.
- At least one of the first light shielding layer and the second light shielding layer is made of a material having a light reflection property.
- the first light shielding layer and second light shielding layer have a light reflection property, and thus it is possible to prevent the first transistor and the second transistor (further, liquid crystal device) from heating.
- materials of the first light shielding layer and the second light shielding layer are tungsten silicide.
- the first light shielding layer and the second light shielding layer are made of tungsten silicide, and thus it is possible to prevent the first transistor and the second transistor (further, liquid crystal device) from heating.
- a liquid crystal device including: a first substrate; a second substrate disposed opposite to the first substrate; a liquid crystal layer interposed between the first substrate and the second substrate; a switching element including a semiconductor layer that is disposed on the first substrate for each pixel and includes a channel region, a gate insulating layer covering the semiconductor layer, and a gate electrode disposed opposite to the channel region via the gate insulating layer; a first light shielding layer that is disposed on the first substrate so as to overlap with the semiconductor layer in a plan view and is set to the same potential as the potential of the gate electrode; a first insulating layer disposed so as to cover the first light shielding layer; a second light shielding layer that is disposed on the first insulating layer so as to overlap with the semiconductor layer and the first light shielding layer in a plan view and is set to the same potential as the potential of the gate electrode; and a second insulating layer disposed so as to cover the second light shielding layer, in which the first light shielding layer,
- the first light shielding layer, the first insulating layer, the second light shielding layer, and the second insulating layer are disposed between the first substrate and the semiconductor layer. Therefore, light incident from the first substrate side toward the semiconductor layer side is reflected at the interface between the first substrate and the first light shielding layer, and then reflected at the interface between the first insulating layer and the second light shielding layer. Thus, it is possible to effectively shield light incident from the first substrate side to the semiconductor layer.
- the potentials of the first light shielding layer and the second light shielding layer are set to the same potential as that of the gate electrode, and thus it is possible to configure the scanning line using the two layers of light shielding layer.
- the gate wiring is disposed in the same layer as that of the gate electrode, it is possible to configure the scanning line using the three layers including the two layers of the light shielding layer, thereby decreasing the wiring resistance of the scanning line. As a result, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding properties compared to the related art, thereby providing the liquid crystal device having a high liquid crystal quality.
- the first light shielding layer and the second light shielding layer are formed straddling the boundary between the pixels.
- the first light shielding layer and the second light shielding layer that constitute the scanning line are formed straddling the boundary between the pixels, and thus, even in a case where the liquid crystal device is a large liquid crystal device including the scanning line with a long length liquid crystal device, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding property.
- the first light shielding layer or the second light shielding layer may be formed to be separated for each pixel.
- any one of the light shielding layers may be separated for each pixel.
- a first contact hole and a second contact hole that penetrate the first insulating layer and electrically connect the first light shielding layer and the second light shielding layer, are further provided, and that the first contact hole and the second contact hole are disposed at both outsides of the semiconductor layer in a direction intersecting the extending direction of the semiconductor layer in a plan view.
- the pair of light shielding portions along the normal direction of the first substrate are formed between the first light shielding layer and the second light shielding layer by the contact holes penetrating the first insulating layer.
- the pair of light shielding portions are disposed at both outsides of the semiconductor layer in a plan view. Therefore, it is possible to shield light that is incident at an angle with respect to the normal direction of the first substrate from the first substrate side, and light reflected and propagated between the first light shielding layer and the second light shielding layer, from both outsides of the semiconductor layer, by the light shielding portions formed by the contact holes. Accordingly, it is possible to further improve the light shielding property.
- the second light shielding layer is formed so as to fill the first contact hole and the second contact hole and has a substantially flat surface.
- the second light shielding layer having a substantially flat surface is formed on the first insulating layer by filling the pair of the contact holes penetrating the first insulating layer. Therefore, in a case of forming the contact holes for electrical connection from the upper layer side (gate electrode side) to the second light shielding layer, the positions at which the contact holes are disposed are not restricted, and thus it is possible to increase the degree of freedom in the wiring pattern design.
- a third contact hole and a fourth contact hole that penetrate the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer are further provided, and that the third contact hole is disposed so as to overlap with the first contact hole in a plan view and the fourth contact hole is disposed so as to overlap with the second contact hole in a plan view.
- the pair of the contact holes that penetrate the first insulating layer and electrically connect the first light shielding layer and the second light shielding layer are disposed so as to overlap with the pair of the contact holes that penetrate the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer in a plan view. Therefore, it is possible to reduce the size of the region that is shielded by the contact holes, thereby improving the aperture ratio of the liquid crystal device. Further, the pair of light shielding portions along the normal direction of the first substrate are formed by the contact holes penetrating the gate insulating layer and the second insulating layer, and the pair of light shielding portions are disposed at both outsides of the semiconductor layer in a plan view. Thus, it is possible to further improve the light shielding property.
- a fifth contact hole that penetrates the first insulating layer and electrically connects the first light shielding layer and the second light shielding layer is further provided, and that, in the sectional view taken along the extending direction of the semiconductor layer, the second light shielding layer is disposed across the bottom portion and the side portions of the fifth contact hole, and the surface of the first insulating layer positioned at the outsides of the fifth contact hole, and that, in the sectional view taken along the extending direction of the semiconductor layer, the semiconductor layer is disposed so as to cover the second light shielding layer via the second insulating layer.
- the second light shielding layer is disposed across the bottom portion of the contact hole penetrating the first insulating layer, the side portions of the contact hole, and the surface of the first insulating layer at the outsides of the contact hole.
- the semiconductor layer is disposed so as to cover the second light shielding layer via the second insulating layer. Therefore, it is possible to make the substantial length of the semiconductor layer longer than the length of the semiconductor layer in a plan view. In other words, it is possible to make the length of the semiconductor layer in a plan view shorter than the length of the semiconductor layer that is required. Thus, it is possible to reduce the size of the light shielding region, thereby improving the aperture ratio of the liquid crystal device.
- the channel region of the semiconductor layer is disposed at the bottom portion of the fifth contact hole.
- the channel region of the semiconductor layer is disposed on the bottom portion of the contact hole.
- the LDD regions are disposed at both outsides of the channel region, it is possible to dispose the LDD regions in a region from the bottom portion to the outsides of the contact hole via the side portions of the contact hole.
- the LDD regions having a sufficient length. Therefore, it is possible to form the switching element with excellent operating characteristics.
- the second light shielding layer that is disposed in the lower layer of the semiconductor layer is disposed so as to cover the bottom portion of the contact hole on which the channel region is disposed, the side portions of the contact hole, and the surface of the first insulating layer at the outsides of the contact hole.
- a third contact hole and a fourth contact hole that penetrate the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer, are further provided, and that the third contact hole and the fourth contact hole are disposed at both outsides of the semiconductor layer in a direction intersecting the extending direction of the semiconductor layer in a plan view.
- the pair of light shielding portions along the normal direction of the first substrate are formed by the contact holes penetrating the gate insulating layer and the second insulating layer.
- the pair of light shielding portions are disposed at both outsides of the semiconductor layer in a plan view. Therefore, it is possible to shield light that is incident at an angle with respect to the normal direction of the first substrate from the first substrate side, and light reflected and propagated between the gate electrode and the second light shielding layer, from both outsides of the semiconductor layer, by the light shielding portions formed by the contact holes. Accordingly, it is possible to further improve the light shielding property.
- a plurality of contact holes that penetrate the first insulating layer and electrically connect the first light shielding layer and the second light shielding layer, may be further provided, and the number of the contact holes may be less than the number of the pixels.
- the number of the contact holes may be less than the number of the pixels.
- an electronic apparatus including the liquid crystal device described above.
- the liquid crystal device is provided, and thus it is possible to provide the electronic apparatus having an excellent display quality.
- FIG. 1 is a schematic plan view illustrating the configuration of a liquid crystal device.
- FIG. 2 is a schematic sectional view taken along line II-II of the liquid crystal device illustrated in FIG. 1 .
- FIG. 3 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device.
- FIG. 4 is a schematic sectional view mainly illustrating the configuration of the pixel of the liquid crystal device.
- FIG. 5 is an enlarged plan view illustrating the enlarged V portion of the liquid crystal device in FIG. 1 .
- FIG. 6 is a schematic sectional view illustrating the configuration of a light shielding layer of a display region according to a first embodiment.
- FIG. 7 is a schematic sectional view illustrating the configuration of the light shielding layer of a peripheral region.
- FIG. 8 is a schematic diagram illustrating the configuration of a projector as an electronic apparatus.
- FIG. 9 is a schematic sectional view illustrating the configuration of a light shielding layer of a display region according to a second embodiment.
- FIG. 10 is a schematic sectional view illustrating the configuration of the light shielding layer of a peripheral region.
- FIG. 11 is a schematic plan view illustrating the configurations of a light shielding layer and a first transistor of a display region according to a third embodiment.
- FIG. 12 is a schematic sectional view illustrating the configurations of the light shielding layer and the first transistor of the display region.
- FIG. 13 is a schematic plan view illustrating the configuration of a liquid crystal device according to a fourth embodiment.
- FIG. 14 is a schematic sectional view taken along line XIV-XIV in FIG. 13 .
- FIG. 15 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device according to the fourth embodiment.
- FIG. 16 is a schematic sectional view illustrating the configuration of an element substrate of the liquid crystal device according to the fourth embodiment.
- FIG. 17 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the fourth embodiment.
- FIG. 18 is a schematic sectional view taken along line XVIII-XVIII in FIG. 17 .
- FIG. 19 is a graph illustrating the light shielding effect of the element substrate according to the fourth embodiment.
- FIG. 20 is a schematic plan view illustrating the configuration of a TFT portion of an element substrate according to a fifth embodiment.
- FIG. 21 is a schematic sectional view taken along line XXI-XXI in FIG. 20 .
- FIG. 22 is a schematic plan view illustrating the configuration of a TFT portion of an element substrate according to a sixth embodiment.
- FIG. 23 is a schematic sectional view taken along line XXIII-XXIII in FIG. 22 .
- FIG. 24 is a schematic plan view illustrating the configuration of a TFT portion of an element substrate according to a seventh embodiment.
- FIG. 25 is a schematic sectional view taken along line XXV-XXV in FIG. 24 .
- FIG. 26 is a schematic diagram illustrating the configuration of a projector as an electronic apparatus according to an eighth embodiment.
- FIG. 27 is a schematic plan view illustrating a configuration example of a TFT portion of an element substrate of the related art.
- FIG. 28 is a schematic sectional view taken along line XXVIII-XXVIII in FIG. 27 .
- “on substrate” when “on substrate” is described, it represents a case so as to be disposed in contact with the surface of the substrate, a case so as to be disposed on the substrate via other components, or a case so as to be disposed in partial contact with the surface of the substrate and disposed on the substrate via other components.
- liquid crystal device an active matrix type liquid crystal device that includes a thin film transistor as a switching element of a pixel will be described as an example.
- the liquid crystal device may be preferably used, for example, as a light modulation element (liquid crystal light bulb) of a projection type display apparatus (liquid crystal projector).
- FIG. 1 is a schematic plan view illustrating the configuration of the liquid crystal device.
- FIG. 2 is a schematic sectional view taken along a line II-II of the liquid crystal device illustrated in FIG. 1 .
- FIG. 3 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device.
- the configuration of the liquid crystal device will be described with reference to FIGS. 1 to 3 .
- the liquid crystal device 100 includes an element substrate 10 and a counter substrate 20 that are disposed to be opposite to each other, and a liquid crystal layer 15 that is interposed by a pair of the substrates.
- a first base material 10 a (substrate) that constitutes the element substrate 10 and a second base material 20 a that constitutes the counter substrate 20 for example, a transparent substrate such as a glass substrate or a quartz substrate is used.
- the size of the element substrate 10 is larger than that of the counter substrate 20 , and both of the substrates are bonded to each other via sealing members 14 disposed along the outer circumference of the counter substrate 20 .
- the gap between the sealing members 14 is filled and sealed with liquid crystal having a positive or negative dielectric anisotropy, and thus the liquid crystal layer 15 is configured.
- sealing member 14 for example, an adhesive such as thermosetting epoxy resin or ultraviolet-curable epoxy resin is employed.
- the sealing member 14 incorporates a spacer for maintaining the gap between the pair of substrates. The spacer is used to make a cell gap.
- the display region E in which a plurality of pixels P that contributes to display are arranged is provided in the inside of the sealing member 14 .
- a peripheral region E 1 in which peripheral circuits or the like that do not contribute to display are provided is disposed around the display region E.
- a data line driving circuit 22 is provided between the sealing member 14 along a first-direction side portion of the element substrate 10 and the first-direction side portion.
- An inspection circuit 25 is provided between the sealing member 14 along another first-direction side portion that is opposite to the first-direction side portion and the display region E.
- Scanning line driving circuits 24 are provided between the sealing members 14 along second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other and the display region E.
- a plurality of wirings 29 connecting the two scanning line driving circuits 24 are provided between the sealing member 14 along another first-direction side portion that is opposite to the first-direction side portion and the inspection circuit 25 .
- a frame-shaped light shielding film 18 (parting portion) is provided in the inside of the sealing member 14 at the counter substrate 20 side that is disposed in a frame shape.
- the light shielding film 18 is made of metal, metal oxide, or the like having a light reflection property, and the inside of the light shielding film 18 is the display region E that includes the plurality of pixels P.
- the light shielding film 18 for example, tungsten silicide (WSi) may be used.
- WSi tungsten silicide
- a light shielding film that partitions the plurality of pixels P in a plane is also provided in the display region E.
- the wiring connected to the data line driving circuit 22 and the scanning line driving circuit 24 is connected to a plurality of external connection terminals 65 that are arranged along the first-direction side portion.
- the direction along the first-direction side portion is described as an X-direction
- the direction along second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other is described as a Y-direction.
- a transparent pixel electrode 27 and a thin film transistor as a switching element that are provided for each pixel P, signal wiring (not illustrated), and a first alignment film 28 covering the transparent pixel electrode 27 , the transistor 30 , and the signal wiring is formed on the surface of the first base material 10 a on the liquid crystal layer 15 side.
- the light shielding configuration (not illustrated) that prevents a switching operation from being unstable due to light that is incident to the semiconductor layer of the transistor 30 is employed.
- the element substrate 10 of the invention includes at least the pixel electrode 27 , the transistor 30 , the signal wiring, and the first alignment film 28 .
- the light shielding film 18 , an insulating layer 33 that is formed so as to cover the light shielding film 18 , a counter electrode 31 that is provided to cover the insulating layer 33 , and a second alignment film 32 that covers the counter electrode 31 are provided on the surface of the counter substrate 20 on the liquid crystal layer 15 side.
- the counter substrate 20 of the invention includes at least the light shielding film 18 , the counter electrode 31 , and the second alignment film 32 .
- the light shielding film 18 surrounds the display region E, and is provided at the position overlapping with the scanning line driving circuit 24 and the inspection circuit 25 in a plane. Accordingly, the light shielding film 18 prevents the malfunction of the peripheral circuits including these driving circuits due to light, by shielding light that is incident to the peripheral circuits from the counter substrate 20 side. Further, the light shielding film 18 ensures high contrast in the display of the display region E by shielding unnecessary stray light so as not to be incident to the display region E.
- the insulating layer 33 is made of, for example, an inorganic material such as silicon oxide, and has a light transmitting property.
- the insulating layer 33 is provided so as to cover the light shielding film 18 .
- a method of forming the insulating layer 33 for example, a method of forming a film using a plasma chemical vapor deposition (CVD) method or the like may be used.
- CVD plasma chemical vapor deposition
- the counter electrode 31 is made of, for example, a transparent conductive film such indium tin oxide (ITO), and covers the insulating layer 33 . As illustrated in FIG. 1 , the counter electrode 31 is electrically connected to the wiring on the element substrate 10 side by upper and lower conduction portions 26 provided at the four corners of the counter substrate 20 .
- ITO indium tin oxide
- the first alignment film 28 covering the pixel electrode 27 and the second alignment film 32 covering the counter electrode 31 are selected based on the optical design of the liquid crystal device 100 .
- an inorganic alignment film obtained by forming a film with an inorganic material such as SiO x (silicon oxide) using a vapor growth method and aligning the film substantially perpendicular to the liquid crystal molecules having negative dielectric anisotropy may be used.
- the liquid crystal device 100 is, for example, a transmission type, and adopts a normally white mode type optical design in which the transmittance of the pixel P when a voltage is not applied is greater than the transmittance when a voltage is applied, or a normally black mode type optical design in which the transmittance of the pixel P when a voltage is not applied is smaller than the transmittance when a voltage is applied.
- a polarization element is respectively disposed and used at the incident side and the emitting side of light according to the optical design.
- the liquid crystal device 100 includes at least a plurality of scanning lines 3 a and a plurality of data lines 6 a that are insulated from each other and perpendicular to each other in the display region E, and a plurality of capacitance lines 3 b .
- the direction to which the scanning lines 3 a are extended is the X-direction
- the direction to which the data lines 6 a are extended is the Y-direction.
- the pixel circuit of the pixel P is configured with the scanning line 3 a , the data line 6 a , the capacitance line 3 b , the pixel electrodes 27 , the transistors 30 , and capacitor elements 16 that are provided in the region divided by the signal lines.
- the scanning line 3 a is electrically connected to the gate of the transistor 30
- the data line 6 a is electrically connected to the source-drain region on the data line side of the transistor 30 .
- the pixel electrode 27 is electrically connected to the source-drain region on the pixel electrode side of the transistor 30 .
- the data line 6 a is connected to the data line driving circuit 22 (refer to FIG. 1 ), and supplies the image signals D 1 , D 2 , . . . , Dn supplied from the data line driving circuit 22 to the pixel P.
- the scanning line 3 a is connected to the scanning line driving circuit 24 (refer to FIG. 1 ), and supplies the scanning signals SC 1 , SC 2 , . . . , SCm supplied from the scanning line driving circuit 24 to each pixel P.
- the image signals D 1 to Dn supplied from the data line driving circuit 22 to the data line 6 a may be line-sequentially supplied in this order, or may be supplied for each group with a plurality of data lines 6 a adjacent to each other.
- the scanning line driving circuit 24 supplies the scanning signals SC 1 to SCm to the scanning lines 3 a in a line sequential manner using a pulse at a predetermined timing.
- the transistor 30 as a switching element is turned on only for a certain period by the input of the scanning signals SC 1 to SCm, and thus image signals D 1 to Dn supplied from the data lines 6 a are written to the pixel electrode 27 at a predetermined timing.
- the image signals D 1 to Dn with a predetermined level that are written to the liquid crystal layer 15 via the pixel electrode 27 are held for a predetermined period between the pixel electrode 27 and the counter electrode 31 that are disposed to interpose the liquid crystal layer 15 .
- the capacitor element 16 is connected in parallel to a liquid crystal capacitor formed between the pixel electrode 27 and the counter electrode 31 .
- the capacitor element 16 is provided between the source-drain region of the transistor 30 on the pixel electrode side and the capacitance line 3 b .
- the capacitor element 16 is an element that includes a dielectric layer between two capacitor electrodes.
- FIG. 4 is a schematic sectional view mainly illustrating the configuration of the pixel of the liquid crystal device.
- FIG. 4 illustrates the sectional position relationship of each component in a clearly displayable scale.
- the pixel P of the liquid crystal device 100 includes the element substrate 10 , and the counter substrate 20 disposed opposite to the element substrate.
- the first base material 10 a constituting the element substrate 10 is, for example, a quartz substrate.
- a first light shielding layer 3 c 1 that is made of, for example, tungsten silicide (WSi) is disposed on the first base material 10 a .
- the first light shielding layer 3 c 1 is patterned in a plane lattice shape, and defines the opening region of each pixel P.
- a first insulating layer 11 a that is made of silicon oxide is formed on the first light shielding layer 3 c 1 and the first base material 10 a .
- a second light shielding layer 3 c 2 that is made of, for example, tungsten silicide (WSi) having a light reflection property is formed on the first insulating layer 11 a , so as to overlap with a partial region of a semiconductor layer 30 a in a plan view.
- a second insulating layer 11 b that is made of silicon oxide or the like is formed on the second light shielding layer 3 c 2 and the first insulating layer 11 a.
- the transistor 30 , the scanning line 3 a , and the like are formed on the second insulating layer 11 b .
- the transistor 30 has, for example, a Lightly Doped Drain (LDD) structure, and includes the semiconductor layer 30 a that is made of polysilicon (polycrystalline silicon having high purity), a gate insulating layer 11 g formed on the semiconductor layer 30 a , and a gate electrode 30 g that is made of polysilicon film or the like and formed on the gate insulating layer 11 g .
- the scanning line 3 a also functions as the gate electrode 30 g.
- the semiconductor layer 30 a is formed as the N-type transistor 30 by, for example, being implanted with N-type impurity ions such as phosphorus (P) ions.
- the semiconductor layer 30 a includes a channel region 30 c , a data line side LDD region 30 s 1 , a data line side source-drain region 30 s , a pixel electrode side LDD region 30 d 1 , and a pixel electrode side source-drain region 30 d.
- the channel region 30 c is doped with P-type impurity ions such as boron (B) ions.
- the other regions ( 30 s 1 , 30 s , 30 d 1 , 30 d ) are doped with N-type impurity ions such as phosphorus (P) ions.
- the transistor 30 is formed as an N-type transistor.
- a third interlayer insulating layer 11 c that is made of silicon oxide or the like is formed on the gate electrode 30 g and the gate insulating layer 11 g .
- the capacitor element 16 is provided on the third interlayer insulating layer 11 c .
- a first capacitor electrode 16 a as a pixel potential side capacitor electrode that is electrically connected to the pixel electrode side source-drain region 30 d of the transistor 30 and the pixel electrode 27 and a part of the capacitance line 3 b (second capacitor electrode 16 b ) as a fixed potential side capacitor electrode are disposed opposite to each other via a dielectric film 16 c , and thus the capacitor element 16 is formed.
- the dielectric film 16 c is, for example, a silicon nitride film.
- the second capacitor electrode 16 b (capacitance line 3 b ) is made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, or a material obtained by stacking the above-mentioned material that includes at least one of metals having a high melting point such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), or molybdenum (Mo).
- the second capacitor electrode 16 b may also be formed by an aluminum (Al) film.
- the first capacitor electrode 16 a functions as the pixel potential side capacitor electrode of the capacitor element 16 that is made of, for example, a conductive polysilicon film.
- the first capacitor electrode 16 a may be made of a single layer film or a multilayer film that includes a metal or an alloy, similarly to the capacitance line 3 b .
- the first capacitor electrode 16 a has a function of relaying and connecting the pixel electrode 27 and the pixel electrode side source-drain region 30 d (drain region) of the transistor 30 via contact holes CNT 1 , CNT 3 , and CNT 4 , in addition to the function as the pixel potential side capacitor electrode.
- the data line 6 a is formed on the capacitor element 16 via a fourth interlayer insulating layer 11 d .
- the data line 6 a is electrically connected to the data line side source-drain region 30 s (source region) of the semiconductor layer 30 a via a gate insulating layer 11 g , a third interlayer insulating layer 11 c , the dielectric film 16 c , and a contact hole CNT 2 that is open in the fourth interlayer insulating layer 11 d.
- the pixel electrode 27 is formed above the data line 6 a via a fifth interlayer insulating layer 11 e .
- the fifth interlayer insulating layer 11 e is made of, for example, silicon oxide or silicon nitride, and subjected to a planarization process for planarizing the protrusion portion of the surface that is caused by covering the region in which the transistor 30 is provided.
- a planarization process a chemical mechanical polishing (CMP) process, a spin coating process, or the like may be used.
- CMP chemical mechanical polishing
- the contact hole CNT 4 is formed in the fifth interlayer insulating layer 11 e.
- the pixel electrode 27 is connected to the first capacitor electrode 16 a via the contact holes CNT 4 and CNT 3 , and thus the pixel electrode 27 is electrically connected to the pixel electrode side source-drain region 30 d (drain region) of the semiconductor layer 30 a .
- the pixel electrode 27 is formed, for example, by a transparent conductive film such as an ITO film.
- a first alignment film 28 that is formed by obliquely vapor-depositing an inorganic material such as silicon oxide (SiO 2 ) is provided on the fifth interlayer insulating layer 11 e between the pixel electrode 27 and the adjacent pixel electrode 27 .
- a liquid crystal layer 15 that is filled and sealed with liquid crystal or the like in the space surrounded by the sealing member 14 is provided on the first alignment film 28 .
- the counter electrode 31 is provided, for example, on the entire surface of the insulating layer 33 (liquid crystal layer 15 side) of the counter substrate 20 .
- a second alignment film 32 that is formed by obliquely vapor-depositing an inorganic material such as silicon oxide (SiO 2 ) is provided on the counter electrode 31 .
- the counter electrode 31 is formed, for example, by a transparent conductive film such as an ITO film, similarly to the pixel electrode 27 .
- the liquid crystal layer 15 is in a predetermined alignment state by the alignment films 28 and 32 in a state where an electric field is not generated between the pixel electrode 27 and the counter electrode 31 .
- the sealing member 14 is an adhesive for bonding the element substrate 10 and the counter substrate 20 that is made of a photocurable resin or a thermosetting resin, and the spacers such as glass fibers or glass beads for making the distance between the element substrate 10 and the counter substrate 20 with a predetermined value are mixed into the sealing member 14 .
- Light of a projector 1000 to be described later is incident, for example, from the back side of the liquid crystal device 100 (element substrate 10 side).
- FIG. 5 is an enlarged plan view illustrating the enlarged V portion of the liquid crystal device in FIG. 1 .
- FIG. 6 is a schematic sectional view illustrating the configuration of the light shielding layer (second light shielding layer) of the display region.
- FIG. 7 is a schematic sectional view illustrating the configuration of the light shielding layer (first light shielding layer) of the peripheral region.
- the liquid crystal device 100 includes the display region E in which the pixels P each of which includes a first transistor 301 are disposed, and the peripheral region E 1 in which the peripheral circuits each of which includes a second transistor 302 are disposed.
- the first insulating layer 11 a , the second light shielding layer 3 c 2 , the second insulating layer 11 b , and the semiconductor layer 30 a 1 are stacked in this order from the first base material 10 a side.
- the second light shielding layer 3 c 2 is disposed so as to overlap with the semiconductor layer 30 a 1 in a plan view.
- the second light shielding layer 3 c 2 is disposed so as to overlap with at least the LDD region of the semiconductor layer 30 a 1 in a plan view.
- the first light shielding layer 3 c 1 , the first insulating layer 11 a , the second insulating layer 11 b , and the semiconductor layer 30 a 2 are stacked in this order from the first base material 10 a side.
- the first light shielding layer 3 c 1 is disposed so as to overlap with the semiconductor layer 30 a 2 in a plan view.
- the first light shielding layer 3 c 1 is disposed so as to overlap with at least the LDD region of the semiconductor layer 30 a 2 in a plan view.
- a material having light shielding properties or light reflection properties may be used.
- tungsten silicide (WSi) having a light reflection property may be used, similarly to the light shielding film 18 . As described above, tungsten silicide is used, and thus it is possible to prevent the heat being applied to the transistor.
- the second light shielding layer 3 c 2 provided in the display region E is disposed so as to overlap with the first transistor 301 in a plan view, and can shield light at the position closer than the layer of the first light shielding layer 3 c 1 .
- the first light shielding layer 3 c 1 provided in the peripheral region E 1 is disposed so as to overlap with the second transistor 302 in a plan view.
- the first light shielding layer 3 c 1 can shield light leaked from the outside. Therefore, it is possible to prevent a change in characteristics of the transistor, for example.
- the thickness of the first light shielding layer 3 c 1 is equal to or greater than 200 nm, for example.
- the thickness of the second light shielding layer 3 c 2 is equal to or greater than 100 nm, for example.
- the thickness of the first insulating layer 11 a is, for example, 2000 ⁇ .
- the thickness of the second insulating layer 11 b is, for example, 2000 ⁇ .
- FIG. 8 is a schematic diagram illustrating the configuration of the projector as an electronic apparatus. Hereinafter, the configuration of the projector will be described with reference to FIG. 8 .
- the projector 1000 includes a polarization illumination device 1100 as an illumination system disposed along the system optical axis L, two dichroic mirrors 1104 and 1105 as a light separation element, three reflection mirrors 1106 , 1107 , and 1108 , five relay lenses 1201 , 1202 , 1203 , 1204 , and 1205 , three transmission type liquid crystal light bulbs 1210 , 1220 , and 1230 as light modulation means, a cross dichroic prism 1206 as a light synthesizing element, and a projection lens 1207 .
- a polarization illumination device 1100 as an illumination system disposed along the system optical axis L
- two dichroic mirrors 1104 and 1105 as a light separation element
- three reflection mirrors 1106 , 1107 , and 1108 five relay lenses 1201 , 1202 , 1203 , 1204 , and 1205
- three transmission type liquid crystal light bulbs 1210 , 1220 , and 1230 as light modulation means
- the polarization illumination device 1100 is schematically configured with a lamp unit 1101 as a light source that is configured by a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102 , and a polarization conversion element 1103 .
- the dichroic mirror 1104 reflects red light (R) among polarized light beams emitted from the polarization illumination device 1100 , and transmits green light (G) and blue light (B).
- Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 , and transmits the blue light (B).
- the red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 , and then is incident to the liquid crystal light bulb 1210 via the relay lens 1205 .
- the green light (G) reflected by the dichroic mirror 1105 is incident to the liquid crystal light bulb 1220 via the relay lens 1204 .
- the blue light (B) transmitted through the dichroic mirror 1105 is incident to the liquid crystal light bulb 1230 via a light guide system that is configured by three relay lenses 1201 , 1202 , and 1203 and two reflection mirrors 1107 and 1108 .
- the liquid crystal light bulbs 1210 , 1220 , and 1230 are respectively disposed opposite to the incidence plane of each color light of the cross dichroic prism 1206 .
- Each color light incident to the liquid crystal light bulbs 1210 , 1220 , and 1230 is modulated based on video information (video signal), and emitted toward the cross dichroic prism 1206 .
- the prism is formed by bonding four right-angle prisms.
- a dielectric multilayer film that reflects the red light and a dielectric multilayer film that reflects the blue light are formed in a cross shape.
- Three color light beams are synthesized by the dielectric multilayer films, and thus light beams representing a color image are synthesized.
- Light beams that are synthesized are projected on a screen 1300 by the projection lens 1207 that constitutes a projection optical system 1400 , and thus the image is enlarged and displayed.
- the liquid crystal device 100 to be described later is applied to the liquid crystal light bulb 1210 .
- the liquid crystal device 100 is disposed with a gap between a pair of polarization elements that are disposed in a crossed nicol state at the incident side and the emitting side of the color light.
- the other liquid crystal light bulbs 1220 and 1230 are similar to the liquid crystal light bulb 1210 .
- the electronic apparatus with the above-described configuration uses the liquid crystal device 100 according to the embodiment described above, and thus it is possible to provide the projector 1000 having high reliability and excellent display characteristics.
- various electronic apparatuses such as a head-mounted display (HMD), a head-up display (HUD), a smart phone, an electronic view finder (EVF), a mobile phone, a mobile computer, a digital camera, a digital video camera, an in-vehicle apparatus, or an illumination apparatus can be used, in addition to the projector 1000 .
- HMD head-mounted display
- HUD head-up display
- EVF electronic view finder
- mobile phone a mobile computer
- digital camera a digital video camera
- in-vehicle apparatus an illumination apparatus
- the first transistor 301 of the pixel P disposed in the display region E is overlapped with the second light shielding layer 3 c 2 in a plan view, and thus it is possible to shield the first transistor 301 from light even in a case where light is incident to the display region E from the projector 1000 .
- the second transistor 302 of the peripheral circuit disposed in the peripheral region E 1 is overlapped with the first light shielding layer 3 c 1 in a plan view, and thus it is possible to shield light even in a case where light that is leaked from the outside is incident to the peripheral region. Therefore, it is possible to shield light without causing failure characteristics of the peripheral circuit.
- the second light shielding layer 3 c 2 is disposed in the layer closer to the first transistor 301 than the first light shielding layer 3 c 1 , and thus it is possible to further prevent light from being incident to the first transistor 301 in the light transmission region. Further, it is possible to shield light at the position close to the first transistor 301 , thereby improving the light shielding properties of light that is incident at an angle.
- tungsten silicide having a light reflection property is used in the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 , and thus it is possible to prevent the first transistor 301 and the second transistor 302 (further, liquid crystal device 100 ) from heating.
- the liquid crystal device 100 is provided, and thus it is possible to provide the electronic apparatus having an excellent display quality.
- FIG. 9 is a schematic sectional view illustrating the configuration of the light shielding layer of the display region.
- FIG. 10 is a schematic sectional view illustrating the configuration of the light shielding layer of the peripheral region.
- the liquid crystal device 200 according to the second embodiment is mainly similar to the liquid crystal device 100 according to the first embodiment, except that the two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are disposed in the display region E. For this reason, in the second embodiment, the part different from the first embodiment will be described in detail, and the detailed description of the other parts overlapped with the first embodiment will be omitted.
- the first light shielding layer 3 c 1 , the first insulating layer 11 a , the second light shielding layer 3 c 2 , the second insulating layer 11 b , and the semiconductor layer 30 a 1 are stacked in this order from the first base material 10 a side.
- the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are disposed so as to overlap with the semiconductor layer 30 a 1 in a plan view.
- the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are disposed so as to overlap with at least the LDD region of the semiconductor layer 30 a 1 in a plan view.
- the first light shielding layer 3 c 1 , the first insulating layer 11 a , the second insulating layer 11 b , and the semiconductor layer 30 a 2 are stacked in this order from the first base material 10 a side.
- the first light shielding layer 3 c 1 is disposed so as to overlap with the semiconductor layer 30 a 2 in a plan view.
- the first light shielding layer 3 c 1 is disposed so as to overlap with at least the LDD region of the semiconductor layer 30 a 2 in a plan view.
- the first transistor 301 of the display region E is disposed so as to overlap with the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 in a plan view, and thus it is possible to improve the light shielding property, compared to a case where the first transistor is disposed so as to overlap with only the second light shielding layer 3 c 2 . In particular, it is possible to significantly improve the light shielding properties in the light transmission region.
- the first light shielding layer 3 c 1 provided in the peripheral region E 1 is disposed so as to overlap with the second transistor 302 in a plan view, as in the first embodiment.
- the first light shielding layer 3 c 1 can shield light leaked from the outside. Therefore, it is possible to prevent a change in characteristics of the transistor, for example.
- the following effects can be obtained, in addition to the effects according to the first embodiment.
- the first transistor 301 is disposed so as to overlap with the two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 in a plan view, and thus it is possible to prevent light of the projector 1000 from being incident to the first transistor 301 , thereby improving the light shielding property.
- FIG. 11 is a schematic plan view illustrating the configurations of the light shielding layer and the first transistor of the display region.
- FIG. 12 is a schematic sectional view illustrating the configurations of the light shielding layer and the first transistor of the display region.
- the liquid crystal device 300 according to the third embodiment is mainly similar to the liquid crystal device 200 according to the second embodiment, except that the two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are disposed in the display region E, and further that the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are electrically connected to the gate electrode 30 g .
- the part different from the second embodiment will be described in detail, and the description of the other parts overlapped with the second embodiment will be omitted.
- the first light shielding layer 3 c 1 , the first insulating layer 11 a , the second light shielding layer 3 c 2 , the second insulating layer 11 b , and the semiconductor layer 30 a 1 are stacked in this order from the first base material 10 a side.
- the gate electrode 30 g is disposed on the semiconductor layer 30 a 1 via the gate insulating layer 11 g.
- the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are electrically connected to the gate electrode 30 g via a contact hole CNT 11 .
- the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are electrically connected to the gate electrode 30 g via a contact hole CNT 12 .
- the configuration of the peripheral region E 1 is the same as that of the peripheral region E 1 in the first embodiment and the second embodiment.
- the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 , and the gate electrode 30 g are electrically connected to each other, and thus the potentials of the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are the same as that of the gate electrode, thereby improving the characteristics of the transistor.
- first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 can electrically connected to the gate electrode 30 g by using the one contact hole CNT 11 (or CNT 12 ), and thus it is possible to prevent a planar region from spreading, thereby maintaining an aperture ratio. Further, it is effective in narrowing the pitch between the pixels.
- the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are electrically connected to the gate electrode 30 g , and thus it is possible to prevent a change in characteristics of the transistor such as a potential change or a floating. Further, the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 are electrically connected to the gate electrode 30 g by using the one contact hole CNT 11 (or CNT 12 ), and thus it is possible to prevent a significant decrease in the aperture ratio. In addition, even in a case where the pitch between the pixels is narrowed, it is possible to effectively correspond to the case. Furthermore, it is unlikely to be restricted in layout.
- an active matrix type liquid crystal device that includes a thin film transistors (TFT) as a switching element of the pixel will be described as an example.
- the liquid crystal device can be preferably used, for example, as a light modulation element (liquid crystal light bulb) of a projection type display apparatus (projector) to be described later.
- FIG. 13 is a schematic plan view illustrating the configuration of the liquid crystal device according to the fourth embodiment.
- FIG. 14 is a schematic sectional view taken along line XIV-XIV in FIG. 13 .
- FIG. 15 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device according to the fourth embodiment.
- the liquid crystal device 501 includes an element substrate 510 , a counter substrate 520 disposed opposite to the element substrate 510 , and a liquid crystal layer 540 disposed between the element substrate 510 and the counter substrate 520 .
- the substrate 510 a as a first substrate that constitutes the element substrate 510 and the substrate 520 a as a second substrate that constitutes the counter substrate 520 , for example, the substrate that is made of a material having a light transmitting property such as glass or quartz can be used.
- the size of the element substrate 510 is further larger than that of the counter substrate 520 , and the two substrates are bonded to each other via sealing members 542 disposed in a frame shape.
- the space surrounded by the element substrate 510 , the counter substrate 520 , and the sealing members 542 is filled and sealed with liquid crystal having a positive or negative dielectric anisotropy, and thus the liquid crystal layer 540 is configured.
- the sealing member 542 is made of, for example, an adhesive such as thermosetting epoxy resin or ultraviolet-curable epoxy resin.
- the spacers (not illustrated) for maintaining the gap between the element substrate 510 and the counter substrate 520 with a constant value are mixed into the sealing member 542 .
- a frame-shaped light shielding layer 521 provided on the counter substrate 520 is disposed in the inside of the sealing member 542 disposed in a frame shape.
- the light shielding layer 521 is made of, for example, metal or metal oxide having a light shielding property.
- the inside of the light shielding layer 521 becomes the display region E in which a plurality of pixels P are arrayed.
- the display region E is a region that substantially contributes to display.
- a lattice-shaped light shielding portion for partitioning the plurality of pixels P in a plane is provided, for example, on the counter substrate 520 .
- the data line driving circuit 551 and the plurality of external connection terminals 554 are provided at the outside of the sealing member 542 on a first-direction side portion of the element substrate 510 along the first-direction side portion.
- the inspection circuit 553 is provided in the inside of the sealing member 542 along another first-direction side portion that is opposite to the first-direction side portion.
- the scanning line driving circuits 552 are provided in the inside of the sealing members 542 along second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other.
- a plurality of wirings 555 connecting the two scanning line driving circuits 552 are provided in the inside of the sealing member 542 on the first-direction side portion at which the inspection circuit 553 is provided.
- the wirings connected to the data line driving circuit 551 and the scanning line driving circuit 552 are connected to the plurality of external connection terminals 554 .
- the upper and lower conduction portions 556 for electrical conduction between the element substrate 510 and the counter substrate 520 are provided at the corner portions of the counter substrate 520 .
- the disposition of the inspection circuit 553 is not limited thereto, and the inspection circuit 553 may be provided at the position along the inside of the sealing member 542 between the data line driving circuit 551 and the display region E.
- the direction along the first-direction side portion at which the data line driving circuit 551 is provided is described as an X-direction
- the direction along the second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other is described as a Y-direction
- the direction of the line XIV-XIV in FIG. 13 is a direction along the Y-direction.
- the direction that is perpendicular to the X-direction and the Y-direction and directed toward the upward in FIG. 14 is described as a Z-direction.
- “in a plan view” denotes that it is seen from the normal direction (Z-direction) of the surface of the counter substrate 520 of the liquid crystal device 501 .
- TFTs 530 (refer to FIG. 15 ) as a switching element provided for each pixel P, pixel electrodes 515 having a light transmitting property, signal lines (not illustrated), and an alignment film 518 covering the pixel electrodes 515 are provided on the surface of the substrate 510 a on the liquid crystal layer 540 side.
- the pixel electrode 515 is made of a conductive film having a light transmitting property such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
- a light shielding configuration for preventing the switching operation from becoming unstable due to light incident to the semiconductor layer 530 a (refer to FIG. 17 ) of the TFT 530 is adopted.
- the light shielding configuration will be described later.
- the light shielding layer 521 , an interlayer 522 , a common electrode 523 , and an alignment film 524 covering the common electrode 523 are provided on the liquid crystal layer 540 side of the counter substrate 520 .
- the frame-shaped light shielding layer 521 is provided at the position overlapping with the scanning line driving circuits 552 , and the plurality of wirings 555 or the inspection circuit 553 in a plan view.
- the light shielding layer 521 shields light incident from the counter substrate 520 side, thereby preventing the malfunction of the peripheral circuit including the driving circuits due to light.
- the light shielding layer 521 ensures high contrast in the display of the display region E by shielding unnecessary stray light so as not to be incident to the display region E.
- the interlayer 522 illustrated in FIG. 14 is formed to cover the light shielding layer 521 .
- the interlayer 522 is formed of, for example, an insulating film such as silicon oxide (SiO 2 ), and has a light transmitting property.
- the interlayer 522 is provided to planarize the surface of the liquid crystal layer 540 side on which the common electrode 523 is formed, by reducing unevenness caused by the light shielding layer 521 or the like.
- a method of forming the interlayer 522 for example, a film forming method using a plasma chemical vapor deposition (CVD) method or the like can be used.
- CVD plasma chemical vapor deposition
- the common electrode 523 is made of, for example, a conductive film having a light transmitting property, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
- ITO Indium Tin Oxide
- IZO Indium Zinc Oxide
- the common electrode 523 covers the interlayer 522 , and is electrically connected to the wiring on element substrate 510 side by the upper and lower conduction portions 556 provided at the four corners of the counter substrate 520 , as illustrated in FIG. 13 .
- the alignment film 518 and the alignment film 524 are selected based on the optical design of the liquid crystal device 501 .
- an alignment film that is formed using an organic material such as polyimide and subjected to a substantially horizontal alignment treatment to the liquid crystal molecules by rubbing the surface of the film or an alignment film that is formed using an inorganic material such as SiO x (silicon oxide) by a vapor phase growth method and subjected to a substantially vertical alignment treatment to the liquid crystal molecules, can be used.
- the liquid crystal included in the liquid crystal layer 540 modulates light to allow a gradation display by the change in the alignment or the order of molecular aggregates according to the applied voltage level. For example, in a case of a normally white mode, the transmittance of incident light decreases according to the voltage applied to each pixel P. In a case of a normally black mode, the transmittance of incident light increases according to the voltage applied to each pixel P. Thus, light having contrast according to the image signal is emitted from the liquid crystal device 501 as a whole.
- gate wirings (scanning lines) 503 a and data lines 506 a are formed so as to be insulated and intersected with each other.
- the direction to which the gate wirings 503 a are extended is the X-direction, and the direction to which the data lines 506 a are extended is the Y-direction.
- the pixels P are provided to correspond to the intersections of the gate wirings 503 a and the data lines 506 a .
- a pixel electrode 515 In each pixel P, a pixel electrode 515 , and a thin film transistor (TFT) 530 as a switching element are provided.
- TFT thin film transistor
- the source electrode 531 (refer to FIG. 16 ) of the TFT 530 is electrically connected to the data line 506 a .
- the data line 506 a is connected to the data line driving circuit 551 (refer to FIG. 13 ), and supplies the image signal (data signal) S 1 , S 2 , . . . , Sn supplied from the data line driving circuit 551 to the pixel P.
- the image signal S 1 , S 2 , . . . , Sn supplied from the data line driving circuit 551 to the data line 506 a may be line-sequentially supplied in this order, or may be supplied for each group with a plurality of data lines 506 a adjacent to each other.
- the gate electrode 530 g (refer to FIG. 16 ) of the TFT 530 is electrically connected to the gate wiring (scanning line) 503 a .
- the gate electrode 530 g is a part of the gate wiring (scanning line) 503 a .
- the gate wiring (scanning line) 503 a is connected to the scanning line driving circuit 552 (refer to FIG. 13 ), and supplies the scanning signals G 1 , G 2 , . . . , Gm supplied from the scanning line driving circuit 552 to each pixel P.
- the scanning line driving circuit 552 line-sequentially supplies the scanning signals G 1 , G 2 , . . . , Gm to the gate wiring (scanning line) 503 a using a pulse at a predetermined timing.
- the drain electrode 532 (refer to FIG. 16 ) of the TFT 530 is electrically connected to the pixel electrode 515 .
- the TFT 530 is in a turned-on state only for a certain period, and thus the image signals S 1 , S 2 , . . . , Sn are written to the pixel electrode 515 via the data line 506 a at a predetermined timing.
- the image signals with a predetermined level that are written to the liquid crystal layer 540 via the pixel electrode 515 are held for a certain period in the liquid crystal capacitor formed between the pixel electrode 515 and the common electrode 523 (refer to FIG. 14 ) provided on the counter substrate 520 .
- a storage capacitor 516 is formed between a capacitor line 516 a and the pixel electrode 515 that are formed so as to parallel to the data line 506 a along the data line 506 a , and disposed parallel to the liquid crystal capacitor.
- the alignment state of the liquid crystal is changed according to the applied voltage level. Accordingly, light incident to the liquid crystal layer 540 (refer to FIG. 14 ) is modulated, and thus gradation display can be realized.
- the data line 506 a is connected to the inspection circuit 553 illustrated in FIG. 13 .
- the inspection circuit 553 is configured to check the operation defect or the like of the liquid crystal device 501 , by detecting the image signals in the process of manufacturing the liquid crystal device 501 .
- the inspection circuit 553 is not illustrated in the equivalent circuit diagram of FIG. 15 .
- the inspection circuit 553 may include a sampling circuit for sampling the image signal and supplying the image signal subjected to the sampling to the data line 506 a , and a precharge circuit for supplying a precharge signal with a predetermined voltage level to the data line 506 a prior to the image signal.
- FIG. 16 is a schematic sectional view illustrating the configuration of an element substrate of the liquid crystal device according to the fourth embodiment.
- the element substrate 510 includes a substrate 510 a as a first substrate, a lower light shielding layer 503 b as a first light shielding layer, an interlayer insulating layer 511 a as a first insulating layer, an upper light shielding layer 503 c as a second light shielding layer, an interlayer insulating layer 511 b as a second insulating layer, a TFT 530 , a data line 506 a , a storage capacitor 516 , and a pixel electrode 515 .
- the lower light shielding layer 503 b is formed on the substrate 510 a .
- the lower light shielding layer 503 b is made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, a nitride, or a material obtained by stacking the above-mentioned material that includes at least one of metals such as aluminum (Al), titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), or molybdenum (Mo).
- the lower light shielding layer 503 b has a conductivity and a light shielding property.
- the thickness of the lower light shielding layer 503 b is, for example, approximately 200 nm.
- the interlayer insulating layer 511 a is formed so as to cover the substrate 510 a and the lower light shielding layer 503 b .
- the interlayer insulating layer 511 a is made of, for example, a silicon oxide film or the like.
- the thickness of the interlayer insulating layer 511 a is, for example, approximately 400 nm to 5300 nm.
- the upper light shielding layer 503 c is formed on the interlayer insulating layer 511 a .
- the upper light shielding layer 503 c is made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, a nitride, or a material obtained by stacking the above-mentioned material that includes at least one of the same metals as the lower light shielding layer 503 b .
- the upper light shielding layer 503 c has a conductivity and a light shielding property.
- the thickness of the upper light shielding layer 503 c is, for example, approximately 100 nm.
- the lower light shielding layer 503 b and the upper light shielding layer 503 c shield light incident from the substrate 510 a side, and function as a scanning line.
- the interlayer insulating layer 511 b is formed so as to cover the interlayer insulating layer 511 a and the upper light shielding layer 503 c .
- the interlayer insulating layer 511 b is made of, for example, a silicon oxide film or the like.
- the thickness of the interlayer insulating layer 511 b is, for example, approximately 5300 nm to 400 nm.
- the TFT 530 is provided on the interlayer insulating layer 511 b .
- the TFT 530 includes the semiconductor layer 530 a , a gate insulating layer 511 c , the gate electrode 530 g , the source electrode 531 , and the drain electrode 532 .
- the semiconductor layer 530 a is formed in an island shape on the interlayer insulating layer 511 b .
- the semiconductor layer 530 a is made of, for example, a polycrystalline silicon film, and N-type impurity ions such as phosphorus (P) ions are implanted to the semiconductor layer 530 a.
- the semiconductor layer 530 a has a lightly doped drain (LDD) structure that includes a data line side source-drain region 530 s (hereinafter, referred to as a source region), a pixel electrode side source-drain region 530 d (hereinafter, referred to as a drain region), a channel region 530 c , a data line side LDD region 530 e provided between the source region 530 s and the channel region 530 c , and a pixel electrode side LDD region 530 f provided between the channel region 530 c and the drain region 530 d .
- the thickness of the semiconductor layer 530 a is, for example, approximately 50 nm.
- the TFT 530 is formed as an N-type TFT.
- the gate insulating layer 511 c is formed so as to cover the interlayer insulating layer 511 b and the semiconductor layer 530 a .
- the gate insulating layer 511 c is made of, for example, a silicon oxide film or the like.
- the gate electrode 530 g is formed on the gate insulating layer 511 c so as to be opposed to the channel region 530 c with the gate insulating layer 511 c interposed therebetween.
- the gate electrode 530 g (gate wiring 503 a ) is made of, for example, a polycrystalline silicon film.
- the interlayer insulating layer 511 d is formed so as to cover the gate insulating layer 511 c and the gate electrode 530 g .
- the interlayer insulating layer 511 d is made of, for example, a silicon oxide film or the like.
- a contact hole CH 501 penetrating the interlayer insulating layer 511 d and the gate insulating layer 511 c is formed at the position overlapped with the end portion of the source region 530 s side of the semiconductor layer 530 a .
- a contact hole CH 502 penetrating the interlayer insulating layer 511 d and the gate insulating layer 511 c is formed at the position overlapped with the end portion of the drain region 530 d side.
- the data line 506 a and a relay electrode 506 b are formed on the interlayer insulating layer 511 d .
- the data line 506 a and the relay electrode 506 b are made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, a nitride, or a material obtained by stacking the above-mentioned material that includes at least one of metals such as Al, Ti, Cr, W, Ta, or Mo.
- the data line 506 a and the relay electrode 506 b have conductivity and a light shielding property.
- the data line 506 a and the relay electrode 506 b is obtained, for example, by forming a conductive film using the same material and patterning the conductive film.
- the source electrode 531 is formed by filling the contact hole CH 501 with the material forming the data line 506 a and the relay electrode 506 b
- the drain electrode 532 is formed by filling the contact hole CH 502 .
- An interlayer insulating layer 511 e is formed so as to cover the data line 506 a , the relay electrode 506 b , and the interlayer insulating layer 511 d .
- the interlayer insulating layer 511 e is made of, for example, a silicon oxide or a silicon nitride.
- the interlayer insulating layer 511 e is subjected to a planarization process for planarizing the unevenness of the surface that is caused by covering the region in which the TFT 530 is provided.
- a method for the planarization process for example, a chemical mechanical polishing (CMP) process, a spin coating process, or the like may be used.
- CMP chemical mechanical polishing
- a contact hole CH 503 penetrating the interlayer insulating layer 511 e is formed at the position overlapped with the relay electrode 506 b .
- the capacitor line 516 a constituting a part of the storage capacitor 516 (COM potential) is formed on the interlayer insulating layer 511 e .
- the capacitor line 516 a has a multilayer structure in which, for example, an aluminum (Al) film is disposed in the lower layer and a titanium nitride (TiN) film is disposed in the upper layer.
- a capacitor insulating film 516 b that is made of an alumina film, silicon nitride film, or the like is formed so as to cover the capacitor line 516 a .
- a stopper film 516 c 1 that is made of a silicon oxide film or the like is formed on the capacitor insulating film 516 b in the vicinity of the region overlapped with the region of a contact hole CH 504 in a plan view.
- the stopper film 516 c 1 may be formed, before forming the capacitor insulating film 516 b , that is, between the capacitor line 516 a and the capacitor insulating film 516 b.
- a capacitor electrode 516 c constituting a part of the storage capacitor 516 is formed on the stopper film 516 c 1 , the capacitor insulating film 516 b , and the interlayer insulating layer 511 e so as to overlap the relay electrode 506 b in a plan view.
- the capacitor electrode 516 c is formed by forming a conductive film using a conduction portion material having light shielding properties such as aluminum (Al) and patterning the conductive film.
- the capacitor electrode 516 c is patterned on the stopper film 516 c 1 so as to be separated from the adjacent capacitor electrode 516 c.
- the capacitor electrode 516 c is also formed in the contact hole CH 503 .
- the capacitor electrode 516 c is electrically connected to the relay electrode 506 b via the contact hole CH 503 , and electrically connected to the drain electrode 532 .
- the capacitor electrode 516 c also functions as a relay electrode that electrically connects the relay electrode 506 b to the pixel electrode 515 via the contact hole CH 503 .
- An interlayer insulating layer 511 f is formed on the capacitor electrode 516 c .
- the interlayer insulating layer 511 f is made of, for example, silicon oxide or silicon nitride.
- the interlayer insulating layer 511 f also may be subjected to a planarization process as in the interlayer insulating layer 511 e .
- the contact hole CH 504 penetrating the interlayer insulating layer 511 f is formed at the position overlapped with the capacitor electrode 516 c .
- the contact hole CH 504 is formed, for example, on the capacitor electrode 516 c at the position overlapped with the stopper film 516 c 1 in a plan view.
- the pixel electrode 515 is formed on the interlayer insulating layer 511 f so as to overlap with the capacitor electrode 516 c and the contact hole CH 504 in a plan view.
- the pixel electrode 515 is formed with a transparent conductive film such as ITO, and also formed in the contact hole CH 504 .
- the pixel electrode 515 is electrically connected to the capacitor electrode 516 c via the contact hole CH 504 , and electrically connected to the drain electrode 532 via the contact hole CH 503 and the relay electrode 506 b.
- the liquid crystal device 501 illustrated in FIG. 14 is used as the liquid crystal light bulb of the projector
- light that is emitted from the light source is incident from the counter substrate 520 side, transmitted through the liquid crystal layer 540 , and emitted to the element substrate 510 side.
- the capacitor electrode 516 c , the data line 506 a , and the relay electrode 506 b shield light that is incident to the semiconductor layer 530 a from the counter substrate 520 side (upper side in FIG. 16 ), thereby preventing the malfunction of the TFT 530 due to light.
- the liquid crystal device 501 has a light shielding configuration for shielding light incident from the element substrate 510 side (back side), and thus the wiring resistance of the scanning line decreases by the light shielding configuration.
- the light shielding configuration of the liquid crystal device 501 will be described with reference to FIGS. 17 and 18 .
- FIG. 17 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the fourth embodiment.
- FIG. 18 is a schematic sectional view taken along line XVIII-XVIII in FIG. 17 .
- the line XVIII-XVIII in FIG. 17 is a line along the X-direction intersecting the direction to which the semiconductor layer 530 a extends.
- the components in the higher layers than the gate electrode 530 g gate wiring 503 a ) are not illustrated.
- the intersection portion of the gate wiring 503 a extending along the X-direction and the data line 506 a (refer to FIG. 15 ) extending along the Y-direction is illustrated in FIG. 17 .
- the semiconductor layer 530 a of the TFT 530 extends to the both sides of the intersection portion of the gate wiring 503 a and the data line 506 a along the Y-direction.
- the semiconductor layer 530 a is disposed so as to overlap with the data line 506 a in a plan view.
- the portion of the gate wiring 503 a that is overlapped with the channel region 530 c of the semiconductor layer 530 a in a plan view becomes the gate electrode 530 g .
- the gate electrode 530 g overlaps with the channel region 530 c of the semiconductor layer 530 a in a plan view.
- the lower light shielding layer 503 b and the upper light shielding layer 503 c are disposed so as to overlap with the gate wiring 503 a in a plan view, and provided between the pixels P (refer to FIG. 13 ) in the X-direction.
- the lower light shielding layer 503 b and the upper light shielding layer 503 c are disposed at the intersection portion of the gate wiring 503 a and the data lines 506 a so as to overlap with at least the channel region 530 c of the semiconductor layer 530 a in a plan view.
- the TFT 530 is provided in the vicinity of the intersection portion of the non-opening region between the pixels P that has a light shielding property, and thus it is possible to prevent the malfunction of the TFT 530 due to light, and ensure the aperture ratio of the opening region of the pixel P.
- a contact hole CH 505 as a third contact hole penetrating the gate insulating layer 511 c and the interlayer insulating layer 511 b , and a contact hole CH 506 as a fourth contact hole are formed at both outsides of the semiconductor layer 530 a (channel region 530 c ) in the X-direction.
- the contact holes CH 505 and CH 506 are filled with the material forming the gate electrode 530 g (gate wiring 503 a ), and thus the gate electrode 530 g (gate wiring 503 a ) is electrically connected to the upper light shielding layer 503 c.
- a contact hole CH 507 as a first contact hole penetrating the interlayer insulating layer 511 a , and a contact hole CH 508 as a second contact hole are formed at both outsides of the semiconductor layer 530 a (channel region 530 c ) in the X-direction.
- the contact hole CH 507 is disposed at a further outside of the semiconductor layer 530 a than the contact hole CH 505
- the contact hole CH 508 is disposed at a further outside of the semiconductor layer 530 a than the contact hole CH 506 .
- the contact holes CH 507 and CH 508 are filled with the material forming the upper light shielding layer 503 c , and thus the upper light shielding layer 503 c that is electrically connected to the gate electrode 530 g (gate wiring 503 a ) is electrically connected to the lower light shielding layer 503 b .
- both of the upper light shielding layer 503 c and the lower light shielding layer 503 b are set to the same potential as that of the gate electrode 530 g . Therefore, the scanning line is configured with the three layers of the gate wiring 503 a , the upper light shielding layer 503 c , and the lower light shielding layer 503 b.
- the positions of the contact holes CH 507 and CH 508 are not particularly limited. However, there is a case where a recess occurs at the positions of the contact holes CH 507 and CH 508 on the surface of the upper light shielding layer 503 c . Therefore, it is preferably that the contact holes CH 507 and CH 508 are disposed so as not to overlap with the upper contact holes CH 505 and CH 506 in a plan view.
- the upper light shielding layer 503 c and the lower light shielding layer 503 b are disposed between the semiconductor layer 530 a and the substrate 510 a so as to overlap with the semiconductor layer 530 a in a plan view. Therefore, it is possible to shield light incident to the semiconductor layer 530 a from the substrate 510 a side.
- FIG. 19 is a graph illustrating the light shielding effect of the element substrate according to the fourth embodiment.
- FIG. 27 is a schematic plan view illustrating a configuration example of the TFT portion of the element substrate of the related art.
- FIG. 28 is a schematic sectional view taken along line XXVIII-XXVIII in FIG. 27 .
- the components in the higher layers than the gate electrode 530 g are not illustrated.
- the element substrate 560 of the related art illustrated in FIGS. 27 and 28 is different from the element substrate 510 according to the fourth embodiment in that the light shielding layer disposed between the semiconductor layer 530 a and the substrate 510 a has a single layer (only the lower light shielding layer 503 b ).
- the thickness of the lower light shielding layer 503 b is approximately 200 nm, similarly to the element substrate 510 .
- the lower light shielding layer 503 b is electrically connected to the gate electrode 530 g (gate wiring 503 a ) via the contact holes CH 505 and CH 506 .
- the scanning line is configured with the two layers of the gate wiring 503 a and the lower light shielding layer 503 b.
- a part of incident light L that is incident at an angle with respect to the normal direction of the substrate 510 a (Z-direction) from the substrate 510 a side is reflected at the interface between the substrate 510 a and the lower light shielding layer 503 b .
- Another part of incident light L is absorbed into the lower light shielding layer 503 b and transmitted through the lower light shielding layer 503 b .
- a part of the transmitted light is incident to the channel region 530 c of the semiconductor layer 530 a .
- FIG. 28 a part of incident light L that is incident at an angle with respect to the normal direction of the substrate 510 a (Z-direction) from the substrate 510 a side is reflected at the interface between the substrate 510 a and the lower light shielding layer 503 b .
- Another part of incident light L is absorbed into the lower light shielding layer 503 b and transmitted through the lower light shielding layer 503 b .
- a part of the transmitted light is incident to the channel region
- incident light L incident from the substrate 510 a side is reflected at the interface between the substrate 510 a and the lower light shielding layer 503 b . Further, a part of light that is transmitted through the lower light shielding layer 503 b is reflected at the interface between the interlayer insulating layer 511 a and the upper light shielding layer 503 c . Therefore, it is possible to more effectively shield light incident to the channel region 530 c of the semiconductor layer 530 a.
- the horizontal axis represents the wavelength (nm) of incident light L
- the vertical axis represents the transmittance (%) of incident light L transmitted through the light shielding layer.
- the light shielding layer with a single layer (film thickness of 200 nm) illustrated in FIG. 19 represents the transmittance according to the configuration of the element substrate 560
- the two layers of the light shielding layer (film thickness of 100 nm+200 nm) represents the transmittance according to the configuration of the element substrate 510 of the fourth embodiment.
- the two layers of the light shielding layer (film thickness of 100 nm+100 nm) represents the transmittance according to a comparative example in which the thickness of the lower light shielding layer 503 b in the element substrate 510 is set to 100 nm.
- the transmittance according the configuration of the element substrate 510 of the fourth embodiment remarkably decreases, compared to the transmittance according to the configuration of the element substrate 560 in the related art.
- the transmittance according to the comparative example decreases, compared to the transmittance according to the configuration of the element substrate 560 in the related art.
- the two layers of the light shielding layer that have the interlayer insulating layer (interlayer insulating layer 511 a ) interposed therebetween is provided, and thus the reflection at the interface increases, thereby improving the light shielding properties compared to the related art.
- the range of the horizontal axis is set to substantially the center of a visible light wavelength region, the magnitude relationship in the transmittance is substantially the same in the entire visible light wavelength region.
- the thickness of the lower light shielding layer 503 b and the thickness of the upper light shielding layer 503 c are set to 200 nm (two layers of 200 nm+200 nm), the light shielding properties are expected to be further improved.
- the step that occurs in the upper layer due to the two layers of the light shielding layer becomes larger, and thus it is preferably that the thickness of the upper light shielding layer 503 c is set to 100 nm.
- the scanning line is configured with the two layers of the gate wiring 503 a and the lower light shielding layer 503 b .
- the scanning line is configured with the three layers of the gate wiring 503 a , the lower light shielding layer 503 b , and the upper light shielding layer 503 c , and thus it is possible to decrease the wiring resistance of the scanning line, compared to the related art. Therefore, even when the liquid crystal device 501 is a large liquid crystal device that is driven by a high frequency driving signal, it is possible to decrease the wiring resistance of the scanning line, while improving the light shielding properties of incident light L incident from the substrate 510 a side, compared to the related art.
- the lower light shielding layer 503 b and the upper light shielding layer 503 c are provided straddling the boundary between the pixels P, and thus the contact holes CH 507 and CH 508 for electrically connecting the lower light shielding layer 503 b and the upper light shielding layer 503 c may not be provided for each pixel P.
- the number of the contact holes CH 507 and CH 508 may be less than the number of the pixels P.
- the lower light shielding layer 503 b , the interlayer insulating layer 511 a , and the upper light shielding layer 503 c are disposed between the substrate 510 a and the semiconductor layer 530 a .
- incident light L incident from the substrate 510 a side toward the semiconductor layer 530 a side is reflected at the interface between the substrate 510 a and the lower light shielding layer 503 b , and further reflected at the interface between the interlayer insulating layer 511 a and the upper light shielding layer 503 c . Therefore, it is possible to effectively shield incident light L incident from the substrate 510 a side to the semiconductor layer 530 a .
- the lower light shielding layer 503 b and the upper light shielding layer 503 c are set to have the same potential as that of the gate electrode 530 g , and thus it is possible to configure the scanning line using the three layers that includes the two layers of the gate wiring 503 a and the light shielding layer, thereby decreasing the wiring resistance of the scanning line. As a result, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding properties compared to the related art, thereby providing the liquid crystal device 501 having a high display quality.
- the lower light shielding layer 503 b and the upper light shielding layer 503 c that constitute the scanning line are formed straddling the boundary between the pixels P, and thus, even in a case where the liquid crystal device 501 is a large liquid crystal device including the scanning line with a long length, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding property.
- the pair of the light shielding portions along the Z-direction are formed between the lower light shielding layer 503 b and the upper light shielding layer 503 c by the contact holes CH 507 and CH 508 penetrating the interlayer insulating layer 511 a .
- the pair of the light shielding portions are disposed at both sides of the semiconductor layer 530 a in a plan view.
- the pair of light shielding portions along the Z-direction are formed by the contact holes CH 505 and CH 506 penetrating the gate insulating layer 511 c and the interlayer insulating layer 511 b .
- the pair of light shielding portions are disposed at both outsides of the semiconductor layer 530 a in a plan view. Therefore, it is possible to shield incident light L that is incident at an angle with respect to the Z-direction from the substrate 510 a side, and light reflected and propagated between the gate wiring 503 a and the upper light shielding layer 503 c , from both outsides of the semiconductor layer 530 a , by the light shielding portions formed by the contact holes CH 505 and CH 506 , thereby further improving the light shielding property.
- FIG. 20 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the fifth embodiment.
- FIG. 21 is a schematic sectional view taken along line XXI-XXI in FIG. 20 .
- the element substrate 510 A according to the fifth embodiment has the same configuration as that of the element substrate 510 according to the fourth embodiment, except that the upper light shielding layer 503 d as a second light shielding layer is formed to be separated for each pixel P.
- the differences from the fourth embodiment will be described.
- the same reference numerals are given to the same components as those of the fourth embodiment, and detailed description thereof will be omitted.
- the element substrate 510 A according to the fifth embodiment is provided with the lower light shielding layer 503 b , the interlayer insulating layer 511 a , and the upper light shielding layer 503 d , between the substrate 510 a and the semiconductor layer 530 a .
- the upper light shielding layer 503 c is provided straddling the boundary between the pixels P in the X-direction.
- the upper light shielding layer 503 d is provided to be separated for each pixel P, and the lower light shielding layer 503 b is formed straddling the boundary between the pixels P.
- the upper light shielding layer 503 d according to the fifth embodiment is formed of the same material as that of the upper light shielding layer 503 c according to the fourth embodiment, and formed to have the same thickness as that of the upper light shielding layer 503 c according to the fourth embodiment.
- the upper light shielding layer 503 d is electrically connected to the lower light shielding layer 503 b via the contact holes CH 507 and CH 508 penetrating the interlayer insulating layer 511 a .
- the contact hole CH 507 is disposed at a further outside of the semiconductor layer 530 a than the contact hole CH 505
- the contact hole CH 508 is disposed at a further outside of the semiconductor layer 530 a than the contact hole CH 506 .
- the configuration of the element substrate 510 A of the fifth embodiment even though the upper light shielding layer 503 d is separated for each pixel P, the lower light shielding layer 503 b , the interlayer insulating layer 511 a , and the upper light shielding layer 503 d are disposed between the substrate 510 a and the semiconductor layer 530 a , and thus it is possible to improve the light shielding properties compared to the related art, similarly to the fourth embodiment. Even in a case where, as in the element substrate 560 in the related art that is illustrated in FIGS. 27 and 28 , only the lower light shielding layer 503 b is disposed between the substrate 510 a and the semiconductor layer 530 a , it is possible to decrease the wiring resistance of the scanning line.
- the configuration according to the fifth embodiment can be applied to a case where the size of the liquid crystal device 501 is small and decreasing the wiring resistance of the scanning line is not important.
- the upper light shielding layer 503 d is separated for each pixel P, the lower light shielding layer 503 b , the interlayer insulating layer 511 a , and the upper light shielding layer 503 d are disposed between the substrate 510 a and the semiconductor layer 530 a , and thus it is possible to improve the light shielding properties compared to the related art, similarly to the fourth embodiment. Further, it is possible to decrease the wiring resistance of the scanning line.
- FIG. 22 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the sixth embodiment.
- FIG. 23 is a schematic sectional view taken along line XXIII-XXIII in FIG. 22 .
- the element substrate 510 B according to the sixth embodiment is similar to the element substrate 510 A according to the fifth embodiment, in that the upper light shielding layer 503 e as a second light shielding layer is formed to be separated for each pixel P.
- the element substrate 510 B according to the sixth embodiment is different from the element substrate 510 A according to the fifth embodiment, in that the contact holes CH 505 and CH 506 are disposed so as to overlap with the contact holes CH 507 and CH 508 in a plan view.
- the same reference numerals are given to the same components as those of the above-described embodiment, and detailed description thereof will be omitted.
- the element substrate 510 B according to the sixth embodiment is provided with the lower light shielding layer 503 b , the interlayer insulating layer 511 a and the upper light shielding layer 503 e , between the substrate 510 a and the semiconductor layer 530 a .
- the contact holes CH 507 and CH 508 is formed in the interlayer insulating layer 511 a , and a recess portion 534 recessed from the surface (upper surface) is formed in the region including the contact holes CH 507 and CH 508 .
- the upper light shielding layer 503 e according to the sixth embodiment is formed of the same material as that of the upper light shielding layer 503 c according to the fourth embodiment, and formed to have the same thickness as that of the upper light shielding layer 503 c according to the fourth embodiment.
- the upper light shielding layer 503 e is separated for each pixel P, and formed so as to fill the recess portion 534 and the contact holes CH 507 and CH 508 that are provided in the interlayer insulating layer 511 a .
- the surface of the upper light shielding layer 503 e is a substantially flat surface that also includes the positions of the contact holes CH 507 and CH 508 .
- the surface of the upper light shielding layer 503 e and the surface of the interlayer insulating layer 511 a form a substantially flat surface.
- the upper light shielding layer 503 e is electrically connected to the lower light shielding layer 503 b via the contact holes CH 507 and CH 508 .
- the element substrate 510 B according to the sixth embodiment can be manufactured as follows. After forming the contact holes CH 507 and CH 508 in the interlayer insulating layer 511 a , the recess portion 534 is formed by etching the interlayer insulating layer 511 a from the surface side. Then, the material of the upper light shielding layer 503 e is placed so as to fill the recess portion 534 and the contact holes CH 507 and CH 508 , and the upper light shielding layer 503 e is patterned. Then, a planarization process for planarizing the surface of the upper light shielding layer 503 e and the surface of the interlayer insulating layer 511 a is performed.
- the contact hole CH 507 is disposed so as to overlap with the contact hole CH 505 in a plan view
- the contact hole CH 508 is disposed so as to overlap with the contact hole CH 506 in a plan view.
- the surface of the upper light shielding layer 503 e is a substantially flat surface, and thus the positions of the contact holes CH 505 and CH 506 to be formed on the upper layer of the upper light shielding layer 503 e are not restricted. In other words, the positions of the contact holes CH 507 and CH 508 are not restricted with respect to the positions of the contact holes CH 505 and CH 506 .
- the configuration of the element substrate 510 B according to the sixth embodiment is suitable in a case where the liquid crystal device 501 is a small high-definition liquid crystal device in which the arrangement pitch of the pixels P is narrow.
- the surface of the upper light shielding layer 503 e and the surface of the interlayer insulating layer 511 a are a substantially flat surface, and thus it is possible to decrease the step that occurs in the upper layer due to the thickness of the upper light shielding layer 503 e.
- the upper light shielding layer 503 e is separated for each pixel P, the lower light shielding layer 503 b , the interlayer insulating layer 511 a , and the upper light shielding layer 503 e are disposed between the substrate 510 a and the semiconductor layer 530 a , and thus it is possible to improve the light shielding properties compared to the related art, similarly to the fourth embodiment. Further, it is possible to decrease the wiring resistance of the scanning line.
- the upper light shielding layer 503 e having a substantially flat surface is formed on the interlayer insulating layer 511 a by filling the pair of the contact holes CH 507 and CH 508 penetrating the interlayer insulating layer 511 a . Therefore, in a case of forming the contact holes CH 505 and CH 506 for electrical connection from the upper side to the upper light shielding layer 503 e , the positions of the contact holes CH 505 and CH 506 are not restricted, and thus it is possible to increase the degree of freedom in the wiring pattern design.
- the pair of the contact holes CH 507 and CH 508 that penetrate the interlayer insulating layer 511 a and electrically connect the lower light shielding layer 503 b and the upper light shielding layer 503 e are disposed so as to overlap with the pair of the contact holes CH 505 and CH 506 that penetrate the gate insulating layer 511 c and the interlayer insulating layer 511 b and electrically connect the gate electrode 530 g and the upper light shielding layer 503 e in a plan view. Therefore, it is possible to reduce the size of the region that is shielded by the contact holes CH 505 , CH 506 , CH 507 and CH 508 , thereby improving the aperture ratio of the liquid crystal device 501 .
- FIG. 24 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the seventh embodiment.
- FIG. 25 is a schematic sectional view taken along line XXV-XXV in FIG. 24 .
- the line XXV-XXV in FIG. 24 is a line along the Y-direction to which the semiconductor layer 530 a extends.
- the element substrate 510 C according to the seventh embodiment is different from the element substrates 510 , 510 A, and 510 B according to the above-described embodiments, in that a contact hole CH 509 which penetrates the interlayer insulating layer 511 a and electrically connects the lower light shielding layer 503 b and an upper light shielding layer 503 f as a second light shielding layer is disposed at the position overlapped with the channel region 530 c of the semiconductor layer 530 a in a plan view.
- a contact hole CH 509 which penetrates the interlayer insulating layer 511 a and electrically connects the lower light shielding layer 503 b and an upper light shielding layer 503 f as a second light shielding layer is disposed at the position overlapped with the channel region 530 c of the semiconductor layer 530 a in a plan view.
- the element substrate 510 C according to the seventh embodiment is provided with the lower light shielding layer 503 b , the interlayer insulating layer 511 a , and the upper light shielding layer 503 f between the substrate 510 a and the semiconductor layer 530 a .
- the upper light shielding layer 503 f according to the seventh embodiment is formed of the same material as that of the upper light shielding layer 503 c according to the fourth embodiment, and formed to have the same thickness as that of the upper light shielding layer 503 c according to the fourth embodiment.
- the contact holes CH 505 and CH 506 are disposed at both outsides of the semiconductor layer 530 a in a plan view (refer to FIG. 24 ), similarly to the fourth embodiment.
- a through hole 535 (contact hole CH 509 as a fifth contact hole) is provided at the position overlapped with the channel region 530 c of the semiconductor layer 530 a in a plan view. It is preferably that the through hole 535 is formed in a region that includes the channel region 530 c of the semiconductor layer 530 a and is wider than the channel region 530 c in the X-direction and the Y-direction.
- the length of the through hole 535 along the Y-direction is, for example, approximately 2 ⁇ m, and the depth of the through hole 535 is, for example, approximately 0.5 ⁇ m.
- the through hole 535 is provided in the region overlapped with the lower light shielding layer 503 b in a plan view.
- the lower light shielding layer 503 b is exposed into the through hole 535 .
- the side portion (inclined surface) of the through hole 535 formed in the interlayer insulating layer 511 a is referred to as the side portion 535 b of the contact hole CH 509
- the surface of the lower light shielding layer 503 b exposed into the through hole 535 is referred to as the bottom portion 535 a of the contact hole CH 509 .
- the upper light shielding layer 503 f is disposed across the bottom portion 535 a of the contact hole CH 509 (the surface of the lower light shielding layer 503 b exposed into the through hole 535 ), the side portions 535 b of the contact hole CH 509 , and the surface of the interlayer insulating layer 511 a positioned at the outside of the contact hole CH 509 .
- the upper light shielding layer 503 f is electrically connected to the lower light shielding layer 503 b while being contact with the lower light shielding layer 503 b at the bottom portion 535 a of the contact hole CH 509 .
- the upper light shielding layer 503 f is formed in a recessed shape in a sectional view.
- the upper light shielding layer 503 f is disposed so as to cover the bottom portion 535 a of which the channel region 530 c of the semiconductor layer 530 a is disposed on the upper layer, the side portions 535 b , and the surface of the interlayer insulating layer 511 a at the outside of the side portion. Therefore, it is possible to effectively shield light incident to the channel region 530 c.
- the interlayer insulating layer 511 b is formed so as to cover the interlayer insulating layer 511 a and the upper light shielding layer 503 f .
- the thickness of the interlayer insulating layer 511 b formed on the interlayer insulating layer 511 a is approximately 5300 nm to 400 nm as described above, the thickness of the interlayer insulating layer 511 b at the side portion 535 b of the contact hole CH 509 is, for example, approximately 200 nm.
- the shape of the upper light shielding layer 503 f formed along the bottom portion 535 a and the side portions 535 b of the contact hole CH 509 is reflected in the surface of the interlayer insulating layer 511 b , and thus a recess portion 536 that includes a bottom portion 536 a corresponding to the bottom portion 535 a and side portions 536 b corresponding to the side portions 535 b , is formed on the surface side of the interlayer insulating layer 511 b .
- the length of the bottom portion 536 a along the Y-direction is, for example, approximately 1.5 ⁇ m.
- the semiconductor layer 530 a is disposed on the interlayer insulating layer 511 b so as to cover the upper light shielding layer 503 f along the bottom portion 536 a and the side portions 536 b of the recess portion 536 .
- the semiconductor layer 530 a is formed in a recessed shape in a sectional view, and thus it is possible to make the substantial length of the semiconductor layer 530 a longer than the length DD of the semiconductor layer 530 a in a plan view that is illustrated in FIG. 24 .
- the configuration of the element substrate 510 C according to the seventh embodiment is suitable in a case where the liquid crystal device 501 is a small high-definition liquid crystal device in which the arrangement pitch of the pixels P is narrow.
- the gate insulating layer 511 c is formed so as to cover the interlayer insulating layer 511 b and the semiconductor layer 530 a .
- the gate electrode 530 g is formed on the gate insulating layer 511 c so as to be opposed to the channel region 530 c .
- the shape of the recess portion 536 is also reflected in the surface of the gate insulating layer 511 c , and thus the gate electrode 530 g is also formed along the bottom portion 536 a and the side portions 536 b of the recess portion 536 . Accordingly, it is possible to reduce the width of the gate electrode 530 g in a plan view.
- the gate electrode 530 g is formed at both outsides of the semiconductor layer 530 a (channel region 530 c ) in the X-direction, and electrically connected to the upper light shielding layer 503 f via the contact holes CH 505 and CH 506 penetrating the gate insulating layer 511 c and the interlayer insulating layer 511 b (refer to FIG. 24 ).
- the channel region 530 c of the semiconductor layer 530 a is preferably disposed on the bottom portion 536 a of the recess portion 536 .
- the channel region 530 c is disposed on the bottom portion 536 a of the recess portion 536 , and thus it is possible to ensure the channel length of the channel region 530 c .
- the LDD region having a sufficient length. Therefore, even in a case where the liquid crystal device 501 is a small high-definition liquid crystal device in which the arrangement pitch of the pixels P is narrow, it is possible to form the TFT 530 having excellent operation characteristics.
- the diameter of the bottom portion 535 a of the contact hole CH 509 (through hole 535 ) formed in the lower side interlayer insulating layer 511 a is appropriately set such that the diameter of the bottom portion 536 a is equal to or greater than the desired channel length of the channel region 530 c.
- the upper light shielding layer 503 f is disposed across the bottom portion 535 a of the contact hole CH 509 penetrating the interlayer insulating layer 511 a , the side portions 535 b of the contact hole CH 509 , and the surface of the interlayer insulating layer 511 a at the outsides of the contact hole CH 509 .
- the semiconductor layer 530 a is disposed so as to cover the upper light shielding layer 503 f via the interlayer insulating layer 511 b . Therefore, it is possible to make the substantial length of the semiconductor layer 530 a longer than the length DD of the semiconductor layer in a plan view.
- At least the channel region 530 c of the semiconductor layer 530 a is disposed on the bottom portion 535 a of the contact hole CH 509 .
- the channel length of the channel region 530 c even in a case where the size of the liquid crystal device 501 is small, it is possible to ensure the channel length of the channel region 530 c .
- the data line side LDD region 530 e and the pixel electrode side LDD region 530 f are disposed at both outsides of the channel region 530 c , it is possible to dispose the data line side LDD region 530 e and the pixel electrode side LDD region 530 f in a region from the bottom portion 535 a to the outsides of the contact hole CH 509 via the side portions 535 b .
- the upper light shielding layer 503 f that is disposed in the lower layer of the semiconductor layer 530 a is disposed so as to cover the bottom portion 535 a of the contact hole on which the channel region 530 c is disposed, the side portions 535 b of the contact hole, and the surface of the interlayer insulating layer 511 a at the outsides of the contact hole CH 509 .
- the channel region 530 c is disposed so as to cover the bottom portion 535 a of the contact hole on which the channel region 530 c is disposed, the side portions 535 b of the contact hole, and the surface of the interlayer insulating layer 511 a at the outsides of the contact hole CH 509 .
- the configuration of the element substrate 510 C according to the seventh embodiment can be also applied to the fourth embodiment, the fifth embodiment, and the sixth embodiment.
- FIG. 26 is a schematic diagram illustrating the configuration of a projector as an electronic apparatus according to the eighth embodiment.
- the projector (projection type display apparatus) 2100 as an electronic apparatus according to the eighth embodiment includes a polarization illumination device 2110 , two dichroic mirrors 2104 and 2105 as a light separation element, three reflection mirrors 2106 , 2107 , and 2108 , five relay lenses 2111 , 2112 , 2113 , 2114 , and 2115 , three liquid crystal light bulbs 2121 , 2122 , and 2123 , a cross dichroic prism 2116 as a light synthesizing element, and a projection lens 2117 .
- the polarization illumination device 2110 includes a lamp unit 2101 as a light source that is configured by a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 2102 , and a polarization conversion element 2103 .
- the lamp unit 2101 , the integrator lens 2102 , and the polarization conversion element 2103 are disposed along the system optical axis Lx.
- the dichroic mirror 2104 reflects red light (R) among polarized light beams emitted from the polarization illumination device 2110 , and transmits green light (G) and blue light (B).
- Another dichroic mirror 2105 reflects the green light (G) transmitted through the dichroic mirror 2104 , and transmits the blue light (B).
- the red light (R) reflected by the dichroic mirror 2104 is reflected by the reflection mirror 2106 , and then incident to the liquid crystal light bulb 2121 via the relay lens 2115 .
- the green light (G) reflected by the dichroic mirror 2105 is incident to the liquid crystal light bulb 2122 via the relay lens 2114 .
- the blue light (B) transmitted through the dichroic mirror 2105 is incident to the liquid crystal light bulb 2123 via a light guide system that is configured by three relay lenses 2111 , 2112 , and 2113 and two reflection mirrors 2107 and 2108 .
- the projection type liquid crystal light bulbs 2121 , 2122 , and 2123 as a light modulation element are respectively disposed opposite to the incidence plane of each color light of the cross dichroic prism 2116 .
- Each color light incident to the liquid crystal light bulbs 2121 , 2122 , and 2123 is modulated based on video information (video signal), and emitted toward the cross dichroic prism 2116 .
- the cross dichroic prism 2116 is formed by bonding four right-angle prisms.
- a dielectric multilayer film that reflects the red light and a dielectric multilayer film that reflects the blue light are formed in a cross shape.
- Three color light beams are synthesized by the dielectric multilayer films, and thus light beams representing a color image are synthesized.
- Light beams that are synthesized are projected on a screen 2130 by the projection lens 2117 as a projection optical system, and thus the image is enlarged and displayed.
- the liquid crystal device 501 is applied to the liquid crystal light bulb 2121 .
- the liquid crystal light bulb 2121 is disposed with a gap between a pair of polarization elements that are disposed in a crossed nicol state at the incident side and the emitting side of the color light.
- the other liquid crystal light bulbs 2122 and 2123 are similar to the liquid crystal light bulb 2121 .
- the liquid crystal device 501 that has high aperture ratio in the pixel region in which light is transmitted and can prevent the occurrence of light leakage current in the TFT 530 .
- the projector 2100 that has high quality and emits bright light.
- the light shielding layer in the peripheral region E 1 is not limited to only the first light shielding layer 3 c 1 , and two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3 c 2 may be disposed.
- the second light shielding layer 3 c 2 according to the first embodiment is not limited to be in a floating state, for example, and may be electrically connected to the gate electrode 30 g by providing a contact hole.
- the element substrates 510 , 510 A, 510 B, and 510 C according to the embodiments have a configuration in which the thickness of the lower light shielding layer 503 b is thick (approximately 200 nm) and the thicknesses of the upper light shielding layers 503 c , 503 d , 503 e , and 503 f are thin (approximately 100 nm).
- the invention is not limited to the embodiments.
- the element substrate according to the invention may have a configuration in which the thickness of the lower light shielding layer 503 b is thin (approximately 100 nm) and the thicknesses of the upper light shielding layers 503 c , 503 d , 503 e , and 503 f are thick (approximately 200 nm). Even in the configuration, the same effects as those of the embodiments can be obtained.
- the element substrates 510 A and 510 B according to the fifth and sixth embodiments have a configuration in which the lower light shielding layer 503 b is formed straddling the boundary between the pixels P and the upper light shielding layers 503 d and 503 e are separated for each pixel P.
- the invention is not limited to the embodiments.
- the element substrate according to the invention may have a configuration in which lower light shielding layer 503 b is separated for each pixel P and the upper light shielding layers 503 d and 503 e are formed straddling the boundary between the pixels P. Even in the configuration, the same effects as those of the embodiments can be obtained.
- the display apparatus that can apply the light shielding configurations of the element substrates 510 , 510 A, 510 B, and 510 C according to the embodiments is not limited to the liquid crystal device 501 .
- the light shielding configurations of the element substrates 510 , 510 A, 510 B, and 510 C may be applied to a display apparatus such as an organic EL apparatus, a plasma display, or an electronic paper.
- the electronic apparatus that can apply the liquid crystal device 501 according to the embodiment is not limited to the projector 2100 .
- the liquid crystal device 501 can be suitably used, for example, as a projection type HUD (head-up display) or a direct-view type HMD (head-mounted display), or a display unit of an information terminal device such as an electronic book, a personal computer, a digital still camera, a liquid crystal television, a view finder type or monitor direct-view type video recorder, a car navigation system, an electronic organizer, or a POS.
- a projection type HUD head-up display
- a direct-view type HMD head-mounted display
- an information terminal device such as an electronic book, a personal computer, a digital still camera, a liquid crystal television, a view finder type or monitor direct-view type video recorder, a car navigation system, an electronic organizer, or a POS.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
Abstract
Description
- 1. Technical Field
- The present invention relates to a liquid crystal device and an electronic apparatus.
- 2. Related Art
- As the liquid crystal device, for example, an active driving type liquid crystal device in which a transistor for switching and controlling a pixel electrode is provided for each pixel, is known. The liquid crystal device is used, for example, as a liquid crystal light bulb of a liquid crystal projector as an electronic apparatus.
- The liquid crystal device includes an element substrate, a counter substrate disposed opposite to the element substrate, and a liquid crystal layer interposed by the element substrate and the counter substrate. In the element substrate, the transistor and a light shielding layer for shielding light from the liquid crystal projector to the transistor are provided.
- For example, in the liquid crystal device described in JP-A-2003-131261, a method of shielding light toward the transistor is disclosed, by providing the transistor on a substrate of a pixel region and providing a first light shielding film and a second light shielding film between the substrate and the transistor (active layer). In particular, as the amount of light of the liquid crystal projector increases, it is required to improve light shielding properties.
- Even though strong light from a light source is incident to the liquid crystal light bulb, when light is irradiated to the semiconductor layer that constitutes the switching element, a flicker or pixel non-uniformity occurs on the display image by light leakage current, and this results in display quality degradation. Thus, improvement in the light shielding properties of incident light has been achieved from the related art. In recent years, there has been a case where the amount of light from the light source increases and an inorganic polarization plate having high light reflectivity compared to the related art is used. For this reason, a technique for improving the light shielding properties of the reflected light or the like that is incident from the side from which light of the liquid crystal device is emitted (back surface), has been proposed (for example, refer to JP-A-2004-5302475 and JP-A-2011-238835).
- JP-A-2003-131261 discloses a configuration in which a scanning line (gate wiring) that is formed by stacking a metal light shielding film A, an insulating film (metal oxide film or metal nitride film) B, and a metal light shielding film C is disposed in the lower layer of the semiconductor layer of a reverse staggered (bottom gate) type TFT. JP-A-2004-5302475 discloses a configuration in which a first light shielding film and a second light shielding film that interpose an insulating film therebetween are stacked in the lower layer of the semiconductor layer and the potential of the second light shielding film is set to a gate potential or a constant voltage.
- In a large liquid crystal device, there is an increasing need for driving using a high frequency driving signal. On the other hand, in a small liquid crystal device, though the arrangement pitch of the pixels is narrow, a light shielding region tends to be narrowed in order to increase the aperture ratio. For this reason, a technique for improving the light shielding properties and decreasing the wiring resistance has been proposed (for example, refer to JP-A-2011-158700). JP-A-2011-238835 discloses a configuration in which a scanning line that is formed by stacking the three layers of a metal film is disposed in the lower layer of the semiconductor layer.
- However, in JP-A-2003-131261, although the configuration of the light shielding film in the pixel region is disclosed, the configuration of the light shielding film in the peripheral region around the pixel region is not disclosed. Further, when light is incident to the transistor in the peripheral region, there is a problem that light negatively affects the characteristics of the transistor such as the change in the characteristics of the transistor or the like.
- In addition, in JP-A-2004-5302475 and JP-A-2011-238835, since two layers of the light shielding layer are insulated from each other, the wiring resistance of the scanning line is not considered. Further, in JP-A-2011-158700, since the light shielding layer (scanning line) is made of the three layers of a metal film that are stacked being in contact with each other, there is a concern that the light shielding properties are insufficient compared to a case where a layer having a different refractive index such as an insulating film or the like is interposed between the light shielding layers. Therefore, there is a demand for a display apparatus capable of improving the light shielding properties compared to the related art and decreasing the wiring resistance of the scanning line.
- The invention can be realized in the following aspects or application examples.
- According to this application example, there is provided a liquid crystal device, including: a substrate; a liquid crystal layer disposed on the substrate; a first light shielding layer disposed between the substrate and the liquid crystal layer; a second light shielding layer disposed between the first light shielding layer and the liquid crystal layer; a first transistor provided between the second light shielding layer and the liquid crystal layer in a display region; and a second transistor provided between the first light shielding layer and the liquid crystal layer in a peripheral region that is a region around the display region, in which the first transistor is disposed so as to overlap with at least the second light shielding layer in a plan view, and in which the second transistor is disposed so as to overlap with at least the first light shielding layer in a plan view.
- In this application example, the first transistor of the pixel disposed in the display region overlaps with the second light shielding layer in a plan view, and thus, even in a case where light is incident to the display region, it is possible to shield the first transistor from light. On the other hand, the second transistor disposed in the peripheral region overlaps with the first light shielding layer in a plan view, and thus, for example, even in a case where light leaked from the outside is incident to the peripheral region, it is possible to shield the second transistor from light. The second light shielding layer is disposed in the layer closer to the first transistor than the first light shielding layer, and thus it is possible to further prevent light from being incident to the first transistor in a transmission region through which light is transmitted. Further, it is possible to improve the light shielding properties of light that is incident at an angle.
- In the liquid crystal device according to the application example, it is preferable that the first transistor is disposed so as to overlap with the first light shielding layer and the second light shielding layer in a plan view.
- In this application example, the first transistor is disposed so as to overlap with the two layers of the first light shielding layer and the second light shielding layer in a plan view, and thus it is possible to further improve the light shielding properties of the first transistor in the region (display region) through which light is transmitted.
- In the liquid crystal device according to the application example, it is preferable that the first light shielding layer and the second light shielding layer are electrically connected to a gate electrode of the first transistor by one contact hole.
- In this application example, the first light shielding layer and the second light shielding layer are electrically connected to the gate electrode, and thus it is possible to prevent a change in characteristics of the transistor such as a potential change or a floating. Further, the first light shielding layer and the second light shielding layer are electrically connected to the gate electrode by one contact hole, and thus it is possible to prevent a significant decrease in the aperture ratio. In addition, it is also possible to effectively correspond to a case where the pitch between pixels is narrowed.
- In the liquid crystal device according to the application example, it is preferable that at least one of the first light shielding layer and the second light shielding layer is made of a material having a light reflection property.
- In this application example, the first light shielding layer and second light shielding layer have a light reflection property, and thus it is possible to prevent the first transistor and the second transistor (further, liquid crystal device) from heating.
- In the liquid crystal device according to the application example, it is preferable that materials of the first light shielding layer and the second light shielding layer are tungsten silicide.
- In this application example, the first light shielding layer and the second light shielding layer are made of tungsten silicide, and thus it is possible to prevent the first transistor and the second transistor (further, liquid crystal device) from heating.
- According to this application example, there is provided a liquid crystal device including: a first substrate; a second substrate disposed opposite to the first substrate; a liquid crystal layer interposed between the first substrate and the second substrate; a switching element including a semiconductor layer that is disposed on the first substrate for each pixel and includes a channel region, a gate insulating layer covering the semiconductor layer, and a gate electrode disposed opposite to the channel region via the gate insulating layer; a first light shielding layer that is disposed on the first substrate so as to overlap with the semiconductor layer in a plan view and is set to the same potential as the potential of the gate electrode; a first insulating layer disposed so as to cover the first light shielding layer; a second light shielding layer that is disposed on the first insulating layer so as to overlap with the semiconductor layer and the first light shielding layer in a plan view and is set to the same potential as the potential of the gate electrode; and a second insulating layer disposed so as to cover the second light shielding layer, in which the first light shielding layer, the first insulating layer, the second light shielding layer, and the second insulating layer are provided between the first substrate and the semiconductor layer.
- In this application example, the first light shielding layer, the first insulating layer, the second light shielding layer, and the second insulating layer are disposed between the first substrate and the semiconductor layer. Therefore, light incident from the first substrate side toward the semiconductor layer side is reflected at the interface between the first substrate and the first light shielding layer, and then reflected at the interface between the first insulating layer and the second light shielding layer. Thus, it is possible to effectively shield light incident from the first substrate side to the semiconductor layer. In addition, the potentials of the first light shielding layer and the second light shielding layer are set to the same potential as that of the gate electrode, and thus it is possible to configure the scanning line using the two layers of light shielding layer. In a case where the gate wiring is disposed in the same layer as that of the gate electrode, it is possible to configure the scanning line using the three layers including the two layers of the light shielding layer, thereby decreasing the wiring resistance of the scanning line. As a result, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding properties compared to the related art, thereby providing the liquid crystal device having a high liquid crystal quality.
- In the liquid crystal device according to the application example, it is preferable that the first light shielding layer and the second light shielding layer are formed straddling the boundary between the pixels.
- In this application example, the first light shielding layer and the second light shielding layer that constitute the scanning line are formed straddling the boundary between the pixels, and thus, even in a case where the liquid crystal device is a large liquid crystal device including the scanning line with a long length liquid crystal device, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding property.
- In the liquid crystal device according to the application example, the first light shielding layer or the second light shielding layer may be formed to be separated for each pixel.
- In a case where the size of the liquid crystal device is not large and decreasing the wiring resistance of the scanning line is not important, any one of the light shielding layers may be separated for each pixel.
- In the liquid crystal device according to the application example, it is preferable that a first contact hole and a second contact hole that penetrate the first insulating layer and electrically connect the first light shielding layer and the second light shielding layer, are further provided, and that the first contact hole and the second contact hole are disposed at both outsides of the semiconductor layer in a direction intersecting the extending direction of the semiconductor layer in a plan view.
- In this application example, the pair of light shielding portions along the normal direction of the first substrate are formed between the first light shielding layer and the second light shielding layer by the contact holes penetrating the first insulating layer. The pair of light shielding portions are disposed at both outsides of the semiconductor layer in a plan view. Therefore, it is possible to shield light that is incident at an angle with respect to the normal direction of the first substrate from the first substrate side, and light reflected and propagated between the first light shielding layer and the second light shielding layer, from both outsides of the semiconductor layer, by the light shielding portions formed by the contact holes. Accordingly, it is possible to further improve the light shielding property.
- In the liquid crystal device according to the application example, it is preferable that the second light shielding layer is formed so as to fill the first contact hole and the second contact hole and has a substantially flat surface.
- In this application example, the second light shielding layer having a substantially flat surface is formed on the first insulating layer by filling the pair of the contact holes penetrating the first insulating layer. Therefore, in a case of forming the contact holes for electrical connection from the upper layer side (gate electrode side) to the second light shielding layer, the positions at which the contact holes are disposed are not restricted, and thus it is possible to increase the degree of freedom in the wiring pattern design.
- In the liquid crystal device according to the application example, it is preferable that a third contact hole and a fourth contact hole that penetrate the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer are further provided, and that the third contact hole is disposed so as to overlap with the first contact hole in a plan view and the fourth contact hole is disposed so as to overlap with the second contact hole in a plan view.
- In this application example, the pair of the contact holes that penetrate the first insulating layer and electrically connect the first light shielding layer and the second light shielding layer are disposed so as to overlap with the pair of the contact holes that penetrate the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer in a plan view. Therefore, it is possible to reduce the size of the region that is shielded by the contact holes, thereby improving the aperture ratio of the liquid crystal device. Further, the pair of light shielding portions along the normal direction of the first substrate are formed by the contact holes penetrating the gate insulating layer and the second insulating layer, and the pair of light shielding portions are disposed at both outsides of the semiconductor layer in a plan view. Thus, it is possible to further improve the light shielding property.
- In the liquid crystal device according to the application example, it is preferable that a fifth contact hole that penetrates the first insulating layer and electrically connects the first light shielding layer and the second light shielding layer, is further provided, and that, in the sectional view taken along the extending direction of the semiconductor layer, the second light shielding layer is disposed across the bottom portion and the side portions of the fifth contact hole, and the surface of the first insulating layer positioned at the outsides of the fifth contact hole, and that, in the sectional view taken along the extending direction of the semiconductor layer, the semiconductor layer is disposed so as to cover the second light shielding layer via the second insulating layer.
- In this application example, in the sectional view taken along the extending direction of the semiconductor layer, the second light shielding layer is disposed across the bottom portion of the contact hole penetrating the first insulating layer, the side portions of the contact hole, and the surface of the first insulating layer at the outsides of the contact hole. The semiconductor layer is disposed so as to cover the second light shielding layer via the second insulating layer. Therefore, it is possible to make the substantial length of the semiconductor layer longer than the length of the semiconductor layer in a plan view. In other words, it is possible to make the length of the semiconductor layer in a plan view shorter than the length of the semiconductor layer that is required. Thus, it is possible to reduce the size of the light shielding region, thereby improving the aperture ratio of the liquid crystal device.
- In the liquid crystal device according to the application example, it is preferable that at least the channel region of the semiconductor layer is disposed at the bottom portion of the fifth contact hole.
- In this application example, at least the channel region of the semiconductor layer is disposed on the bottom portion of the contact hole. Thus, even in a case where the size of the liquid crystal device is small, it is possible to ensure the channel length of the channel region. In a case where the LDD regions are disposed at both outsides of the channel region, it is possible to dispose the LDD regions in a region from the bottom portion to the outsides of the contact hole via the side portions of the contact hole. Thus, it is possible to ensure the LDD regions having a sufficient length. Therefore, it is possible to form the switching element with excellent operating characteristics. Further, the second light shielding layer that is disposed in the lower layer of the semiconductor layer is disposed so as to cover the bottom portion of the contact hole on which the channel region is disposed, the side portions of the contact hole, and the surface of the first insulating layer at the outsides of the contact hole. Thus, it is possible to effectively shield light incident to the channel region.
- In the liquid crystal device according to the application example, it is preferable that a third contact hole and a fourth contact hole that penetrate the gate insulating layer and the second insulating layer and electrically connect the gate electrode and the second light shielding layer, are further provided, and that the third contact hole and the fourth contact hole are disposed at both outsides of the semiconductor layer in a direction intersecting the extending direction of the semiconductor layer in a plan view.
- In this application example, the pair of light shielding portions along the normal direction of the first substrate are formed by the contact holes penetrating the gate insulating layer and the second insulating layer. The pair of light shielding portions are disposed at both outsides of the semiconductor layer in a plan view. Therefore, it is possible to shield light that is incident at an angle with respect to the normal direction of the first substrate from the first substrate side, and light reflected and propagated between the gate electrode and the second light shielding layer, from both outsides of the semiconductor layer, by the light shielding portions formed by the contact holes. Accordingly, it is possible to further improve the light shielding property.
- In the liquid crystal device according to the application example, a plurality of contact holes that penetrate the first insulating layer and electrically connect the first light shielding layer and the second light shielding layer, may be further provided, and the number of the contact holes may be less than the number of the pixels.
- In a case where the first light shielding layer and the second light shielding layer are formed straddling the boundary between the pixels, the number of the contact holes may be less than the number of the pixels.
- According to this application example, there is provided an electronic apparatus including the liquid crystal device described above.
- In this application example, the liquid crystal device is provided, and thus it is possible to provide the electronic apparatus having an excellent display quality.
- The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
-
FIG. 1 is a schematic plan view illustrating the configuration of a liquid crystal device. -
FIG. 2 is a schematic sectional view taken along line II-II of the liquid crystal device illustrated inFIG. 1 . -
FIG. 3 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device. -
FIG. 4 is a schematic sectional view mainly illustrating the configuration of the pixel of the liquid crystal device. -
FIG. 5 is an enlarged plan view illustrating the enlarged V portion of the liquid crystal device inFIG. 1 . -
FIG. 6 is a schematic sectional view illustrating the configuration of a light shielding layer of a display region according to a first embodiment. -
FIG. 7 is a schematic sectional view illustrating the configuration of the light shielding layer of a peripheral region. -
FIG. 8 is a schematic diagram illustrating the configuration of a projector as an electronic apparatus. -
FIG. 9 is a schematic sectional view illustrating the configuration of a light shielding layer of a display region according to a second embodiment. -
FIG. 10 is a schematic sectional view illustrating the configuration of the light shielding layer of a peripheral region. -
FIG. 11 is a schematic plan view illustrating the configurations of a light shielding layer and a first transistor of a display region according to a third embodiment. -
FIG. 12 is a schematic sectional view illustrating the configurations of the light shielding layer and the first transistor of the display region. -
FIG. 13 is a schematic plan view illustrating the configuration of a liquid crystal device according to a fourth embodiment. -
FIG. 14 is a schematic sectional view taken along line XIV-XIV inFIG. 13 . -
FIG. 15 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device according to the fourth embodiment. -
FIG. 16 is a schematic sectional view illustrating the configuration of an element substrate of the liquid crystal device according to the fourth embodiment. -
FIG. 17 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the fourth embodiment. -
FIG. 18 is a schematic sectional view taken along line XVIII-XVIII inFIG. 17 . -
FIG. 19 is a graph illustrating the light shielding effect of the element substrate according to the fourth embodiment. -
FIG. 20 is a schematic plan view illustrating the configuration of a TFT portion of an element substrate according to a fifth embodiment. -
FIG. 21 is a schematic sectional view taken along line XXI-XXI inFIG. 20 . -
FIG. 22 is a schematic plan view illustrating the configuration of a TFT portion of an element substrate according to a sixth embodiment. -
FIG. 23 is a schematic sectional view taken along line XXIII-XXIII inFIG. 22 . -
FIG. 24 is a schematic plan view illustrating the configuration of a TFT portion of an element substrate according to a seventh embodiment. -
FIG. 25 is a schematic sectional view taken along line XXV-XXV inFIG. 24 . -
FIG. 26 is a schematic diagram illustrating the configuration of a projector as an electronic apparatus according to an eighth embodiment. -
FIG. 27 is a schematic plan view illustrating a configuration example of a TFT portion of an element substrate of the related art. -
FIG. 28 is a schematic sectional view taken along line XXVIII-XXVIII inFIG. 27 . - Hereinafter, embodiments embodying the invention will be described with reference to the accompanying drawings. The drawings used in the description are appropriately enlarged or reduced such that the parts to be described are in a recognizable state.
- In the following embodiment, for example, when “on substrate” is described, it represents a case so as to be disposed in contact with the surface of the substrate, a case so as to be disposed on the substrate via other components, or a case so as to be disposed in partial contact with the surface of the substrate and disposed on the substrate via other components.
- In this embodiment, as a liquid crystal device, an active matrix type liquid crystal device that includes a thin film transistor as a switching element of a pixel will be described as an example. The liquid crystal device may be preferably used, for example, as a light modulation element (liquid crystal light bulb) of a projection type display apparatus (liquid crystal projector).
-
FIG. 1 is a schematic plan view illustrating the configuration of the liquid crystal device.FIG. 2 is a schematic sectional view taken along a line II-II of the liquid crystal device illustrated inFIG. 1 .FIG. 3 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device. Hereinafter, the configuration of the liquid crystal device will be described with reference toFIGS. 1 to 3 . - As illustrated in
FIGS. 1 and 2 , theliquid crystal device 100 according to this embodiment includes anelement substrate 10 and acounter substrate 20 that are disposed to be opposite to each other, and aliquid crystal layer 15 that is interposed by a pair of the substrates. As afirst base material 10 a (substrate) that constitutes theelement substrate 10 and asecond base material 20 a that constitutes thecounter substrate 20, for example, a transparent substrate such as a glass substrate or a quartz substrate is used. - The size of the
element substrate 10 is larger than that of thecounter substrate 20, and both of the substrates are bonded to each other via sealingmembers 14 disposed along the outer circumference of thecounter substrate 20. The gap between the sealingmembers 14 is filled and sealed with liquid crystal having a positive or negative dielectric anisotropy, and thus theliquid crystal layer 15 is configured. - As the sealing
member 14, for example, an adhesive such as thermosetting epoxy resin or ultraviolet-curable epoxy resin is employed. The sealingmember 14 incorporates a spacer for maintaining the gap between the pair of substrates. The spacer is used to make a cell gap. - The display region E in which a plurality of pixels P that contributes to display are arranged is provided in the inside of the sealing
member 14. A peripheral region E1 in which peripheral circuits or the like that do not contribute to display are provided is disposed around the display region E. - A data
line driving circuit 22 is provided between the sealingmember 14 along a first-direction side portion of theelement substrate 10 and the first-direction side portion. Aninspection circuit 25 is provided between the sealingmember 14 along another first-direction side portion that is opposite to the first-direction side portion and the display region E. Scanningline driving circuits 24 are provided between the sealingmembers 14 along second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other and the display region E. A plurality ofwirings 29 connecting the two scanningline driving circuits 24 are provided between the sealingmember 14 along another first-direction side portion that is opposite to the first-direction side portion and theinspection circuit 25. - A frame-shaped light shielding film 18 (parting portion) is provided in the inside of the sealing
member 14 at thecounter substrate 20 side that is disposed in a frame shape. For example, thelight shielding film 18 is made of metal, metal oxide, or the like having a light reflection property, and the inside of thelight shielding film 18 is the display region E that includes the plurality of pixels P. As thelight shielding film 18, for example, tungsten silicide (WSi) may be used. Although not illustrated inFIG. 1 , a light shielding film that partitions the plurality of pixels P in a plane is also provided in the display region E. - The wiring connected to the data line driving
circuit 22 and the scanningline driving circuit 24 is connected to a plurality ofexternal connection terminals 65 that are arranged along the first-direction side portion. Hereinafter, the direction along the first-direction side portion is described as an X-direction, and the direction along second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other is described as a Y-direction. - As illustrated in
FIG. 2 , atransparent pixel electrode 27 and a thin film transistor as a switching element (hereafter, referred to as “transistor 30”) that are provided for each pixel P, signal wiring (not illustrated), and afirst alignment film 28 covering thetransparent pixel electrode 27, thetransistor 30, and the signal wiring is formed on the surface of thefirst base material 10 a on theliquid crystal layer 15 side. - The light shielding configuration (not illustrated) that prevents a switching operation from being unstable due to light that is incident to the semiconductor layer of the
transistor 30 is employed. Theelement substrate 10 of the invention includes at least thepixel electrode 27, thetransistor 30, the signal wiring, and thefirst alignment film 28. - The
light shielding film 18, an insulatinglayer 33 that is formed so as to cover thelight shielding film 18, acounter electrode 31 that is provided to cover the insulatinglayer 33, and asecond alignment film 32 that covers thecounter electrode 31 are provided on the surface of thecounter substrate 20 on theliquid crystal layer 15 side. Thecounter substrate 20 of the invention includes at least thelight shielding film 18, thecounter electrode 31, and thesecond alignment film 32. - As illustrated in
FIG. 1 , thelight shielding film 18 surrounds the display region E, and is provided at the position overlapping with the scanningline driving circuit 24 and theinspection circuit 25 in a plane. Accordingly, thelight shielding film 18 prevents the malfunction of the peripheral circuits including these driving circuits due to light, by shielding light that is incident to the peripheral circuits from thecounter substrate 20 side. Further, thelight shielding film 18 ensures high contrast in the display of the display region E by shielding unnecessary stray light so as not to be incident to the display region E. - The insulating
layer 33 is made of, for example, an inorganic material such as silicon oxide, and has a light transmitting property. The insulatinglayer 33 is provided so as to cover thelight shielding film 18. As the method of forming the insulatinglayer 33, for example, a method of forming a film using a plasma chemical vapor deposition (CVD) method or the like may be used. - The
counter electrode 31 is made of, for example, a transparent conductive film such indium tin oxide (ITO), and covers the insulatinglayer 33. As illustrated inFIG. 1 , thecounter electrode 31 is electrically connected to the wiring on theelement substrate 10 side by upper andlower conduction portions 26 provided at the four corners of thecounter substrate 20. - The
first alignment film 28 covering thepixel electrode 27 and thesecond alignment film 32 covering thecounter electrode 31 are selected based on the optical design of theliquid crystal device 100. As thefirst alignment film 28 and thesecond alignment film 32, an inorganic alignment film obtained by forming a film with an inorganic material such as SiOx (silicon oxide) using a vapor growth method and aligning the film substantially perpendicular to the liquid crystal molecules having negative dielectric anisotropy may be used. - The
liquid crystal device 100 is, for example, a transmission type, and adopts a normally white mode type optical design in which the transmittance of the pixel P when a voltage is not applied is greater than the transmittance when a voltage is applied, or a normally black mode type optical design in which the transmittance of the pixel P when a voltage is not applied is smaller than the transmittance when a voltage is applied. A polarization element is respectively disposed and used at the incident side and the emitting side of light according to the optical design. - As illustrated in
FIG. 3 , theliquid crystal device 100 includes at least a plurality ofscanning lines 3 a and a plurality ofdata lines 6 a that are insulated from each other and perpendicular to each other in the display region E, and a plurality ofcapacitance lines 3 b. For example, the direction to which thescanning lines 3 a are extended is the X-direction, and the direction to which thedata lines 6 a are extended is the Y-direction. - The pixel circuit of the pixel P is configured with the
scanning line 3 a, thedata line 6 a, thecapacitance line 3 b, thepixel electrodes 27, thetransistors 30, andcapacitor elements 16 that are provided in the region divided by the signal lines. - The
scanning line 3 a is electrically connected to the gate of thetransistor 30, and thedata line 6 a is electrically connected to the source-drain region on the data line side of thetransistor 30. Thepixel electrode 27 is electrically connected to the source-drain region on the pixel electrode side of thetransistor 30. - The
data line 6 a is connected to the data line driving circuit 22 (refer toFIG. 1 ), and supplies the image signals D1, D2, . . . , Dn supplied from the data line drivingcircuit 22 to the pixel P. Thescanning line 3 a is connected to the scanning line driving circuit 24 (refer toFIG. 1 ), and supplies the scanning signals SC1, SC2, . . . , SCm supplied from the scanningline driving circuit 24 to each pixel P. - The image signals D1 to Dn supplied from the data line driving
circuit 22 to thedata line 6 a may be line-sequentially supplied in this order, or may be supplied for each group with a plurality ofdata lines 6 a adjacent to each other. The scanningline driving circuit 24 supplies the scanning signals SC1 to SCm to thescanning lines 3 a in a line sequential manner using a pulse at a predetermined timing. - In the
liquid crystal device 100, thetransistor 30 as a switching element is turned on only for a certain period by the input of the scanning signals SC1 to SCm, and thus image signals D1 to Dn supplied from thedata lines 6 a are written to thepixel electrode 27 at a predetermined timing. The image signals D1 to Dn with a predetermined level that are written to theliquid crystal layer 15 via thepixel electrode 27 are held for a predetermined period between thepixel electrode 27 and thecounter electrode 31 that are disposed to interpose theliquid crystal layer 15. - In order to prevent the held image signals D1 to Dn from leaking, the
capacitor element 16 is connected in parallel to a liquid crystal capacitor formed between thepixel electrode 27 and thecounter electrode 31. Thecapacitor element 16 is provided between the source-drain region of thetransistor 30 on the pixel electrode side and thecapacitance line 3 b. Thecapacitor element 16 is an element that includes a dielectric layer between two capacitor electrodes. - Next, the configuration of the pixel will be described with reference to
FIG. 4 .FIG. 4 is a schematic sectional view mainly illustrating the configuration of the pixel of the liquid crystal device.FIG. 4 illustrates the sectional position relationship of each component in a clearly displayable scale. - As illustrated in
FIG. 4 , the pixel P of theliquid crystal device 100 includes theelement substrate 10, and thecounter substrate 20 disposed opposite to the element substrate. Thefirst base material 10 a constituting theelement substrate 10 is, for example, a quartz substrate. - As illustrated in
FIG. 4 , a first light shielding layer 3c 1 that is made of, for example, tungsten silicide (WSi) is disposed on thefirst base material 10 a. The first light shielding layer 3c 1 is patterned in a plane lattice shape, and defines the opening region of each pixel P. - A first insulating
layer 11 a that is made of silicon oxide is formed on the first light shielding layer 3 c 1 and thefirst base material 10 a. A second light shielding layer 3c 2 that is made of, for example, tungsten silicide (WSi) having a light reflection property is formed on the first insulatinglayer 11 a, so as to overlap with a partial region of asemiconductor layer 30 a in a plan view. A second insulatinglayer 11 b that is made of silicon oxide or the like is formed on the second light shielding layer 3 c 2 and the first insulatinglayer 11 a. - The
transistor 30, thescanning line 3 a, and the like are formed on the second insulatinglayer 11 b. Thetransistor 30 has, for example, a Lightly Doped Drain (LDD) structure, and includes thesemiconductor layer 30 a that is made of polysilicon (polycrystalline silicon having high purity), agate insulating layer 11 g formed on thesemiconductor layer 30 a, and agate electrode 30 g that is made of polysilicon film or the like and formed on thegate insulating layer 11 g. Thescanning line 3 a also functions as thegate electrode 30 g. - The
semiconductor layer 30 a is formed as the N-type transistor 30 by, for example, being implanted with N-type impurity ions such as phosphorus (P) ions. Specifically, thesemiconductor layer 30 a includes achannel region 30 c, a data lineside LDD region 30s 1, a data line side source-drain region 30 s, a pixel electrodeside LDD region 30d 1, and a pixel electrode side source-drain region 30 d. - The
channel region 30 c is doped with P-type impurity ions such as boron (B) ions. The other regions (30s d transistor 30 is formed as an N-type transistor. - A third
interlayer insulating layer 11 c that is made of silicon oxide or the like is formed on thegate electrode 30 g and thegate insulating layer 11 g. Thecapacitor element 16 is provided on the thirdinterlayer insulating layer 11 c. Specifically, afirst capacitor electrode 16 a as a pixel potential side capacitor electrode that is electrically connected to the pixel electrode side source-drain region 30 d of thetransistor 30 and thepixel electrode 27 and a part of thecapacitance line 3 b (second capacitor electrode 16 b) as a fixed potential side capacitor electrode are disposed opposite to each other via adielectric film 16 c, and thus thecapacitor element 16 is formed. - The
dielectric film 16 c is, for example, a silicon nitride film. Thesecond capacitor electrode 16 b (capacitance line 3 b) is made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, or a material obtained by stacking the above-mentioned material that includes at least one of metals having a high melting point such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), or molybdenum (Mo). Alternatively, thesecond capacitor electrode 16 b may also be formed by an aluminum (Al) film. - The
first capacitor electrode 16 a functions as the pixel potential side capacitor electrode of thecapacitor element 16 that is made of, for example, a conductive polysilicon film. Here, thefirst capacitor electrode 16 a may be made of a single layer film or a multilayer film that includes a metal or an alloy, similarly to thecapacitance line 3 b. Thefirst capacitor electrode 16 a has a function of relaying and connecting thepixel electrode 27 and the pixel electrode side source-drain region 30 d (drain region) of thetransistor 30 via contact holes CNT1, CNT3, and CNT4, in addition to the function as the pixel potential side capacitor electrode. - The
data line 6 a is formed on thecapacitor element 16 via a fourthinterlayer insulating layer 11 d. Thedata line 6 a is electrically connected to the data line side source-drain region 30 s (source region) of thesemiconductor layer 30 a via agate insulating layer 11 g, a thirdinterlayer insulating layer 11 c, thedielectric film 16 c, and a contact hole CNT2 that is open in the fourthinterlayer insulating layer 11 d. - The
pixel electrode 27 is formed above thedata line 6 a via a fifthinterlayer insulating layer 11 e. The fifthinterlayer insulating layer 11 e is made of, for example, silicon oxide or silicon nitride, and subjected to a planarization process for planarizing the protrusion portion of the surface that is caused by covering the region in which thetransistor 30 is provided. As a method for the planarization process, a chemical mechanical polishing (CMP) process, a spin coating process, or the like may be used. The contact hole CNT4 is formed in the fifthinterlayer insulating layer 11 e. - The
pixel electrode 27 is connected to thefirst capacitor electrode 16 a via the contact holes CNT4 and CNT3, and thus thepixel electrode 27 is electrically connected to the pixel electrode side source-drain region 30 d (drain region) of thesemiconductor layer 30 a. Thepixel electrode 27 is formed, for example, by a transparent conductive film such as an ITO film. - A
first alignment film 28 that is formed by obliquely vapor-depositing an inorganic material such as silicon oxide (SiO2) is provided on the fifthinterlayer insulating layer 11 e between thepixel electrode 27 and theadjacent pixel electrode 27. Aliquid crystal layer 15 that is filled and sealed with liquid crystal or the like in the space surrounded by the sealingmember 14 is provided on thefirst alignment film 28. - On the other hand, the
counter electrode 31 is provided, for example, on the entire surface of the insulating layer 33 (liquid crystal layer 15 side) of thecounter substrate 20. Asecond alignment film 32 that is formed by obliquely vapor-depositing an inorganic material such as silicon oxide (SiO2) is provided on thecounter electrode 31. Thecounter electrode 31 is formed, for example, by a transparent conductive film such as an ITO film, similarly to thepixel electrode 27. - The
liquid crystal layer 15 is in a predetermined alignment state by thealignment films pixel electrode 27 and thecounter electrode 31. The sealingmember 14 is an adhesive for bonding theelement substrate 10 and thecounter substrate 20 that is made of a photocurable resin or a thermosetting resin, and the spacers such as glass fibers or glass beads for making the distance between theelement substrate 10 and thecounter substrate 20 with a predetermined value are mixed into the sealingmember 14. - Light of a
projector 1000 to be described later is incident, for example, from the back side of the liquid crystal device 100 (element substrate 10 side). - Next, the configuration of the light shielding layer of the first embodiment will be described with reference to
FIGS. 5 to 7 .FIG. 5 is an enlarged plan view illustrating the enlarged V portion of the liquid crystal device inFIG. 1 .FIG. 6 is a schematic sectional view illustrating the configuration of the light shielding layer (second light shielding layer) of the display region.FIG. 7 is a schematic sectional view illustrating the configuration of the light shielding layer (first light shielding layer) of the peripheral region. - As illustrated in
FIG. 5 , theliquid crystal device 100 includes the display region E in which the pixels P each of which includes afirst transistor 301 are disposed, and the peripheral region E1 in which the peripheral circuits each of which includes asecond transistor 302 are disposed. - As illustrated in
FIG. 6 , in the display region E, for example, the first insulatinglayer 11 a, the second light shielding layer 3c 2, the second insulatinglayer 11 b, and thesemiconductor layer 30 a 1 are stacked in this order from thefirst base material 10 a side. The second light shielding layer 3c 2 is disposed so as to overlap with thesemiconductor layer 30 a 1 in a plan view. Specifically, the second light shielding layer 3c 2 is disposed so as to overlap with at least the LDD region of thesemiconductor layer 30 a 1 in a plan view. - As illustrated in
FIG. 7 , in the peripheral region E1, for example, the first light shielding layer 3c 1, the first insulatinglayer 11 a, the second insulatinglayer 11 b, and thesemiconductor layer 30 a 2 are stacked in this order from thefirst base material 10 a side. The first light shielding layer 3c 1 is disposed so as to overlap with thesemiconductor layer 30 a 2 in a plan view. Specifically, the first light shielding layer 3c 1 is disposed so as to overlap with at least the LDD region of thesemiconductor layer 30 a 2 in a plan view. - As the material of the first light shielding layer 3 c 1 and the second light shielding layer 3
c 2, a material having light shielding properties or light reflection properties may be used. For example, tungsten silicide (WSi) having a light reflection property may be used, similarly to thelight shielding film 18. As described above, tungsten silicide is used, and thus it is possible to prevent the heat being applied to the transistor. - The second light shielding layer 3
c 2 provided in the display region E is disposed so as to overlap with thefirst transistor 301 in a plan view, and can shield light at the position closer than the layer of the first light shielding layer 3c 1. Thus, in a projector or the like, it is possible to improve the light shielding properties in the light transmission region in which light is transmitted. - The first light shielding layer 3
c 1 provided in the peripheral region E1 is disposed so as to overlap with thesecond transistor 302 in a plan view. Thus, the first light shielding layer 3c 1 can shield light leaked from the outside. Therefore, it is possible to prevent a change in characteristics of the transistor, for example. - The thickness of the first light shielding layer 3
c 1 is equal to or greater than 200 nm, for example. The thickness of the second light shielding layer 3c 2 is equal to or greater than 100 nm, for example. The thickness of the first insulatinglayer 11 a is, for example, 2000 Å. The thickness of the second insulatinglayer 11 b is, for example, 2000 Å. -
FIG. 8 is a schematic diagram illustrating the configuration of the projector as an electronic apparatus. Hereinafter, the configuration of the projector will be described with reference toFIG. 8 . - As illustrated in
FIG. 8 , theprojector 1000 according to this embodiment includes apolarization illumination device 1100 as an illumination system disposed along the system optical axis L, twodichroic mirrors reflection mirrors relay lenses crystal light bulbs dichroic prism 1206 as a light synthesizing element, and aprojection lens 1207. - The
polarization illumination device 1100 is schematically configured with alamp unit 1101 as a light source that is configured by a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, anintegrator lens 1102, and apolarization conversion element 1103. - The
dichroic mirror 1104 reflects red light (R) among polarized light beams emitted from thepolarization illumination device 1100, and transmits green light (G) and blue light (B). Anotherdichroic mirror 1105 reflects the green light (G) transmitted through thedichroic mirror 1104, and transmits the blue light (B). - The red light (R) reflected by the
dichroic mirror 1104 is reflected by thereflection mirror 1106, and then is incident to the liquidcrystal light bulb 1210 via therelay lens 1205. The green light (G) reflected by thedichroic mirror 1105 is incident to the liquidcrystal light bulb 1220 via therelay lens 1204. The blue light (B) transmitted through thedichroic mirror 1105 is incident to the liquidcrystal light bulb 1230 via a light guide system that is configured by threerelay lenses reflection mirrors - The liquid
crystal light bulbs dichroic prism 1206. Each color light incident to the liquidcrystal light bulbs dichroic prism 1206. - The prism is formed by bonding four right-angle prisms. In the inner surface of the prism, a dielectric multilayer film that reflects the red light and a dielectric multilayer film that reflects the blue light are formed in a cross shape. Three color light beams are synthesized by the dielectric multilayer films, and thus light beams representing a color image are synthesized. Light beams that are synthesized are projected on a
screen 1300 by theprojection lens 1207 that constitutes a projectionoptical system 1400, and thus the image is enlarged and displayed. - The
liquid crystal device 100 to be described later is applied to the liquidcrystal light bulb 1210. Theliquid crystal device 100 is disposed with a gap between a pair of polarization elements that are disposed in a crossed nicol state at the incident side and the emitting side of the color light. The other liquidcrystal light bulbs crystal light bulb 1210. - The electronic apparatus with the above-described configuration uses the
liquid crystal device 100 according to the embodiment described above, and thus it is possible to provide theprojector 1000 having high reliability and excellent display characteristics. - As the electronic apparatus in which the
liquid crystal device 100 is mounted, for example, various electronic apparatuses such as a head-mounted display (HMD), a head-up display (HUD), a smart phone, an electronic view finder (EVF), a mobile phone, a mobile computer, a digital camera, a digital video camera, an in-vehicle apparatus, or an illumination apparatus can be used, in addition to theprojector 1000. - As described above, according to the
liquid crystal device 100 and the electronic apparatus of the first embodiment, the following effects can be obtained. - (1) According to the
liquid crystal device 100 of the first embodiment, thefirst transistor 301 of the pixel P disposed in the display region E is overlapped with the second light shielding layer 3c 2 in a plan view, and thus it is possible to shield thefirst transistor 301 from light even in a case where light is incident to the display region E from theprojector 1000. On the other hand, thesecond transistor 302 of the peripheral circuit disposed in the peripheral region E1 is overlapped with the first light shielding layer 3c 1 in a plan view, and thus it is possible to shield light even in a case where light that is leaked from the outside is incident to the peripheral region. Therefore, it is possible to shield light without causing failure characteristics of the peripheral circuit. In addition, the second light shielding layer 3c 2 is disposed in the layer closer to thefirst transistor 301 than the first light shielding layer 3c 1, and thus it is possible to further prevent light from being incident to thefirst transistor 301 in the light transmission region. Further, it is possible to shield light at the position close to thefirst transistor 301, thereby improving the light shielding properties of light that is incident at an angle. - (2) According to the
liquid crystal device 100 of the first embodiment, tungsten silicide having a light reflection property is used in the first light shielding layer 3 c 1 and the second light shielding layer 3c 2, and thus it is possible to prevent thefirst transistor 301 and the second transistor 302 (further, liquid crystal device 100) from heating. - (3) According to the electronic apparatus of the first embodiment, the
liquid crystal device 100 is provided, and thus it is possible to provide the electronic apparatus having an excellent display quality. - Next, the configuration of the light shielding layer according to the second embodiment will be described with reference to
FIGS. 9 and 10 .FIG. 9 is a schematic sectional view illustrating the configuration of the light shielding layer of the display region.FIG. 10 is a schematic sectional view illustrating the configuration of the light shielding layer of the peripheral region. - The
liquid crystal device 200 according to the second embodiment is mainly similar to theliquid crystal device 100 according to the first embodiment, except that the two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are disposed in the display region E. For this reason, in the second embodiment, the part different from the first embodiment will be described in detail, and the detailed description of the other parts overlapped with the first embodiment will be omitted. - As illustrated in
FIG. 9 , in the display region E of theliquid crystal device 200 according to the second embodiment, the first light shielding layer 3c 1, the first insulatinglayer 11 a, the second light shielding layer 3c 2, the second insulatinglayer 11 b, and thesemiconductor layer 30 a 1 are stacked in this order from thefirst base material 10 a side. The first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are disposed so as to overlap with thesemiconductor layer 30 a 1 in a plan view. Specifically, the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are disposed so as to overlap with at least the LDD region of thesemiconductor layer 30 a 1 in a plan view. - As illustrated in
FIG. 10 , in the peripheral region E1, as in the first embodiment, the first light shielding layer 3c 1, the first insulatinglayer 11 a, the second insulatinglayer 11 b, and thesemiconductor layer 30 a 2 are stacked in this order from thefirst base material 10 a side. The first light shielding layer 3c 1 is disposed so as to overlap with thesemiconductor layer 30 a 2 in a plan view. Specifically, the first light shielding layer 3c 1 is disposed so as to overlap with at least the LDD region of thesemiconductor layer 30 a 2 in a plan view. - The
first transistor 301 of the display region E is disposed so as to overlap with the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 in a plan view, and thus it is possible to improve the light shielding property, compared to a case where the first transistor is disposed so as to overlap with only the second light shielding layer 3c 2. In particular, it is possible to significantly improve the light shielding properties in the light transmission region. - The first light shielding layer 3
c 1 provided in the peripheral region E1 is disposed so as to overlap with thesecond transistor 302 in a plan view, as in the first embodiment. Thus, the first light shielding layer 3c 1 can shield light leaked from the outside. Therefore, it is possible to prevent a change in characteristics of the transistor, for example. - As described above in detail, according to the
liquid crystal device 200 of the second embodiment, the following effects can be obtained, in addition to the effects according to the first embodiment. - (4) According to the
liquid crystal device 200 of the second embodiment, in the display region E, thefirst transistor 301 is disposed so as to overlap with the two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 in a plan view, and thus it is possible to prevent light of theprojector 1000 from being incident to thefirst transistor 301, thereby improving the light shielding property. - Next, the configuration of the light shielding layer according to the third embodiment will be described with reference to
FIGS. 11 and 12 .FIG. 11 is a schematic plan view illustrating the configurations of the light shielding layer and the first transistor of the display region.FIG. 12 is a schematic sectional view illustrating the configurations of the light shielding layer and the first transistor of the display region. - The
liquid crystal device 300 according to the third embodiment is mainly similar to theliquid crystal device 200 according to the second embodiment, except that the two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are disposed in the display region E, and further that the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are electrically connected to thegate electrode 30 g. For this reason, in the third embodiment, the part different from the second embodiment will be described in detail, and the description of the other parts overlapped with the second embodiment will be omitted. - As illustrated in
FIGS. 11 and 12 , in the display region E of theliquid crystal device 300 according to the third embodiment, as in the second embodiment, the first light shielding layer 3c 1, the first insulatinglayer 11 a, the second light shielding layer 3c 2, the second insulatinglayer 11 b, and thesemiconductor layer 30 a 1 are stacked in this order from thefirst base material 10 a side. The gate electrode 30 g is disposed on thesemiconductor layer 30 a 1 via thegate insulating layer 11 g. - The first light shielding layer 3 c 1 and the second light shielding layer 3
c 2 are electrically connected to thegate electrode 30 g via a contact hole CNT11. The first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are electrically connected to thegate electrode 30 g via a contact hole CNT12. - The configuration of the peripheral region E1 is the same as that of the peripheral region E1 in the first embodiment and the second embodiment.
- In the
first transistor 301 of the display region E, the first light shielding layer 3 c 1 and the second light shielding layer 3c 2, and thegate electrode 30 g are electrically connected to each other, and thus the potentials of the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are the same as that of the gate electrode, thereby improving the characteristics of the transistor. - In addition, the first light shielding layer 3 c 1 and the second light shielding layer 3
c 2 can electrically connected to thegate electrode 30 g by using the one contact hole CNT11 (or CNT12), and thus it is possible to prevent a planar region from spreading, thereby maintaining an aperture ratio. Further, it is effective in narrowing the pitch between the pixels. - As described above, according to the
liquid crystal device 300 of the third embodiment, the following effects can be obtained, in addition to the effects of the embodiments described above. - (5) According to the
liquid crystal device 300 of the third embodiment, the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are electrically connected to thegate electrode 30 g, and thus it is possible to prevent a change in characteristics of the transistor such as a potential change or a floating. Further, the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 are electrically connected to thegate electrode 30 g by using the one contact hole CNT11 (or CNT12), and thus it is possible to prevent a significant decrease in the aperture ratio. In addition, even in a case where the pitch between the pixels is narrowed, it is possible to effectively correspond to the case. Furthermore, it is unlikely to be restricted in layout. - Here, an active matrix type liquid crystal device that includes a thin film transistors (TFT) as a switching element of the pixel will be described as an example. The liquid crystal device can be preferably used, for example, as a light modulation element (liquid crystal light bulb) of a projection type display apparatus (projector) to be described later.
- First, the liquid crystal device as a display apparatus according to the fourth embodiment will be described with reference to
FIGS. 13 and 14 .FIG. 13 is a schematic plan view illustrating the configuration of the liquid crystal device according to the fourth embodiment.FIG. 14 is a schematic sectional view taken along line XIV-XIV inFIG. 13 .FIG. 15 is an equivalent circuit diagram illustrating the electrical configuration of the liquid crystal device according to the fourth embodiment. - As illustrated in
FIGS. 13 and 14 , theliquid crystal device 501 according to the fourth embodiment includes anelement substrate 510, acounter substrate 520 disposed opposite to theelement substrate 510, and aliquid crystal layer 540 disposed between theelement substrate 510 and thecounter substrate 520. As thesubstrate 510 a as a first substrate that constitutes theelement substrate 510 and thesubstrate 520 a as a second substrate that constitutes thecounter substrate 520, for example, the substrate that is made of a material having a light transmitting property such as glass or quartz can be used. - The size of the
element substrate 510 is further larger than that of thecounter substrate 520, and the two substrates are bonded to each other via sealingmembers 542 disposed in a frame shape. The space surrounded by theelement substrate 510, thecounter substrate 520, and the sealingmembers 542 is filled and sealed with liquid crystal having a positive or negative dielectric anisotropy, and thus theliquid crystal layer 540 is configured. - The sealing
member 542 is made of, for example, an adhesive such as thermosetting epoxy resin or ultraviolet-curable epoxy resin. The spacers (not illustrated) for maintaining the gap between theelement substrate 510 and thecounter substrate 520 with a constant value are mixed into the sealingmember 542. A frame-shapedlight shielding layer 521 provided on thecounter substrate 520 is disposed in the inside of the sealingmember 542 disposed in a frame shape. Thelight shielding layer 521 is made of, for example, metal or metal oxide having a light shielding property. - The inside of the
light shielding layer 521 becomes the display region E in which a plurality of pixels P are arrayed. In theliquid crystal device 501, the display region E is a region that substantially contributes to display. Although not illustrated inFIGS. 13 and 14 , even in the display region E, a lattice-shaped light shielding portion for partitioning the plurality of pixels P in a plane is provided, for example, on thecounter substrate 520. - The data line driving
circuit 551 and the plurality ofexternal connection terminals 554 are provided at the outside of the sealingmember 542 on a first-direction side portion of theelement substrate 510 along the first-direction side portion. Theinspection circuit 553 is provided in the inside of the sealingmember 542 along another first-direction side portion that is opposite to the first-direction side portion. The scanningline driving circuits 552 are provided in the inside of the sealingmembers 542 along second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other. - A plurality of
wirings 555 connecting the two scanningline driving circuits 552 are provided in the inside of the sealingmember 542 on the first-direction side portion at which theinspection circuit 553 is provided. The wirings connected to the data line drivingcircuit 551 and the scanningline driving circuit 552 are connected to the plurality ofexternal connection terminals 554. The upper andlower conduction portions 556 for electrical conduction between theelement substrate 510 and thecounter substrate 520 are provided at the corner portions of thecounter substrate 520. The disposition of theinspection circuit 553 is not limited thereto, and theinspection circuit 553 may be provided at the position along the inside of the sealingmember 542 between the data line drivingcircuit 551 and the display region E. - In the following description, the direction along the first-direction side portion at which the data
line driving circuit 551 is provided is described as an X-direction, and the direction along the second-direction side portions that are perpendicular to the first-direction side portions and opposite to each other is described as a Y-direction. The direction of the line XIV-XIV inFIG. 13 is a direction along the Y-direction. The direction that is perpendicular to the X-direction and the Y-direction and directed toward the upward inFIG. 14 is described as a Z-direction. In the specification, “in a plan view” denotes that it is seen from the normal direction (Z-direction) of the surface of thecounter substrate 520 of theliquid crystal device 501. - As illustrated in
FIG. 14 , TFTs 530 (refer toFIG. 15 ) as a switching element provided for each pixel P,pixel electrodes 515 having a light transmitting property, signal lines (not illustrated), and an alignment film 518 covering thepixel electrodes 515 are provided on the surface of thesubstrate 510 a on theliquid crystal layer 540 side. Thepixel electrode 515 is made of a conductive film having a light transmitting property such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). - In the
element substrate 510 according to this embodiment, a light shielding configuration for preventing the switching operation from becoming unstable due to light incident to thesemiconductor layer 530 a (refer toFIG. 17 ) of theTFT 530 is adopted. The light shielding configuration will be described later. - The
light shielding layer 521, aninterlayer 522, acommon electrode 523, and analignment film 524 covering thecommon electrode 523 are provided on theliquid crystal layer 540 side of thecounter substrate 520. - As illustrated in
FIGS. 13 and 14 , the frame-shapedlight shielding layer 521 is provided at the position overlapping with the scanningline driving circuits 552, and the plurality ofwirings 555 or theinspection circuit 553 in a plan view. Thelight shielding layer 521 shields light incident from thecounter substrate 520 side, thereby preventing the malfunction of the peripheral circuit including the driving circuits due to light. Thelight shielding layer 521 ensures high contrast in the display of the display region E by shielding unnecessary stray light so as not to be incident to the display region E. - The
interlayer 522 illustrated inFIG. 14 is formed to cover thelight shielding layer 521. Theinterlayer 522 is formed of, for example, an insulating film such as silicon oxide (SiO2), and has a light transmitting property. Theinterlayer 522 is provided to planarize the surface of theliquid crystal layer 540 side on which thecommon electrode 523 is formed, by reducing unevenness caused by thelight shielding layer 521 or the like. As a method of forming theinterlayer 522, for example, a film forming method using a plasma chemical vapor deposition (CVD) method or the like can be used. - The
common electrode 523 is made of, for example, a conductive film having a light transmitting property, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). Thecommon electrode 523 covers theinterlayer 522, and is electrically connected to the wiring onelement substrate 510 side by the upper andlower conduction portions 556 provided at the four corners of thecounter substrate 520, as illustrated inFIG. 13 . - The alignment film 518 and the
alignment film 524 are selected based on the optical design of theliquid crystal device 501. As the alignment film 518 and thealignment film 524, for example, an alignment film that is formed using an organic material such as polyimide and subjected to a substantially horizontal alignment treatment to the liquid crystal molecules by rubbing the surface of the film, or an alignment film that is formed using an inorganic material such as SiOx (silicon oxide) by a vapor phase growth method and subjected to a substantially vertical alignment treatment to the liquid crystal molecules, can be used. - The liquid crystal included in the
liquid crystal layer 540 modulates light to allow a gradation display by the change in the alignment or the order of molecular aggregates according to the applied voltage level. For example, in a case of a normally white mode, the transmittance of incident light decreases according to the voltage applied to each pixel P. In a case of a normally black mode, the transmittance of incident light increases according to the voltage applied to each pixel P. Thus, light having contrast according to the image signal is emitted from theliquid crystal device 501 as a whole. - As illustrated in
FIG. 15 , in the display region E, gate wirings (scanning lines) 503 a anddata lines 506 a are formed so as to be insulated and intersected with each other. The direction to which the gate wirings 503 a are extended is the X-direction, and the direction to which thedata lines 506 a are extended is the Y-direction. The pixels P are provided to correspond to the intersections of the gate wirings 503 a and thedata lines 506 a. In each pixel P, apixel electrode 515, and a thin film transistor (TFT) 530 as a switching element are provided. - The source electrode 531 (refer to
FIG. 16 ) of theTFT 530 is electrically connected to thedata line 506 a. The data line 506 a is connected to the data line driving circuit 551 (refer toFIG. 13 ), and supplies the image signal (data signal) S1, S2, . . . , Sn supplied from the data line drivingcircuit 551 to the pixel P. The image signal S1, S2, . . . , Sn supplied from the data line drivingcircuit 551 to thedata line 506 a may be line-sequentially supplied in this order, or may be supplied for each group with a plurality ofdata lines 506 a adjacent to each other. - The gate electrode 530 g (refer to
FIG. 16 ) of theTFT 530 is electrically connected to the gate wiring (scanning line) 503 a. In this embodiment, thegate electrode 530 g is a part of the gate wiring (scanning line) 503 a. The gate wiring (scanning line) 503 a is connected to the scanning line driving circuit 552 (refer toFIG. 13 ), and supplies the scanning signals G1, G2, . . . , Gm supplied from the scanningline driving circuit 552 to each pixel P. The scanningline driving circuit 552 line-sequentially supplies the scanning signals G1, G2, . . . , Gm to the gate wiring (scanning line) 503 a using a pulse at a predetermined timing. The drain electrode 532 (refer toFIG. 16 ) of theTFT 530 is electrically connected to thepixel electrode 515. - The
TFT 530 is in a turned-on state only for a certain period, and thus the image signals S1, S2, . . . , Sn are written to thepixel electrode 515 via thedata line 506 a at a predetermined timing. The image signals with a predetermined level that are written to theliquid crystal layer 540 via thepixel electrode 515 are held for a certain period in the liquid crystal capacitor formed between thepixel electrode 515 and the common electrode 523 (refer toFIG. 14 ) provided on thecounter substrate 520. - In order to prevent the image signals S1, S2, . . . , Sn that are held from leaking, a
storage capacitor 516 is formed between acapacitor line 516 a and thepixel electrode 515 that are formed so as to parallel to thedata line 506 a along thedata line 506 a, and disposed parallel to the liquid crystal capacitor. As described above, when a voltage signal is applied to the liquid crystal of each pixel P, the alignment state of the liquid crystal is changed according to the applied voltage level. Accordingly, light incident to the liquid crystal layer 540 (refer toFIG. 14 ) is modulated, and thus gradation display can be realized. - The data line 506 a is connected to the
inspection circuit 553 illustrated inFIG. 13 . Theinspection circuit 553 is configured to check the operation defect or the like of theliquid crystal device 501, by detecting the image signals in the process of manufacturing theliquid crystal device 501. Here, theinspection circuit 553 is not illustrated in the equivalent circuit diagram ofFIG. 15 . Theinspection circuit 553 may include a sampling circuit for sampling the image signal and supplying the image signal subjected to the sampling to thedata line 506 a, and a precharge circuit for supplying a precharge signal with a predetermined voltage level to thedata line 506 a prior to the image signal. -
FIG. 16 is a schematic sectional view illustrating the configuration of an element substrate of the liquid crystal device according to the fourth embodiment. As illustrated inFIG. 16 , theelement substrate 510 includes asubstrate 510 a as a first substrate, a lowerlight shielding layer 503 b as a first light shielding layer, aninterlayer insulating layer 511 a as a first insulating layer, an upperlight shielding layer 503 c as a second light shielding layer, aninterlayer insulating layer 511 b as a second insulating layer, aTFT 530, adata line 506 a, astorage capacitor 516, and apixel electrode 515. - The lower
light shielding layer 503 b is formed on thesubstrate 510 a. The lowerlight shielding layer 503 b is made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, a nitride, or a material obtained by stacking the above-mentioned material that includes at least one of metals such as aluminum (Al), titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), or molybdenum (Mo). The lowerlight shielding layer 503 b has a conductivity and a light shielding property. The thickness of the lowerlight shielding layer 503 b is, for example, approximately 200 nm. - The interlayer insulating
layer 511 a is formed so as to cover thesubstrate 510 a and the lowerlight shielding layer 503 b. The interlayer insulatinglayer 511 a is made of, for example, a silicon oxide film or the like. The thickness of the interlayer insulatinglayer 511 a is, for example, approximately 400 nm to 5300 nm. - The upper
light shielding layer 503 c is formed on theinterlayer insulating layer 511 a. The upperlight shielding layer 503 c is made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, a nitride, or a material obtained by stacking the above-mentioned material that includes at least one of the same metals as the lowerlight shielding layer 503 b. The upperlight shielding layer 503 c has a conductivity and a light shielding property. The thickness of the upperlight shielding layer 503 c is, for example, approximately 100 nm. The lowerlight shielding layer 503 b and the upperlight shielding layer 503 c shield light incident from thesubstrate 510 a side, and function as a scanning line. - The interlayer insulating
layer 511 b is formed so as to cover theinterlayer insulating layer 511 a and the upperlight shielding layer 503 c. The interlayer insulatinglayer 511 b is made of, for example, a silicon oxide film or the like. The thickness of the interlayer insulatinglayer 511 b is, for example, approximately 5300 nm to 400 nm. - The
TFT 530 is provided on theinterlayer insulating layer 511 b. TheTFT 530 includes thesemiconductor layer 530 a, agate insulating layer 511 c, thegate electrode 530 g, thesource electrode 531, and thedrain electrode 532. Thesemiconductor layer 530 a is formed in an island shape on theinterlayer insulating layer 511 b. Thesemiconductor layer 530 a is made of, for example, a polycrystalline silicon film, and N-type impurity ions such as phosphorus (P) ions are implanted to thesemiconductor layer 530 a. - The
semiconductor layer 530 a has a lightly doped drain (LDD) structure that includes a data line side source-drain region 530 s (hereinafter, referred to as a source region), a pixel electrode side source-drain region 530 d (hereinafter, referred to as a drain region), achannel region 530 c, a data lineside LDD region 530 e provided between thesource region 530 s and thechannel region 530 c, and a pixel electrodeside LDD region 530 f provided between thechannel region 530 c and thedrain region 530 d. The thickness of thesemiconductor layer 530 a is, for example, approximately 50 nm. - P-type impurity ions such as boron (B) ions are doped in the
channel region 530 c. N-type impurity ions such as phosphorus (P) ions are doped in thesource region 530 s, thedrain region 530 d, the data lineside LDD region 530 e, and the pixel electrodeside LDD region 530 f. According to the configuration, theTFT 530 is formed as an N-type TFT. - The
gate insulating layer 511 c is formed so as to cover theinterlayer insulating layer 511 b and thesemiconductor layer 530 a. Thegate insulating layer 511 c is made of, for example, a silicon oxide film or the like. The gate electrode 530 g is formed on thegate insulating layer 511 c so as to be opposed to thechannel region 530 c with thegate insulating layer 511 c interposed therebetween. The gate electrode 530 g (gate wiring 503 a) is made of, for example, a polycrystalline silicon film. - The interlayer insulating
layer 511 d is formed so as to cover thegate insulating layer 511 c and thegate electrode 530 g. The interlayer insulatinglayer 511 d is made of, for example, a silicon oxide film or the like. A contact hole CH501 penetrating theinterlayer insulating layer 511 d and thegate insulating layer 511 c is formed at the position overlapped with the end portion of thesource region 530 s side of thesemiconductor layer 530 a. A contact hole CH502 penetrating theinterlayer insulating layer 511 d and thegate insulating layer 511 c is formed at the position overlapped with the end portion of thedrain region 530 d side. - The data line 506 a and a
relay electrode 506 b are formed on theinterlayer insulating layer 511 d. The data line 506 a and therelay electrode 506 b are made of, for example, a single metal, an alloy, a metal silicide, a polysilicide, a nitride, or a material obtained by stacking the above-mentioned material that includes at least one of metals such as Al, Ti, Cr, W, Ta, or Mo. The data line 506 a and therelay electrode 506 b have conductivity and a light shielding property. - The data line 506 a and the
relay electrode 506 b is obtained, for example, by forming a conductive film using the same material and patterning the conductive film. Thesource electrode 531 is formed by filling the contact hole CH501 with the material forming thedata line 506 a and therelay electrode 506 b, and thedrain electrode 532 is formed by filling the contact hole CH502. - An interlayer insulating
layer 511 e is formed so as to cover thedata line 506 a, therelay electrode 506 b, and the interlayer insulatinglayer 511 d. The interlayer insulatinglayer 511 e is made of, for example, a silicon oxide or a silicon nitride. The interlayer insulatinglayer 511 e is subjected to a planarization process for planarizing the unevenness of the surface that is caused by covering the region in which theTFT 530 is provided. As a method for the planarization process, for example, a chemical mechanical polishing (CMP) process, a spin coating process, or the like may be used. - In the interlayer insulating
layer 511 e, a contact hole CH503 penetrating theinterlayer insulating layer 511 e is formed at the position overlapped with therelay electrode 506 b. Thecapacitor line 516 a constituting a part of the storage capacitor 516 (COM potential) is formed on theinterlayer insulating layer 511 e. Thecapacitor line 516 a has a multilayer structure in which, for example, an aluminum (Al) film is disposed in the lower layer and a titanium nitride (TiN) film is disposed in the upper layer. - A
capacitor insulating film 516 b that is made of an alumina film, silicon nitride film, or the like is formed so as to cover thecapacitor line 516 a. Astopper film 516 c 1 that is made of a silicon oxide film or the like is formed on thecapacitor insulating film 516 b in the vicinity of the region overlapped with the region of a contact hole CH504 in a plan view. Thestopper film 516 c 1 may be formed, before forming thecapacitor insulating film 516 b, that is, between thecapacitor line 516 a and thecapacitor insulating film 516 b. - A
capacitor electrode 516 c constituting a part of thestorage capacitor 516 is formed on thestopper film 516 c 1, thecapacitor insulating film 516 b, and the interlayer insulatinglayer 511 e so as to overlap therelay electrode 506 b in a plan view. Thecapacitor electrode 516 c is formed by forming a conductive film using a conduction portion material having light shielding properties such as aluminum (Al) and patterning the conductive film. Thecapacitor electrode 516 c is patterned on thestopper film 516 c 1 so as to be separated from theadjacent capacitor electrode 516 c. - The
capacitor electrode 516 c is also formed in the contact hole CH503. Thus, thecapacitor electrode 516 c is electrically connected to therelay electrode 506 b via the contact hole CH503, and electrically connected to thedrain electrode 532. Thecapacitor electrode 516 c also functions as a relay electrode that electrically connects therelay electrode 506 b to thepixel electrode 515 via the contact hole CH503. - An interlayer insulating layer 511 f is formed on the
capacitor electrode 516 c. The interlayer insulating layer 511 f is made of, for example, silicon oxide or silicon nitride. The interlayer insulating layer 511 f also may be subjected to a planarization process as in theinterlayer insulating layer 511 e. The contact hole CH504 penetrating the interlayer insulating layer 511 f is formed at the position overlapped with thecapacitor electrode 516 c. The contact hole CH504 is formed, for example, on thecapacitor electrode 516 c at the position overlapped with thestopper film 516 c 1 in a plan view. - The
pixel electrode 515 is formed on the interlayer insulating layer 511 f so as to overlap with thecapacitor electrode 516 c and the contact hole CH504 in a plan view. Thepixel electrode 515 is formed with a transparent conductive film such as ITO, and also formed in the contact hole CH504. Thus, thepixel electrode 515 is electrically connected to thecapacitor electrode 516 c via the contact hole CH504, and electrically connected to thedrain electrode 532 via the contact hole CH503 and therelay electrode 506 b. - In a case where the
liquid crystal device 501 illustrated inFIG. 14 is used as the liquid crystal light bulb of the projector, light that is emitted from the light source is incident from thecounter substrate 520 side, transmitted through theliquid crystal layer 540, and emitted to theelement substrate 510 side. In theelement substrate 510 illustrated inFIG. 16 , thecapacitor electrode 516 c, thedata line 506 a, and therelay electrode 506 b shield light that is incident to thesemiconductor layer 530 a from thecounter substrate 520 side (upper side inFIG. 16 ), thereby preventing the malfunction of theTFT 530 due to light. - In recent years, there is a case where the amount of light from the light source increases and an inorganic polarizing plate having high light reflectivity compared to the related art is used in sometimes. For this reason, it is required to improve the light shielding properties of the reflected light or the like that is incident from the
element substrate 510 side (back surface) from which light of the lightliquid crystal device 501 is emitted, compared to the related art. Further, in a large liquid crystal device having a diagonal size of approximately one inch, it is highly necessary to drive using a high frequency driving signal, and thus it is also required to decrease the wiring resistance of thegate wiring 503 a. - Therefore, the
liquid crystal device 501 according to this embodiment has a light shielding configuration for shielding light incident from theelement substrate 510 side (back side), and thus the wiring resistance of the scanning line decreases by the light shielding configuration. Hereinafter, the light shielding configuration of theliquid crystal device 501 will be described with reference toFIGS. 17 and 18 . -
FIG. 17 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the fourth embodiment.FIG. 18 is a schematic sectional view taken along line XVIII-XVIII inFIG. 17 . The line XVIII-XVIII inFIG. 17 is a line along the X-direction intersecting the direction to which thesemiconductor layer 530 a extends. InFIGS. 17 and 18 , the components in the higher layers than thegate electrode 530 g (gate wiring 503 a) are not illustrated. - In the
element substrate 510 according to the fourth embodiment, the intersection portion of thegate wiring 503 a extending along the X-direction and thedata line 506 a (refer toFIG. 15 ) extending along the Y-direction is illustrated inFIG. 17 . Thesemiconductor layer 530 a of theTFT 530 extends to the both sides of the intersection portion of thegate wiring 503 a and thedata line 506 a along the Y-direction. Thesemiconductor layer 530 a is disposed so as to overlap with thedata line 506 a in a plan view. The portion of thegate wiring 503 a that is overlapped with thechannel region 530 c of thesemiconductor layer 530 a in a plan view becomes thegate electrode 530 g. In other words, thegate electrode 530 g overlaps with thechannel region 530 c of thesemiconductor layer 530 a in a plan view. - The lower
light shielding layer 503 b and the upperlight shielding layer 503 c are disposed so as to overlap with thegate wiring 503 a in a plan view, and provided between the pixels P (refer toFIG. 13 ) in the X-direction. The lowerlight shielding layer 503 b and the upperlight shielding layer 503 c are disposed at the intersection portion of thegate wiring 503 a and thedata lines 506 a so as to overlap with at least thechannel region 530 c of thesemiconductor layer 530 a in a plan view. - As described above, the
TFT 530 is provided in the vicinity of the intersection portion of the non-opening region between the pixels P that has a light shielding property, and thus it is possible to prevent the malfunction of theTFT 530 due to light, and ensure the aperture ratio of the opening region of the pixel P. - As illustrated in
FIGS. 17 and 18 , a contact hole CH505 as a third contact hole penetrating thegate insulating layer 511 c and the interlayer insulatinglayer 511 b, and a contact hole CH506 as a fourth contact hole are formed at both outsides of thesemiconductor layer 530 a (channel region 530 c) in the X-direction. The contact holes CH505 and CH506 are filled with the material forming thegate electrode 530 g (gate wiring 503 a), and thus thegate electrode 530 g (gate wiring 503 a) is electrically connected to the upperlight shielding layer 503 c. - A contact hole CH507 as a first contact hole penetrating the
interlayer insulating layer 511 a, and a contact hole CH508 as a second contact hole are formed at both outsides of thesemiconductor layer 530 a (channel region 530 c) in the X-direction. The contact hole CH507 is disposed at a further outside of thesemiconductor layer 530 a than the contact hole CH505, and the contact hole CH508 is disposed at a further outside of thesemiconductor layer 530 a than the contact hole CH506. - The contact holes CH507 and CH508 are filled with the material forming the upper
light shielding layer 503 c, and thus the upperlight shielding layer 503 c that is electrically connected to thegate electrode 530 g (gate wiring 503 a) is electrically connected to the lowerlight shielding layer 503 b. In other words, both of the upperlight shielding layer 503 c and the lowerlight shielding layer 503 b are set to the same potential as that of thegate electrode 530 g. Therefore, the scanning line is configured with the three layers of thegate wiring 503 a, the upperlight shielding layer 503 c, and the lowerlight shielding layer 503 b. - The positions of the contact holes CH507 and CH508 are not particularly limited. However, there is a case where a recess occurs at the positions of the contact holes CH507 and CH508 on the surface of the upper
light shielding layer 503 c. Therefore, it is preferably that the contact holes CH507 and CH508 are disposed so as not to overlap with the upper contact holes CH505 and CH506 in a plan view. - In the
element substrate 510 according to the fourth embodiment, the upperlight shielding layer 503 c and the lowerlight shielding layer 503 b are disposed between thesemiconductor layer 530 a and thesubstrate 510 a so as to overlap with thesemiconductor layer 530 a in a plan view. Therefore, it is possible to shield light incident to thesemiconductor layer 530 a from thesubstrate 510 a side. - A pair of light shielding portions along the Z-direction that are formed by the contact holes CH505 and CH506 penetrating the
interlayer insulating layer 511 b beneath thesemiconductor layer 530 a, and a pair of light shielding portions along the Z-direction that are formed by the contact holes CH507 and CH508 penetrating theinterlayer insulating layer 511 a beneath the upperlight shielding layer 503 c, are disposed at both outsides of thesemiconductor layer 530 a. Therefore, it is possible to shield light that is incident at an angle with respect to the Z-direction from thesubstrate 510 a side, and light reflected and propagated between thegate wiring 503 a and the upperlight shielding layer 503 c or between the upperlight shielding layer 503 c and the lowerlight shielding layer 503 b, from both outsides of thesemiconductor layer 530 a. - Hereinafter, the light shielding effect of the
element substrate 510 according to the fourth embodiment will be described in comparison with the element substrate having the configuration of the related art.FIG. 19 is a graph illustrating the light shielding effect of the element substrate according to the fourth embodiment.FIG. 27 is a schematic plan view illustrating a configuration example of the TFT portion of the element substrate of the related art.FIG. 28 is a schematic sectional view taken along line XXVIII-XXVIII inFIG. 27 . InFIGS. 27 and 28 , the components in the higher layers than thegate electrode 530 g (gate wiring 503 a) are not illustrated. - It is assumed that the
element substrate 560 of the related art illustrated inFIGS. 27 and 28 is different from theelement substrate 510 according to the fourth embodiment in that the light shielding layer disposed between thesemiconductor layer 530 a and thesubstrate 510 a has a single layer (only the lowerlight shielding layer 503 b). The thickness of the lowerlight shielding layer 503 b is approximately 200 nm, similarly to theelement substrate 510. The lowerlight shielding layer 503 b is electrically connected to thegate electrode 530 g (gate wiring 503 a) via the contact holes CH505 and CH506. In other words, in theelement substrate 560 of the related art, the scanning line is configured with the two layers of thegate wiring 503 a and the lowerlight shielding layer 503 b. - As illustrated in
FIG. 28 , in theelement substrate 560 of the related art, a part of incident light L that is incident at an angle with respect to the normal direction of thesubstrate 510 a (Z-direction) from thesubstrate 510 a side is reflected at the interface between thesubstrate 510 a and the lowerlight shielding layer 503 b. Another part of incident light L is absorbed into the lowerlight shielding layer 503 b and transmitted through the lowerlight shielding layer 503 b. A part of the transmitted light is incident to thechannel region 530 c of thesemiconductor layer 530 a. In contrast, as illustrated inFIG. 18 , in theelement substrate 510 according to the fourth embodiment, incident light L incident from thesubstrate 510 a side is reflected at the interface between thesubstrate 510 a and the lowerlight shielding layer 503 b. Further, a part of light that is transmitted through the lowerlight shielding layer 503 b is reflected at the interface between the interlayer insulatinglayer 511 a and the upperlight shielding layer 503 c. Therefore, it is possible to more effectively shield light incident to thechannel region 530 c of thesemiconductor layer 530 a. - In
FIG. 19 , the horizontal axis represents the wavelength (nm) of incident light L, and the vertical axis represents the transmittance (%) of incident light L transmitted through the light shielding layer. The light shielding layer with a single layer (film thickness of 200 nm) illustrated inFIG. 19 represents the transmittance according to the configuration of theelement substrate 560, and the two layers of the light shielding layer (film thickness of 100 nm+200 nm) represents the transmittance according to the configuration of theelement substrate 510 of the fourth embodiment. The two layers of the light shielding layer (film thickness of 100 nm+100 nm) represents the transmittance according to a comparative example in which the thickness of the lowerlight shielding layer 503 b in theelement substrate 510 is set to 100 nm. - As illustrated in
FIG. 19 , the transmittance according the configuration of theelement substrate 510 of the fourth embodiment remarkably decreases, compared to the transmittance according to the configuration of theelement substrate 560 in the related art. This shows that the light shielding properties are improved than the related art by further providing the upperlight shielding layer 503 c between thesemiconductor layer 530 a and the lowerlight shielding layer 503 b. - In the comparative example in which the thickness of the lower
light shielding layer 503 b in theelement substrate 510 is set to 100 nm, although the total thickness of the two layers of the light shielding layer is 200 nm and the same as that of theelement substrate 560 in the related art, the transmittance according to the comparative example decreases, compared to the transmittance according to the configuration of theelement substrate 560 in the related art. This shows that even though the (total) thickness of the light shielding layer is the same, the two layers of the light shielding layer that have the interlayer insulating layer (interlayer insulating layer 511 a) interposed therebetween is provided, and thus the reflection at the interface increases, thereby improving the light shielding properties compared to the related art. InFIG. 19 , although the range of the horizontal axis is set to substantially the center of a visible light wavelength region, the magnitude relationship in the transmittance is substantially the same in the entire visible light wavelength region. - In the configuration of the
element substrate 510 according to the fourth embodiment, when the thickness of the lowerlight shielding layer 503 b and the thickness of the upperlight shielding layer 503 c are set to 200 nm (two layers of 200 nm+200 nm), the light shielding properties are expected to be further improved. However, the step that occurs in the upper layer due to the two layers of the light shielding layer becomes larger, and thus it is preferably that the thickness of the upperlight shielding layer 503 c is set to 100 nm. - In the
element substrate 560 in the related art, the scanning line is configured with the two layers of thegate wiring 503 a and the lowerlight shielding layer 503 b. In contrast, in theelement substrate 510 according to the fourth embodiment, the scanning line is configured with the three layers of thegate wiring 503 a, the lowerlight shielding layer 503 b, and the upperlight shielding layer 503 c, and thus it is possible to decrease the wiring resistance of the scanning line, compared to the related art. Therefore, even when theliquid crystal device 501 is a large liquid crystal device that is driven by a high frequency driving signal, it is possible to decrease the wiring resistance of the scanning line, while improving the light shielding properties of incident light L incident from thesubstrate 510 a side, compared to the related art. - The lower
light shielding layer 503 b and the upperlight shielding layer 503 c are provided straddling the boundary between the pixels P, and thus the contact holes CH507 and CH508 for electrically connecting the lowerlight shielding layer 503 b and the upperlight shielding layer 503 c may not be provided for each pixel P. In other words, in a case where the lowerlight shielding layer 503 b and the upperlight shielding layer 503 c are formed straddling the boundary between the pixels P, the number of the contact holes CH507 and CH508 may be less than the number of the pixels P. - As described above, according to the configuration of the
element substrate 510 of the fourth embodiment, the following effects can be obtained. - (6) The lower
light shielding layer 503 b, theinterlayer insulating layer 511 a, and the upperlight shielding layer 503 c are disposed between thesubstrate 510 a and thesemiconductor layer 530 a. Thus, incident light L incident from thesubstrate 510 a side toward thesemiconductor layer 530 a side is reflected at the interface between thesubstrate 510 a and the lowerlight shielding layer 503 b, and further reflected at the interface between the interlayer insulatinglayer 511 a and the upperlight shielding layer 503 c. Therefore, it is possible to effectively shield incident light L incident from thesubstrate 510 a side to thesemiconductor layer 530 a. Further, the lowerlight shielding layer 503 b and the upperlight shielding layer 503 c are set to have the same potential as that of thegate electrode 530 g, and thus it is possible to configure the scanning line using the three layers that includes the two layers of thegate wiring 503 a and the light shielding layer, thereby decreasing the wiring resistance of the scanning line. As a result, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding properties compared to the related art, thereby providing theliquid crystal device 501 having a high display quality. - (7) The lower
light shielding layer 503 b and the upperlight shielding layer 503 c that constitute the scanning line are formed straddling the boundary between the pixels P, and thus, even in a case where theliquid crystal device 501 is a large liquid crystal device including the scanning line with a long length, it is possible to decrease the wiring resistance of the scanning line while improving the light shielding property. - (8) The pair of the light shielding portions along the Z-direction are formed between the lower
light shielding layer 503 b and the upperlight shielding layer 503 c by the contact holes CH507 and CH508 penetrating theinterlayer insulating layer 511 a. The pair of the light shielding portions are disposed at both sides of thesemiconductor layer 530 a in a plan view. Therefore, it is possible to shield incident light L that is incident at an angle with respect to the Z-direction from thesubstrate 510 a side, and light reflected and propagated between the upperlight shielding layer 503 c and the lowerlight shielding layer 503 b, from both sides of thesemiconductor layer 530 a, by the light shielding portions formed by the contact holes CH507 and CH508, thereby further improving the light shielding property. - (9) The pair of light shielding portions along the Z-direction are formed by the contact holes CH505 and CH506 penetrating the
gate insulating layer 511 c and the interlayer insulatinglayer 511 b. The pair of light shielding portions are disposed at both outsides of thesemiconductor layer 530 a in a plan view. Therefore, it is possible to shield incident light L that is incident at an angle with respect to the Z-direction from thesubstrate 510 a side, and light reflected and propagated between thegate wiring 503 a and the upperlight shielding layer 503 c, from both outsides of thesemiconductor layer 530 a, by the light shielding portions formed by the contact holes CH505 and CH506, thereby further improving the light shielding property. - Next, the light shielding configuration of the element substrate according to a fifth embodiment will be described with reference to
FIGS. 20 and 21 .FIG. 20 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the fifth embodiment.FIG. 21 is a schematic sectional view taken along line XXI-XXI inFIG. 20 . - The
element substrate 510A according to the fifth embodiment has the same configuration as that of theelement substrate 510 according to the fourth embodiment, except that the upperlight shielding layer 503 d as a second light shielding layer is formed to be separated for each pixel P. Hereinafter, the differences from the fourth embodiment will be described. The same reference numerals are given to the same components as those of the fourth embodiment, and detailed description thereof will be omitted. - As illustrated in
FIGS. 20 and 21 , theelement substrate 510A according to the fifth embodiment is provided with the lowerlight shielding layer 503 b, theinterlayer insulating layer 511 a, and the upperlight shielding layer 503 d, between thesubstrate 510 a and thesemiconductor layer 530 a. In the fourth embodiment, the upperlight shielding layer 503 c is provided straddling the boundary between the pixels P in the X-direction. In contrast, in the fifth embodiment, the upperlight shielding layer 503 d is provided to be separated for each pixel P, and the lowerlight shielding layer 503 b is formed straddling the boundary between the pixels P. - The upper
light shielding layer 503 d according to the fifth embodiment is formed of the same material as that of the upperlight shielding layer 503 c according to the fourth embodiment, and formed to have the same thickness as that of the upperlight shielding layer 503 c according to the fourth embodiment. The upperlight shielding layer 503 d is electrically connected to the lowerlight shielding layer 503 b via the contact holes CH507 and CH508 penetrating theinterlayer insulating layer 511 a. The contact hole CH507 is disposed at a further outside of thesemiconductor layer 530 a than the contact hole CH505, and the contact hole CH508 is disposed at a further outside of thesemiconductor layer 530 a than the contact hole CH506. - According to the configuration of the
element substrate 510A of the fifth embodiment, even though the upperlight shielding layer 503 d is separated for each pixel P, the lowerlight shielding layer 503 b, theinterlayer insulating layer 511 a, and the upperlight shielding layer 503 d are disposed between thesubstrate 510 a and thesemiconductor layer 530 a, and thus it is possible to improve the light shielding properties compared to the related art, similarly to the fourth embodiment. Even in a case where, as in theelement substrate 560 in the related art that is illustrated inFIGS. 27 and 28 , only the lowerlight shielding layer 503 b is disposed between thesubstrate 510 a and thesemiconductor layer 530 a, it is possible to decrease the wiring resistance of the scanning line. The configuration according to the fifth embodiment can be applied to a case where the size of theliquid crystal device 501 is small and decreasing the wiring resistance of the scanning line is not important. - According to the configuration of the
element substrate 510A of the fifth embodiment, the following effects can be obtained. - (10) Even though the upper
light shielding layer 503 d is separated for each pixel P, the lowerlight shielding layer 503 b, theinterlayer insulating layer 511 a, and the upperlight shielding layer 503 d are disposed between thesubstrate 510 a and thesemiconductor layer 530 a, and thus it is possible to improve the light shielding properties compared to the related art, similarly to the fourth embodiment. Further, it is possible to decrease the wiring resistance of the scanning line. - Next, the light shielding configuration of the element substrate according to a sixth embodiment will be described with reference to
FIGS. 22 and 23 .FIG. 22 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the sixth embodiment.FIG. 23 is a schematic sectional view taken along line XXIII-XXIII inFIG. 22 . - The
element substrate 510B according to the sixth embodiment is similar to theelement substrate 510A according to the fifth embodiment, in that the upperlight shielding layer 503 e as a second light shielding layer is formed to be separated for each pixel P. However, theelement substrate 510B according to the sixth embodiment is different from theelement substrate 510A according to the fifth embodiment, in that the contact holes CH505 and CH506 are disposed so as to overlap with the contact holes CH507 and CH508 in a plan view. Hereinafter, the differences from the above-described embodiment will be described. The same reference numerals are given to the same components as those of the above-described embodiment, and detailed description thereof will be omitted. - As illustrated in
FIGS. 22 and 23 , theelement substrate 510B according to the sixth embodiment is provided with the lowerlight shielding layer 503 b, theinterlayer insulating layer 511 a and the upperlight shielding layer 503 e, between thesubstrate 510 a and thesemiconductor layer 530 a. The contact holes CH507 and CH508 is formed in theinterlayer insulating layer 511 a, and arecess portion 534 recessed from the surface (upper surface) is formed in the region including the contact holes CH507 and CH508. - The upper
light shielding layer 503 e according to the sixth embodiment is formed of the same material as that of the upperlight shielding layer 503 c according to the fourth embodiment, and formed to have the same thickness as that of the upperlight shielding layer 503 c according to the fourth embodiment. The upperlight shielding layer 503 e is separated for each pixel P, and formed so as to fill therecess portion 534 and the contact holes CH507 and CH508 that are provided in theinterlayer insulating layer 511 a. The surface of the upperlight shielding layer 503 e is a substantially flat surface that also includes the positions of the contact holes CH507 and CH508. The surface of the upperlight shielding layer 503 e and the surface of the interlayer insulatinglayer 511 a form a substantially flat surface. The upperlight shielding layer 503 e is electrically connected to the lowerlight shielding layer 503 b via the contact holes CH507 and CH508. - The
element substrate 510B according to the sixth embodiment can be manufactured as follows. After forming the contact holes CH507 and CH508 in theinterlayer insulating layer 511 a, therecess portion 534 is formed by etching theinterlayer insulating layer 511 a from the surface side. Then, the material of the upperlight shielding layer 503 e is placed so as to fill therecess portion 534 and the contact holes CH507 and CH508, and the upperlight shielding layer 503 e is patterned. Then, a planarization process for planarizing the surface of the upperlight shielding layer 503 e and the surface of the interlayer insulatinglayer 511 a is performed. - In the
element substrate 510B according to the sixth embodiment, the contact hole CH507 is disposed so as to overlap with the contact hole CH505 in a plan view, and the contact hole CH508 is disposed so as to overlap with the contact hole CH506 in a plan view. In theelement substrate 510B, the surface of the upperlight shielding layer 503 e is a substantially flat surface, and thus the positions of the contact holes CH505 and CH506 to be formed on the upper layer of the upperlight shielding layer 503 e are not restricted. In other words, the positions of the contact holes CH507 and CH508 are not restricted with respect to the positions of the contact holes CH505 and CH506. - Therefore, it is possible to reduce the size of the region that is shielded by the contact holes CH505, CH506, CH507 and CH508, thereby improving the aperture ratio of the
liquid crystal device 501. Accordingly, the configuration of theelement substrate 510B according to the sixth embodiment is suitable in a case where theliquid crystal device 501 is a small high-definition liquid crystal device in which the arrangement pitch of the pixels P is narrow. Further, the surface of the upperlight shielding layer 503 e and the surface of the interlayer insulatinglayer 511 a are a substantially flat surface, and thus it is possible to decrease the step that occurs in the upper layer due to the thickness of the upperlight shielding layer 503 e. - According to the configuration of the
element substrate 510B of the sixth embodiment, the following effects can be obtained. - (11) Even though the upper
light shielding layer 503 e is separated for each pixel P, the lowerlight shielding layer 503 b, theinterlayer insulating layer 511 a, and the upperlight shielding layer 503 e are disposed between thesubstrate 510 a and thesemiconductor layer 530 a, and thus it is possible to improve the light shielding properties compared to the related art, similarly to the fourth embodiment. Further, it is possible to decrease the wiring resistance of the scanning line. - (12) The upper
light shielding layer 503 e having a substantially flat surface is formed on theinterlayer insulating layer 511 a by filling the pair of the contact holes CH507 and CH508 penetrating theinterlayer insulating layer 511 a. Therefore, in a case of forming the contact holes CH505 and CH506 for electrical connection from the upper side to the upperlight shielding layer 503 e, the positions of the contact holes CH505 and CH506 are not restricted, and thus it is possible to increase the degree of freedom in the wiring pattern design. - (13) The pair of the contact holes CH507 and CH508 that penetrate the interlayer insulating
layer 511 a and electrically connect the lowerlight shielding layer 503 b and the upperlight shielding layer 503 e are disposed so as to overlap with the pair of the contact holes CH505 and CH506 that penetrate thegate insulating layer 511 c and the interlayer insulatinglayer 511 b and electrically connect thegate electrode 530 g and the upperlight shielding layer 503 e in a plan view. Therefore, it is possible to reduce the size of the region that is shielded by the contact holes CH505, CH506, CH507 and CH508, thereby improving the aperture ratio of theliquid crystal device 501. - Next, the light shielding configuration of an element substrate according to a seventh embodiment will be described with reference to
FIGS. 24 and 25 .FIG. 24 is a schematic plan view illustrating the configuration of the TFT portion of the element substrate according to the seventh embodiment.FIG. 25 is a schematic sectional view taken along line XXV-XXV inFIG. 24 . The line XXV-XXV inFIG. 24 is a line along the Y-direction to which thesemiconductor layer 530 a extends. - The
element substrate 510C according to the seventh embodiment is different from theelement substrates layer 511 a and electrically connects the lowerlight shielding layer 503 b and an upperlight shielding layer 503 f as a second light shielding layer is disposed at the position overlapped with thechannel region 530 c of thesemiconductor layer 530 a in a plan view. Hereinafter, the differences from the above-described embodiments will be described. The same reference numerals are given to the same components as those of the above-described embodiments, and detailed description thereof will be omitted. - As illustrated in
FIGS. 24 and 25 , theelement substrate 510C according to the seventh embodiment is provided with the lowerlight shielding layer 503 b, theinterlayer insulating layer 511 a, and the upperlight shielding layer 503 f between thesubstrate 510 a and thesemiconductor layer 530 a. The upperlight shielding layer 503 f according to the seventh embodiment is formed of the same material as that of the upperlight shielding layer 503 c according to the fourth embodiment, and formed to have the same thickness as that of the upperlight shielding layer 503 c according to the fourth embodiment. Further, the contact holes CH505 and CH506 are disposed at both outsides of thesemiconductor layer 530 a in a plan view (refer toFIG. 24 ), similarly to the fourth embodiment. - In the interlayer insulating
layer 511 a, a through hole 535 (contact hole CH509 as a fifth contact hole) is provided at the position overlapped with thechannel region 530 c of thesemiconductor layer 530 a in a plan view. It is preferably that the throughhole 535 is formed in a region that includes thechannel region 530 c of thesemiconductor layer 530 a and is wider than thechannel region 530 c in the X-direction and the Y-direction. The length of the throughhole 535 along the Y-direction is, for example, approximately 2 μm, and the depth of the throughhole 535 is, for example, approximately 0.5 μm. - As illustrated in
FIG. 25 , the throughhole 535 is provided in the region overlapped with the lowerlight shielding layer 503 b in a plan view. Thus, at the time of forming the throughhole 535 in theinterlayer insulating layer 511 a, the lowerlight shielding layer 503 b is exposed into the throughhole 535. In this specification, the side portion (inclined surface) of the throughhole 535 formed in theinterlayer insulating layer 511 a is referred to as theside portion 535 b of the contact hole CH509, and the surface of the lowerlight shielding layer 503 b exposed into the throughhole 535 is referred to as thebottom portion 535 a of the contact hole CH509. - In the sectional view taken along the extending direction of the
semiconductor layer 530 a illustrated inFIG. 25 , the upperlight shielding layer 503 f is disposed across thebottom portion 535 a of the contact hole CH509 (the surface of the lowerlight shielding layer 503 b exposed into the through hole 535), theside portions 535 b of the contact hole CH509, and the surface of the interlayer insulatinglayer 511 a positioned at the outside of the contact hole CH509. The upperlight shielding layer 503 f is electrically connected to the lowerlight shielding layer 503 b while being contact with the lowerlight shielding layer 503 b at thebottom portion 535 a of the contact hole CH509. - As described above, the upper
light shielding layer 503 f is formed in a recessed shape in a sectional view. Thus, the upperlight shielding layer 503 f is disposed so as to cover thebottom portion 535 a of which thechannel region 530 c of thesemiconductor layer 530 a is disposed on the upper layer, theside portions 535 b, and the surface of the interlayer insulatinglayer 511 a at the outside of the side portion. Therefore, it is possible to effectively shield light incident to thechannel region 530 c. - The interlayer insulating
layer 511 b is formed so as to cover theinterlayer insulating layer 511 a and the upperlight shielding layer 503 f. In a case where the thickness of the interlayer insulatinglayer 511 b formed on theinterlayer insulating layer 511 a is approximately 5300 nm to 400 nm as described above, the thickness of the interlayer insulatinglayer 511 b at theside portion 535 b of the contact hole CH509 is, for example, approximately 200 nm. The shape of the upperlight shielding layer 503 f formed along thebottom portion 535 a and theside portions 535 b of the contact hole CH509 is reflected in the surface of the interlayer insulatinglayer 511 b, and thus arecess portion 536 that includes abottom portion 536 a corresponding to thebottom portion 535 a andside portions 536 b corresponding to theside portions 535 b, is formed on the surface side of the interlayer insulatinglayer 511 b. The length of thebottom portion 536 a along the Y-direction is, for example, approximately 1.5 μm. - The
semiconductor layer 530 a is disposed on theinterlayer insulating layer 511 b so as to cover the upperlight shielding layer 503 f along thebottom portion 536 a and theside portions 536 b of therecess portion 536. As described above, thesemiconductor layer 530 a is formed in a recessed shape in a sectional view, and thus it is possible to make the substantial length of thesemiconductor layer 530 a longer than the length DD of thesemiconductor layer 530 a in a plan view that is illustrated inFIG. 24 . - In other words, it is possible to make the length DD of the
semiconductor layer 530 a in a plan view shorter than the length of thesemiconductor layer 530 a that is originally required. Therefore, it is possible to reduce the size of the light shielding region, thereby improving the aperture ratio of theliquid crystal device 501. Accordingly, the configuration of theelement substrate 510C according to the seventh embodiment is suitable in a case where theliquid crystal device 501 is a small high-definition liquid crystal device in which the arrangement pitch of the pixels P is narrow. - The
gate insulating layer 511 c is formed so as to cover theinterlayer insulating layer 511 b and thesemiconductor layer 530 a. The gate electrode 530 g is formed on thegate insulating layer 511 c so as to be opposed to thechannel region 530 c. The shape of therecess portion 536 is also reflected in the surface of thegate insulating layer 511 c, and thus thegate electrode 530 g is also formed along thebottom portion 536 a and theside portions 536 b of therecess portion 536. Accordingly, it is possible to reduce the width of thegate electrode 530 g in a plan view. The gate electrode 530 g is formed at both outsides of thesemiconductor layer 530 a (channel region 530 c) in the X-direction, and electrically connected to the upperlight shielding layer 503 f via the contact holes CH505 and CH506 penetrating thegate insulating layer 511 c and the interlayer insulatinglayer 511 b (refer toFIG. 24 ). - Here, at least the
channel region 530 c of thesemiconductor layer 530 a is preferably disposed on thebottom portion 536 a of therecess portion 536. Thechannel region 530 c is disposed on thebottom portion 536 a of therecess portion 536, and thus it is possible to ensure the channel length of thechannel region 530 c. In addition, it is possible to dispose the data lineside LDD region 530 e and the pixel electrodeside LDD region 530 f that are disposed at both outsides of thechannel region 530 c in a region from thebottom portion 536 a to the outsides of therecess portion 536 via theside portions 536 b. Thus, it is possible to ensure the LDD region having a sufficient length. Therefore, even in a case where theliquid crystal device 501 is a small high-definition liquid crystal device in which the arrangement pitch of the pixels P is narrow, it is possible to form theTFT 530 having excellent operation characteristics. - It is assumed that the diameter of the
bottom portion 535 a of the contact hole CH509 (through hole 535) formed in the lower sideinterlayer insulating layer 511 a is appropriately set such that the diameter of thebottom portion 536 a is equal to or greater than the desired channel length of thechannel region 530 c. - According to the configuration of the
element substrate 510C of the seventh embodiment, the following effects can be obtained. - (14) In the sectional view taken along the extending direction of the
semiconductor layer 530 a, the upperlight shielding layer 503 f is disposed across thebottom portion 535 a of the contact hole CH509 penetrating theinterlayer insulating layer 511 a, theside portions 535 b of the contact hole CH509, and the surface of the interlayer insulatinglayer 511 a at the outsides of the contact hole CH509. Thesemiconductor layer 530 a is disposed so as to cover the upperlight shielding layer 503 f via theinterlayer insulating layer 511 b. Therefore, it is possible to make the substantial length of thesemiconductor layer 530 a longer than the length DD of the semiconductor layer in a plan view. In other words, it is possible to make the length DD of thesemiconductor layer 530 a in a plan view shorter than the length of thesemiconductor layer 530 a that is required. Thus, it is possible to reduce the size of the light shielding region, thereby improving the aperture ratio of theliquid crystal device 501. - (15) At least the
channel region 530 c of thesemiconductor layer 530 a is disposed on thebottom portion 535 a of the contact hole CH509. Thus, even in a case where the size of theliquid crystal device 501 is small, it is possible to ensure the channel length of thechannel region 530 c. In a case where the data lineside LDD region 530 e and the pixel electrodeside LDD region 530 f are disposed at both outsides of thechannel region 530 c, it is possible to dispose the data lineside LDD region 530 e and the pixel electrodeside LDD region 530 f in a region from thebottom portion 535 a to the outsides of the contact hole CH509 via theside portions 535 b. Thus, it is possible to ensure the LDD region having a sufficient length. Therefore, it is possible to form theTFT 530 with excellent operating characteristics. Further, the upperlight shielding layer 503 f that is disposed in the lower layer of thesemiconductor layer 530 a is disposed so as to cover thebottom portion 535 a of the contact hole on which thechannel region 530 c is disposed, theside portions 535 b of the contact hole, and the surface of the interlayer insulatinglayer 511 a at the outsides of the contact hole CH509. Thus, it is possible to effectively shield light incident to thechannel region 530 c. - The configuration of the
element substrate 510C according to the seventh embodiment can be also applied to the fourth embodiment, the fifth embodiment, and the sixth embodiment. - Next, an electronic apparatus according to an eighth embodiment will be described with reference to
FIG. 26 .FIG. 26 is a schematic diagram illustrating the configuration of a projector as an electronic apparatus according to the eighth embodiment. - As illustrated in
FIG. 26 , the projector (projection type display apparatus) 2100 as an electronic apparatus according to the eighth embodiment includes apolarization illumination device 2110, twodichroic mirrors reflection mirrors relay lenses crystal light bulbs dichroic prism 2116 as a light synthesizing element, and aprojection lens 2117. - The
polarization illumination device 2110 includes alamp unit 2101 as a light source that is configured by a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, anintegrator lens 2102, and apolarization conversion element 2103. Thelamp unit 2101, theintegrator lens 2102, and thepolarization conversion element 2103 are disposed along the system optical axis Lx. - The
dichroic mirror 2104 reflects red light (R) among polarized light beams emitted from thepolarization illumination device 2110, and transmits green light (G) and blue light (B). Anotherdichroic mirror 2105 reflects the green light (G) transmitted through thedichroic mirror 2104, and transmits the blue light (B). - The red light (R) reflected by the
dichroic mirror 2104 is reflected by thereflection mirror 2106, and then incident to the liquidcrystal light bulb 2121 via therelay lens 2115. The green light (G) reflected by thedichroic mirror 2105 is incident to the liquidcrystal light bulb 2122 via therelay lens 2114. The blue light (B) transmitted through thedichroic mirror 2105 is incident to the liquidcrystal light bulb 2123 via a light guide system that is configured by threerelay lenses reflection mirrors - The projection type liquid
crystal light bulbs dichroic prism 2116. Each color light incident to the liquidcrystal light bulbs dichroic prism 2116. - The cross
dichroic prism 2116 is formed by bonding four right-angle prisms. In the inner surface of the prism, a dielectric multilayer film that reflects the red light and a dielectric multilayer film that reflects the blue light are formed in a cross shape. Three color light beams are synthesized by the dielectric multilayer films, and thus light beams representing a color image are synthesized. Light beams that are synthesized are projected on ascreen 2130 by theprojection lens 2117 as a projection optical system, and thus the image is enlarged and displayed. - The
liquid crystal device 501 according to the above-described embodiment is applied to the liquidcrystal light bulb 2121. The liquidcrystal light bulb 2121 is disposed with a gap between a pair of polarization elements that are disposed in a crossed nicol state at the incident side and the emitting side of the color light. The other liquidcrystal light bulbs crystal light bulb 2121. - According to the configuration of the
projector 2100 of the eight embodiment, even though the plurality of pixels P are disposed with high precision, there is provided theliquid crystal device 501 that has high aperture ratio in the pixel region in which light is transmitted and can prevent the occurrence of light leakage current in theTFT 530. Thus, it is possible to provide theprojector 2100 that has high quality and emits bright light. - The embodiment according to the invention is not limited to the embodiment described above, and can be suitably modified within a scope without departing from the essence or spirit of the invention read from the claims and the entire specification. The modification example of the invention falls within a technical scope of the invention, and may be implemented in the following forms.
- As described above, the light shielding layer in the peripheral region E1 is not limited to only the first light shielding layer 3
c 1, and two layers of the first light shielding layer 3 c 1 and the second light shielding layer 3c 2 may be disposed. - The second light shielding layer 3
c 2 according to the first embodiment is not limited to be in a floating state, for example, and may be electrically connected to thegate electrode 30 g by providing a contact hole. - The element substrates 510, 510A, 510B, and 510C according to the embodiments have a configuration in which the thickness of the lower
light shielding layer 503 b is thick (approximately 200 nm) and the thicknesses of the upperlight shielding layers light shielding layer 503 b is thin (approximately 100 nm) and the thicknesses of the upperlight shielding layers - The
element substrates light shielding layer 503 b is formed straddling the boundary between the pixels P and the upperlight shielding layers light shielding layer 503 b is separated for each pixel P and the upperlight shielding layers - The display apparatus that can apply the light shielding configurations of the
element substrates liquid crystal device 501. The light shielding configurations of theelement substrates - The electronic apparatus that can apply the
liquid crystal device 501 according to the embodiment is not limited to theprojector 2100. Theliquid crystal device 501 can be suitably used, for example, as a projection type HUD (head-up display) or a direct-view type HMD (head-mounted display), or a display unit of an information terminal device such as an electronic book, a personal computer, a digital still camera, a liquid crystal television, a view finder type or monitor direct-view type video recorder, a car navigation system, an electronic organizer, or a POS. - The entire disclosure of Japanese Patent Application No. 2015-227375, filed Nov. 20, 2015 and 2015-212624, filed Oct. 29, 2015 are expressly incorporated by reference herein.
Claims (20)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015-212624 | 2015-10-29 | ||
JP2015212624A JP2017083679A (en) | 2015-10-29 | 2015-10-29 | Display device and electronic apparatus |
JP2015227375A JP2017097086A (en) | 2015-11-20 | 2015-11-20 | Liquid crystal device and electronic apparatus |
JP2015-227375 | 2015-11-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20170123250A1 true US20170123250A1 (en) | 2017-05-04 |
US10088727B2 US10088727B2 (en) | 2018-10-02 |
Family
ID=58635409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/331,007 Active 2037-03-14 US10088727B2 (en) | 2015-10-29 | 2016-10-21 | Liquid crystal device and electronic apparatus |
Country Status (1)
Country | Link |
---|---|
US (1) | US10088727B2 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108535925A (en) * | 2018-03-20 | 2018-09-14 | 厦门天马微电子有限公司 | Display panel and display device |
US10254608B2 (en) * | 2015-08-21 | 2019-04-09 | Samsung Display Co., Ltd. | Display device |
CN109887987A (en) * | 2019-04-17 | 2019-06-14 | 昆山国显光电有限公司 | A kind of array substrate and display module |
US20190391424A1 (en) * | 2018-06-20 | 2019-12-26 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
CN112164701A (en) * | 2020-09-29 | 2021-01-01 | 厦门天马微电子有限公司 | Array substrate and display panel |
US20210013238A1 (en) * | 2019-07-09 | 2021-01-14 | Sharp Kabushiki Kaisha | Active matrix substrate and method for manufacturing same |
US11092862B2 (en) | 2018-06-22 | 2021-08-17 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US20210376279A1 (en) * | 2020-06-01 | 2021-12-02 | Samsung Display Co., Ltd. | Display apparatus and electronic apparatus |
US20210408483A1 (en) * | 2019-01-11 | 2021-12-30 | Japan Display Inc. | Display device |
US20220140014A1 (en) * | 2020-11-05 | 2022-05-05 | Samsung Display Co., Ltd. | Display device and electronic apparatus |
US11424274B2 (en) * | 2020-01-30 | 2022-08-23 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US11515338B2 (en) * | 2019-04-16 | 2022-11-29 | Samsung Display Co., Ltd. | Display device having light shielding pattern |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102552266B1 (en) | 2018-01-31 | 2023-07-07 | 삼성디스플레이 주식회사 | Display device |
KR20200110573A (en) * | 2019-03-15 | 2020-09-24 | 삼성디스플레이 주식회사 | Display device |
KR20220005180A (en) * | 2020-07-06 | 2022-01-13 | 엘지디스플레이 주식회사 | Display device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030025848A1 (en) * | 2001-08-03 | 2003-02-06 | Nec Corporation | TFT array substrate and active-matrix addressing liquid-crystal display device |
US20040149989A1 (en) * | 2003-01-31 | 2004-08-05 | Nec Corporation | Thin film transistor, TFT substrate and liquid crystal display unit |
US20050007512A1 (en) * | 2003-07-11 | 2005-01-13 | Nec Corporation | Thin-film transistor with set trap level densities, and method of manufactures |
US20050078240A1 (en) * | 2003-08-29 | 2005-04-14 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US20120256184A1 (en) * | 2009-12-17 | 2012-10-11 | Sharp Kabushiki Kaisha | Semiconductor device, active matrix substrate and display device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3374717B2 (en) | 1997-09-11 | 2003-02-10 | セイコーエプソン株式会社 | Liquid crystal display panel manufacturing method |
JP3767696B2 (en) | 2001-08-03 | 2006-04-19 | 日本電気株式会社 | Thin film transistor array substrate and active matrix liquid crystal display device |
JP3605823B2 (en) | 2001-08-03 | 2004-12-22 | 日本電気株式会社 | Thin film transistor array substrate and active matrix type liquid crystal display device |
JP4645022B2 (en) | 2003-11-27 | 2011-03-09 | 日本電気株式会社 | Thin film transistor array substrate and active matrix liquid crystal display device |
JP2006178235A (en) | 2004-12-22 | 2006-07-06 | Nec Corp | Thin film transistor array substrate and liquid crystal display device |
JP2011158700A (en) | 2010-02-01 | 2011-08-18 | Seiko Epson Corp | Electro-optical device and electronic apparatus, and method for manufacturing the electro-optical device |
JP5563888B2 (en) | 2010-05-12 | 2014-07-30 | 三菱電機株式会社 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ACTIVE MATRIX SUBSTRATE, AND ELECTRO-OPTICAL DEVICE |
-
2016
- 2016-10-21 US US15/331,007 patent/US10088727B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030025848A1 (en) * | 2001-08-03 | 2003-02-06 | Nec Corporation | TFT array substrate and active-matrix addressing liquid-crystal display device |
US20040149989A1 (en) * | 2003-01-31 | 2004-08-05 | Nec Corporation | Thin film transistor, TFT substrate and liquid crystal display unit |
US20050007512A1 (en) * | 2003-07-11 | 2005-01-13 | Nec Corporation | Thin-film transistor with set trap level densities, and method of manufactures |
US20050078240A1 (en) * | 2003-08-29 | 2005-04-14 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US20120256184A1 (en) * | 2009-12-17 | 2012-10-11 | Sharp Kabushiki Kaisha | Semiconductor device, active matrix substrate and display device |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10254608B2 (en) * | 2015-08-21 | 2019-04-09 | Samsung Display Co., Ltd. | Display device |
CN108535925A (en) * | 2018-03-20 | 2018-09-14 | 厦门天马微电子有限公司 | Display panel and display device |
US20190391424A1 (en) * | 2018-06-20 | 2019-12-26 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US10838263B2 (en) * | 2018-06-20 | 2020-11-17 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US11126039B2 (en) | 2018-06-20 | 2021-09-21 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US11092862B2 (en) | 2018-06-22 | 2021-08-17 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US20210408483A1 (en) * | 2019-01-11 | 2021-12-30 | Japan Display Inc. | Display device |
US11765931B2 (en) * | 2019-01-11 | 2023-09-19 | Japan Display Inc. | Display device having an amount of polymerization initiator for curing the second organic insulating layer and the second organic insulating layer |
US11515338B2 (en) * | 2019-04-16 | 2022-11-29 | Samsung Display Co., Ltd. | Display device having light shielding pattern |
CN109887987A (en) * | 2019-04-17 | 2019-06-14 | 昆山国显光电有限公司 | A kind of array substrate and display module |
US20210013238A1 (en) * | 2019-07-09 | 2021-01-14 | Sharp Kabushiki Kaisha | Active matrix substrate and method for manufacturing same |
US11424274B2 (en) * | 2020-01-30 | 2022-08-23 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
US20210376279A1 (en) * | 2020-06-01 | 2021-12-02 | Samsung Display Co., Ltd. | Display apparatus and electronic apparatus |
CN112164701A (en) * | 2020-09-29 | 2021-01-01 | 厦门天马微电子有限公司 | Array substrate and display panel |
US20220140014A1 (en) * | 2020-11-05 | 2022-05-05 | Samsung Display Co., Ltd. | Display device and electronic apparatus |
Also Published As
Publication number | Publication date |
---|---|
US10088727B2 (en) | 2018-10-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10088727B2 (en) | Liquid crystal device and electronic apparatus | |
JP5834705B2 (en) | Electro-optical device and electronic apparatus | |
JP6566079B1 (en) | Electro-optical device, electronic equipment | |
US20180173064A1 (en) | Electro-optical device and electronic apparatus | |
JP2016218382A (en) | Electro-optical device and electronic apparatus | |
JP5919636B2 (en) | Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device | |
JP2014137526A (en) | Substrate for electro-optic device, electro-optic device, and electronic apparatus | |
JP2018136477A (en) | Electro-optical device and electronic apparatus | |
JP5948777B2 (en) | Liquid crystal device, method for manufacturing liquid crystal device, and electronic apparatus | |
WO2014115499A1 (en) | Electro-optic device, electro-optic device manufacturing method, and electronic device | |
JP2018136478A (en) | Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus | |
JP2015094880A (en) | Electro-optic device and electronic apparatus | |
JP5919890B2 (en) | Electro-optical device and electronic apparatus | |
US9335593B2 (en) | Electro-optic device comprising a data line disposed between a transistor and a capacitor and electronic apparatus | |
JP6044700B2 (en) | Electro-optical device and electronic apparatus | |
JP2017083679A (en) | Display device and electronic apparatus | |
JP5849605B2 (en) | Electro-optical device and electronic apparatus | |
JP2017083678A (en) | Electro-optical device and electronic apparatus | |
JP5754207B2 (en) | Liquid crystal device and electronic device | |
JP6402999B2 (en) | Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus | |
JP2014182251A (en) | Electro-optic device, method for manufacturing electro-optic device, and electronic equipment | |
JP2014092692A (en) | Liquid crystal device and electronic equipment | |
JP7119564B2 (en) | electro-optical device, electronic equipment | |
JP2012252033A (en) | Electro-optical device and electronic apparatus | |
JP2017097086A (en) | Liquid crystal device and electronic apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SEIKO EPSON CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WADA, MASAYUKI;NAKAGAWA, MASASHI;SIGNING DATES FROM 20160819 TO 20160822;REEL/FRAME:040087/0769 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: 138 EAST LCD ADVANCEMENTS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEIKO EPSON CORPORATION;REEL/FRAME:050197/0212 Effective date: 20190725 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |